1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2005, Intec Automation Inc.
4 * Copyright (C) 2014, Freescale Semiconductor, Inc.
7 #include <linux/mtd/spi-nor.h>
11 #define ATMEL_SR_GLOBAL_PROTECT_MASK GENMASK(5, 2)
14 * The Atmel AT25FS010/AT25FS040 parts have some weird configuration for the
15 * block protection bits. We don't support them. But legacy behavior in linux
16 * is to unlock the whole flash array on startup. Therefore, we have to support
17 * exactly this operation.
19 static int at25fs_nor_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
24 static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
28 /* We only support unlocking the whole flash array */
29 if (ofs || len != nor->params->size)
32 /* Write 0x00 to the status register to disable write protection */
33 ret = spi_nor_write_sr_and_check(nor, 0);
35 dev_dbg(nor->dev, "unable to clear BP bits, WP# asserted?\n");
40 static int at25fs_nor_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
45 static const struct spi_nor_locking_ops at25fs_nor_locking_ops = {
46 .lock = at25fs_nor_lock,
47 .unlock = at25fs_nor_unlock,
48 .is_locked = at25fs_nor_is_locked,
51 static int at25fs_nor_late_init(struct spi_nor *nor)
53 nor->params->locking_ops = &at25fs_nor_locking_ops;
58 static const struct spi_nor_fixups at25fs_nor_fixups = {
59 .late_init = at25fs_nor_late_init,
63 * atmel_nor_set_global_protection - Do a Global Protect or Unprotect command
64 * @nor: pointer to 'struct spi_nor'
65 * @ofs: offset in bytes
67 * @is_protect: if true do a Global Protect otherwise it is a Global Unprotect
69 * Return: 0 on success, -error otherwise.
71 static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
72 uint64_t len, bool is_protect)
77 /* We only support locking the whole flash array */
78 if (ofs || len != nor->params->size)
81 ret = spi_nor_read_sr(nor, nor->bouncebuf);
85 sr = nor->bouncebuf[0];
87 /* SRWD bit needs to be cleared, otherwise the protection doesn't change */
90 ret = spi_nor_write_sr_and_check(nor, sr);
92 dev_dbg(nor->dev, "unable to clear SRWD bit, WP# asserted?\n");
98 sr |= ATMEL_SR_GLOBAL_PROTECT_MASK;
100 * Set the SRWD bit again as soon as we are protecting
101 * anything. This will ensure that the WP# pin is working
102 * correctly. By doing this we also behave the same as
103 * spi_nor_sr_lock(), which sets SRWD if any block protection
108 sr &= ~ATMEL_SR_GLOBAL_PROTECT_MASK;
111 nor->bouncebuf[0] = sr;
114 * We cannot use the spi_nor_write_sr_and_check() because this command
115 * isn't really setting any bits, instead it is an pseudo command for
116 * "Global Unprotect" or "Global Protect"
118 return spi_nor_write_sr(nor, nor->bouncebuf, 1);
121 static int atmel_nor_global_protect(struct spi_nor *nor, loff_t ofs,
124 return atmel_nor_set_global_protection(nor, ofs, len, true);
127 static int atmel_nor_global_unprotect(struct spi_nor *nor, loff_t ofs,
130 return atmel_nor_set_global_protection(nor, ofs, len, false);
133 static int atmel_nor_is_global_protected(struct spi_nor *nor, loff_t ofs,
138 if (ofs >= nor->params->size || (ofs + len) > nor->params->size)
141 ret = spi_nor_read_sr(nor, nor->bouncebuf);
145 return ((nor->bouncebuf[0] & ATMEL_SR_GLOBAL_PROTECT_MASK) == ATMEL_SR_GLOBAL_PROTECT_MASK);
148 static const struct spi_nor_locking_ops atmel_nor_global_protection_ops = {
149 .lock = atmel_nor_global_protect,
150 .unlock = atmel_nor_global_unprotect,
151 .is_locked = atmel_nor_is_global_protected,
154 static int atmel_nor_global_protection_late_init(struct spi_nor *nor)
156 nor->params->locking_ops = &atmel_nor_global_protection_ops;
161 static const struct spi_nor_fixups atmel_nor_global_protection_fixups = {
162 .late_init = atmel_nor_global_protection_late_init,
165 static const struct flash_info atmel_nor_parts[] = {
167 .id = SNOR_ID(0x1f, 0x04, 0x00),
170 .no_sfdp_flags = SECT_4K,
172 .id = SNOR_ID(0x1f, 0x25, 0x00),
173 .name = "at45db081d",
175 .no_sfdp_flags = SECT_4K,
177 .id = SNOR_ID(0x1f, 0x42, 0x16),
180 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
182 .id = SNOR_ID(0x1f, 0x44, 0x01),
183 .name = "at25df041a",
185 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
186 .no_sfdp_flags = SECT_4K,
187 .fixups = &atmel_nor_global_protection_fixups,
189 .id = SNOR_ID(0x1f, 0x45, 0x01),
190 .name = "at26df081a",
192 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
193 .no_sfdp_flags = SECT_4K,
194 .fixups = &atmel_nor_global_protection_fixups
196 .id = SNOR_ID(0x1f, 0x46, 0x01),
197 .name = "at26df161a",
199 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
200 .no_sfdp_flags = SECT_4K,
201 .fixups = &atmel_nor_global_protection_fixups
203 .id = SNOR_ID(0x1f, 0x47, 0x00),
206 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
207 .no_sfdp_flags = SECT_4K,
208 .fixups = &atmel_nor_global_protection_fixups
210 .id = SNOR_ID(0x1f, 0x47, 0x01),
211 .name = "at25df321a",
213 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
214 .no_sfdp_flags = SECT_4K,
215 .fixups = &atmel_nor_global_protection_fixups
217 .id = SNOR_ID(0x1f, 0x47, 0x08),
218 .name = "at25ff321a",
219 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
220 .fixups = &atmel_nor_global_protection_fixups
222 .id = SNOR_ID(0x1f, 0x48, 0x00),
225 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
226 .no_sfdp_flags = SECT_4K,
227 .fixups = &atmel_nor_global_protection_fixups
229 .id = SNOR_ID(0x1f, 0x66, 0x01),
231 .sector_size = SZ_32K,
233 .flags = SPI_NOR_HAS_LOCK,
234 .no_sfdp_flags = SECT_4K,
235 .fixups = &at25fs_nor_fixups
237 .id = SNOR_ID(0x1f, 0x66, 0x04),
240 .flags = SPI_NOR_HAS_LOCK,
241 .no_sfdp_flags = SECT_4K,
242 .fixups = &at25fs_nor_fixups
246 const struct spi_nor_manufacturer spi_nor_atmel = {
248 .parts = atmel_nor_parts,
249 .nparts = ARRAY_SIZE(atmel_nor_parts),