2 * SuperH FLCTL nand controller
4 * Copyright (c) 2008 Renesas Solutions Corp.
5 * Copyright (c) 2008 Atom Create Engineering Co., Ltd.
7 * Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/completion.h>
27 #include <linux/delay.h>
28 #include <linux/dmaengine.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/interrupt.h>
33 #include <linux/of_device.h>
34 #include <linux/platform_device.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/sh_dma.h>
37 #include <linux/slab.h>
38 #include <linux/string.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/partitions.h>
43 #include <linux/mtd/sh_flctl.h>
45 static int flctl_4secc_ooblayout_sp_ecc(struct mtd_info *mtd, int section,
46 struct mtd_oob_region *oobregion)
48 struct nand_chip *chip = mtd_to_nand(mtd);
53 oobregion->offset = 0;
54 oobregion->length = chip->ecc.bytes;
59 static int flctl_4secc_ooblayout_sp_free(struct mtd_info *mtd, int section,
60 struct mtd_oob_region *oobregion)
65 oobregion->offset = 12;
66 oobregion->length = 4;
71 static const struct mtd_ooblayout_ops flctl_4secc_oob_smallpage_ops = {
72 .ecc = flctl_4secc_ooblayout_sp_ecc,
73 .free = flctl_4secc_ooblayout_sp_free,
76 static int flctl_4secc_ooblayout_lp_ecc(struct mtd_info *mtd, int section,
77 struct mtd_oob_region *oobregion)
79 struct nand_chip *chip = mtd_to_nand(mtd);
81 if (section >= chip->ecc.steps)
84 oobregion->offset = (section * 16) + 6;
85 oobregion->length = chip->ecc.bytes;
90 static int flctl_4secc_ooblayout_lp_free(struct mtd_info *mtd, int section,
91 struct mtd_oob_region *oobregion)
93 struct nand_chip *chip = mtd_to_nand(mtd);
95 if (section >= chip->ecc.steps)
98 oobregion->offset = section * 16;
99 oobregion->length = 6;
102 oobregion->offset += 2;
103 oobregion->length -= 2;
109 static const struct mtd_ooblayout_ops flctl_4secc_oob_largepage_ops = {
110 .ecc = flctl_4secc_ooblayout_lp_ecc,
111 .free = flctl_4secc_ooblayout_lp_free,
114 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
116 static struct nand_bbt_descr flctl_4secc_smallpage = {
117 .options = NAND_BBT_SCAN2NDPAGE,
120 .pattern = scan_ff_pattern,
123 static struct nand_bbt_descr flctl_4secc_largepage = {
124 .options = NAND_BBT_SCAN2NDPAGE,
127 .pattern = scan_ff_pattern,
130 static void empty_fifo(struct sh_flctl *flctl)
132 writel(flctl->flintdmacr_base | AC1CLR | AC0CLR, FLINTDMACR(flctl));
133 writel(flctl->flintdmacr_base, FLINTDMACR(flctl));
136 static void start_translation(struct sh_flctl *flctl)
138 writeb(TRSTRT, FLTRCR(flctl));
141 static void timeout_error(struct sh_flctl *flctl, const char *str)
143 dev_err(&flctl->pdev->dev, "Timeout occurred in %s\n", str);
146 static void wait_completion(struct sh_flctl *flctl)
148 uint32_t timeout = LOOP_TIMEOUT_MAX;
151 if (readb(FLTRCR(flctl)) & TREND) {
152 writeb(0x0, FLTRCR(flctl));
158 timeout_error(flctl, __func__);
159 writeb(0x0, FLTRCR(flctl));
162 static void flctl_dma_complete(void *param)
164 struct sh_flctl *flctl = param;
166 complete(&flctl->dma_complete);
169 static void flctl_release_dma(struct sh_flctl *flctl)
171 if (flctl->chan_fifo0_rx) {
172 dma_release_channel(flctl->chan_fifo0_rx);
173 flctl->chan_fifo0_rx = NULL;
175 if (flctl->chan_fifo0_tx) {
176 dma_release_channel(flctl->chan_fifo0_tx);
177 flctl->chan_fifo0_tx = NULL;
181 static void flctl_setup_dma(struct sh_flctl *flctl)
184 struct dma_slave_config cfg;
185 struct platform_device *pdev = flctl->pdev;
186 struct sh_flctl_platform_data *pdata = dev_get_platdata(&pdev->dev);
192 if (pdata->slave_id_fifo0_tx <= 0 || pdata->slave_id_fifo0_rx <= 0)
195 /* We can only either use DMA for both Tx and Rx or not use it at all */
197 dma_cap_set(DMA_SLAVE, mask);
199 flctl->chan_fifo0_tx = dma_request_channel(mask, shdma_chan_filter,
200 (void *)(uintptr_t)pdata->slave_id_fifo0_tx);
201 dev_dbg(&pdev->dev, "%s: TX: got channel %p\n", __func__,
202 flctl->chan_fifo0_tx);
204 if (!flctl->chan_fifo0_tx)
207 memset(&cfg, 0, sizeof(cfg));
208 cfg.direction = DMA_MEM_TO_DEV;
209 cfg.dst_addr = flctl->fifo;
211 ret = dmaengine_slave_config(flctl->chan_fifo0_tx, &cfg);
215 flctl->chan_fifo0_rx = dma_request_channel(mask, shdma_chan_filter,
216 (void *)(uintptr_t)pdata->slave_id_fifo0_rx);
217 dev_dbg(&pdev->dev, "%s: RX: got channel %p\n", __func__,
218 flctl->chan_fifo0_rx);
220 if (!flctl->chan_fifo0_rx)
223 cfg.direction = DMA_DEV_TO_MEM;
225 cfg.src_addr = flctl->fifo;
226 ret = dmaengine_slave_config(flctl->chan_fifo0_rx, &cfg);
230 init_completion(&flctl->dma_complete);
235 flctl_release_dma(flctl);
238 static void set_addr(struct mtd_info *mtd, int column, int page_addr)
240 struct sh_flctl *flctl = mtd_to_flctl(mtd);
244 addr = page_addr; /* ERASE1 */
245 } else if (page_addr != -1) {
246 /* SEQIN, READ0, etc.. */
247 if (flctl->chip.options & NAND_BUSWIDTH_16)
249 if (flctl->page_size) {
250 addr = column & 0x0FFF;
251 addr |= (page_addr & 0xff) << 16;
252 addr |= ((page_addr >> 8) & 0xff) << 24;
254 if (flctl->rw_ADRCNT == ADRCNT2_E) {
256 addr2 = (page_addr >> 16) & 0xff;
257 writel(addr2, FLADR2(flctl));
261 addr |= (page_addr & 0xff) << 8;
262 addr |= ((page_addr >> 8) & 0xff) << 16;
263 addr |= ((page_addr >> 16) & 0xff) << 24;
266 writel(addr, FLADR(flctl));
269 static void wait_rfifo_ready(struct sh_flctl *flctl)
271 uint32_t timeout = LOOP_TIMEOUT_MAX;
276 val = readl(FLDTCNTR(flctl)) >> 16;
281 timeout_error(flctl, __func__);
284 static void wait_wfifo_ready(struct sh_flctl *flctl)
286 uint32_t len, timeout = LOOP_TIMEOUT_MAX;
290 len = (readl(FLDTCNTR(flctl)) >> 16) & 0xFF;
295 timeout_error(flctl, __func__);
298 static enum flctl_ecc_res_t wait_recfifo_ready
299 (struct sh_flctl *flctl, int sector_number)
301 uint32_t timeout = LOOP_TIMEOUT_MAX;
302 void __iomem *ecc_reg[4];
304 int state = FL_SUCCESS;
308 * First this loops checks in FLDTCNTR if we are ready to read out the
309 * oob data. This is the case if either all went fine without errors or
310 * if the bottom part of the loop corrected the errors or marked them as
311 * uncorrectable and the controller is given time to push the data into
315 /* check if all is ok and we can read out the OOB */
316 size = readl(FLDTCNTR(flctl)) >> 24;
317 if ((size & 0xFF) == 4)
320 /* check if a correction code has been calculated */
321 if (!(readl(FL4ECCCR(flctl)) & _4ECCEND)) {
323 * either we wait for the fifo to be filled or a
324 * correction pattern is being generated
330 /* check for an uncorrectable error */
331 if (readl(FL4ECCCR(flctl)) & _4ECCFA) {
332 /* check if we face a non-empty page */
333 for (i = 0; i < 512; i++) {
334 if (flctl->done_buff[i] != 0xff) {
335 state = FL_ERROR; /* can't correct */
340 if (state == FL_SUCCESS)
341 dev_dbg(&flctl->pdev->dev,
342 "reading empty sector %d, ecc error ignored\n",
345 writel(0, FL4ECCCR(flctl));
349 /* start error correction */
350 ecc_reg[0] = FL4ECCRESULT0(flctl);
351 ecc_reg[1] = FL4ECCRESULT1(flctl);
352 ecc_reg[2] = FL4ECCRESULT2(flctl);
353 ecc_reg[3] = FL4ECCRESULT3(flctl);
355 for (i = 0; i < 3; i++) {
359 data = readl(ecc_reg[i]);
361 if (flctl->page_size)
362 index = (512 * sector_number) +
367 org = flctl->done_buff[index];
368 flctl->done_buff[index] = org ^ (data & 0xFF);
370 state = FL_REPAIRABLE;
371 writel(0, FL4ECCCR(flctl));
374 timeout_error(flctl, __func__);
375 return FL_TIMEOUT; /* timeout */
378 static void wait_wecfifo_ready(struct sh_flctl *flctl)
380 uint32_t timeout = LOOP_TIMEOUT_MAX;
385 len = (readl(FLDTCNTR(flctl)) >> 24) & 0xFF;
390 timeout_error(flctl, __func__);
393 static int flctl_dma_fifo0_transfer(struct sh_flctl *flctl, unsigned long *buf,
394 int len, enum dma_data_direction dir)
396 struct dma_async_tx_descriptor *desc = NULL;
397 struct dma_chan *chan;
398 enum dma_transfer_direction tr_dir;
403 unsigned long time_left;
405 if (dir == DMA_FROM_DEVICE) {
406 chan = flctl->chan_fifo0_rx;
407 tr_dir = DMA_DEV_TO_MEM;
409 chan = flctl->chan_fifo0_tx;
410 tr_dir = DMA_MEM_TO_DEV;
413 dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
416 desc = dmaengine_prep_slave_single(chan, dma_addr, len,
417 tr_dir, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
420 reg = readl(FLINTDMACR(flctl));
422 writel(reg, FLINTDMACR(flctl));
424 desc->callback = flctl_dma_complete;
425 desc->callback_param = flctl;
426 cookie = dmaengine_submit(desc);
427 if (dma_submit_error(cookie)) {
428 ret = dma_submit_error(cookie);
429 dev_warn(&flctl->pdev->dev,
430 "DMA submit failed, falling back to PIO\n");
434 dma_async_issue_pending(chan);
436 /* DMA failed, fall back to PIO */
437 flctl_release_dma(flctl);
438 dev_warn(&flctl->pdev->dev,
439 "DMA failed, falling back to PIO\n");
445 wait_for_completion_timeout(&flctl->dma_complete,
446 msecs_to_jiffies(3000));
448 if (time_left == 0) {
449 dmaengine_terminate_all(chan);
450 dev_err(&flctl->pdev->dev, "wait_for_completion_timeout\n");
455 reg = readl(FLINTDMACR(flctl));
457 writel(reg, FLINTDMACR(flctl));
459 dma_unmap_single(chan->device->dev, dma_addr, len, dir);
461 /* ret == 0 is success */
465 static void read_datareg(struct sh_flctl *flctl, int offset)
468 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
470 wait_completion(flctl);
472 data = readl(FLDATAR(flctl));
473 *buf = le32_to_cpu(data);
476 static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
479 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
481 len_4align = (rlen + 3) / 4;
483 /* initiate DMA transfer */
484 if (flctl->chan_fifo0_rx && rlen >= 32 &&
485 !flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_FROM_DEVICE))
486 goto convert; /* DMA success */
488 /* do polling transfer */
489 for (i = 0; i < len_4align; i++) {
490 wait_rfifo_ready(flctl);
491 buf[i] = readl(FLDTFIFO(flctl));
495 for (i = 0; i < len_4align; i++)
496 buf[i] = be32_to_cpu(buf[i]);
499 static enum flctl_ecc_res_t read_ecfiforeg
500 (struct sh_flctl *flctl, uint8_t *buff, int sector)
503 enum flctl_ecc_res_t res;
504 unsigned long *ecc_buf = (unsigned long *)buff;
506 res = wait_recfifo_ready(flctl , sector);
508 if (res != FL_ERROR) {
509 for (i = 0; i < 4; i++) {
510 ecc_buf[i] = readl(FLECFIFO(flctl));
511 ecc_buf[i] = be32_to_cpu(ecc_buf[i]);
518 static void write_fiforeg(struct sh_flctl *flctl, int rlen,
522 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
524 len_4align = (rlen + 3) / 4;
525 for (i = 0; i < len_4align; i++) {
526 wait_wfifo_ready(flctl);
527 writel(cpu_to_be32(buf[i]), FLDTFIFO(flctl));
531 static void write_ec_fiforeg(struct sh_flctl *flctl, int rlen,
535 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
537 len_4align = (rlen + 3) / 4;
539 for (i = 0; i < len_4align; i++)
540 buf[i] = cpu_to_be32(buf[i]);
542 /* initiate DMA transfer */
543 if (flctl->chan_fifo0_tx && rlen >= 32 &&
544 !flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_TO_DEVICE))
545 return; /* DMA success */
547 /* do polling transfer */
548 for (i = 0; i < len_4align; i++) {
549 wait_wecfifo_ready(flctl);
550 writel(buf[i], FLECFIFO(flctl));
554 static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val)
556 struct sh_flctl *flctl = mtd_to_flctl(mtd);
557 uint32_t flcmncr_val = flctl->flcmncr_base & ~SEL_16BIT;
558 uint32_t flcmdcr_val, addr_len_bytes = 0;
560 /* Set SNAND bit if page size is 2048byte */
561 if (flctl->page_size)
562 flcmncr_val |= SNAND_E;
564 flcmncr_val &= ~SNAND_E;
566 /* default FLCMDCR val */
567 flcmdcr_val = DOCMD1_E | DOADR_E;
569 /* Set for FLCMDCR */
571 case NAND_CMD_ERASE1:
572 addr_len_bytes = flctl->erase_ADRCNT;
573 flcmdcr_val |= DOCMD2_E;
576 case NAND_CMD_READOOB:
577 case NAND_CMD_RNDOUT:
578 addr_len_bytes = flctl->rw_ADRCNT;
579 flcmdcr_val |= CDSRC_E;
580 if (flctl->chip.options & NAND_BUSWIDTH_16)
581 flcmncr_val |= SEL_16BIT;
584 /* This case is that cmd is READ0 or READ1 or READ00 */
585 flcmdcr_val &= ~DOADR_E; /* ONLY execute 1st cmd */
587 case NAND_CMD_PAGEPROG:
588 addr_len_bytes = flctl->rw_ADRCNT;
589 flcmdcr_val |= DOCMD2_E | CDSRC_E | SELRW;
590 if (flctl->chip.options & NAND_BUSWIDTH_16)
591 flcmncr_val |= SEL_16BIT;
593 case NAND_CMD_READID:
594 flcmncr_val &= ~SNAND_E;
595 flcmdcr_val |= CDSRC_E;
596 addr_len_bytes = ADRCNT_1;
598 case NAND_CMD_STATUS:
600 flcmncr_val &= ~SNAND_E;
601 flcmdcr_val &= ~(DOADR_E | DOSR_E);
607 /* Set address bytes parameter */
608 flcmdcr_val |= addr_len_bytes;
610 /* Now actually write */
611 writel(flcmncr_val, FLCMNCR(flctl));
612 writel(flcmdcr_val, FLCMDCR(flctl));
613 writel(flcmcdr_val, FLCMCDR(flctl));
616 static int flctl_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
617 uint8_t *buf, int oob_required, int page)
619 chip->read_buf(mtd, buf, mtd->writesize);
621 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
625 static int flctl_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
626 const uint8_t *buf, int oob_required,
629 chip->write_buf(mtd, buf, mtd->writesize);
630 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
634 static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr)
636 struct sh_flctl *flctl = mtd_to_flctl(mtd);
637 int sector, page_sectors;
638 enum flctl_ecc_res_t ecc_result;
640 page_sectors = flctl->page_size ? 4 : 1;
642 set_cmd_regs(mtd, NAND_CMD_READ0,
643 (NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
645 writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE | _4ECCCORRECT,
647 writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl));
648 writel(page_addr << 2, FLADR(flctl));
651 start_translation(flctl);
653 for (sector = 0; sector < page_sectors; sector++) {
654 read_fiforeg(flctl, 512, 512 * sector);
656 ecc_result = read_ecfiforeg(flctl,
657 &flctl->done_buff[mtd->writesize + 16 * sector],
660 switch (ecc_result) {
662 dev_info(&flctl->pdev->dev,
663 "applied ecc on page 0x%x", page_addr);
664 mtd->ecc_stats.corrected++;
667 dev_warn(&flctl->pdev->dev,
668 "page 0x%x contains corrupted data\n",
670 mtd->ecc_stats.failed++;
677 wait_completion(flctl);
679 writel(readl(FLCMNCR(flctl)) & ~(ACM_SACCES_MODE | _4ECCCORRECT),
683 static void execmd_read_oob(struct mtd_info *mtd, int page_addr)
685 struct sh_flctl *flctl = mtd_to_flctl(mtd);
686 int page_sectors = flctl->page_size ? 4 : 1;
689 set_cmd_regs(mtd, NAND_CMD_READ0,
690 (NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
694 for (i = 0; i < page_sectors; i++) {
695 set_addr(mtd, (512 + 16) * i + 512 , page_addr);
696 writel(16, FLDTCNTR(flctl));
698 start_translation(flctl);
699 read_fiforeg(flctl, 16, 16 * i);
700 wait_completion(flctl);
704 static void execmd_write_page_sector(struct mtd_info *mtd)
706 struct sh_flctl *flctl = mtd_to_flctl(mtd);
707 int page_addr = flctl->seqin_page_addr;
708 int sector, page_sectors;
710 page_sectors = flctl->page_size ? 4 : 1;
712 set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
713 (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
716 writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE, FLCMNCR(flctl));
717 writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl));
718 writel(page_addr << 2, FLADR(flctl));
719 start_translation(flctl);
721 for (sector = 0; sector < page_sectors; sector++) {
722 write_fiforeg(flctl, 512, 512 * sector);
723 write_ec_fiforeg(flctl, 16, mtd->writesize + 16 * sector);
726 wait_completion(flctl);
727 writel(readl(FLCMNCR(flctl)) & ~ACM_SACCES_MODE, FLCMNCR(flctl));
730 static void execmd_write_oob(struct mtd_info *mtd)
732 struct sh_flctl *flctl = mtd_to_flctl(mtd);
733 int page_addr = flctl->seqin_page_addr;
734 int sector, page_sectors;
736 page_sectors = flctl->page_size ? 4 : 1;
738 set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
739 (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
741 for (sector = 0; sector < page_sectors; sector++) {
743 set_addr(mtd, sector * 528 + 512, page_addr);
744 writel(16, FLDTCNTR(flctl)); /* set read size */
746 start_translation(flctl);
747 write_fiforeg(flctl, 16, 16 * sector);
748 wait_completion(flctl);
752 static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command,
753 int column, int page_addr)
755 struct sh_flctl *flctl = mtd_to_flctl(mtd);
756 uint32_t read_cmd = 0;
758 pm_runtime_get_sync(&flctl->pdev->dev);
760 flctl->read_bytes = 0;
761 if (command != NAND_CMD_PAGEPROG)
768 /* read page with hwecc */
769 execmd_read_page_sector(mtd, page_addr);
772 if (flctl->page_size)
773 set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
776 set_cmd_regs(mtd, command, command);
778 set_addr(mtd, 0, page_addr);
780 flctl->read_bytes = mtd->writesize + mtd->oobsize;
781 if (flctl->chip.options & NAND_BUSWIDTH_16)
783 flctl->index += column;
784 goto read_normal_exit;
786 case NAND_CMD_READOOB:
788 /* read page with hwecc */
789 execmd_read_oob(mtd, page_addr);
793 if (flctl->page_size) {
794 set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
796 set_addr(mtd, mtd->writesize, page_addr);
798 set_cmd_regs(mtd, command, command);
799 set_addr(mtd, 0, page_addr);
801 flctl->read_bytes = mtd->oobsize;
802 goto read_normal_exit;
804 case NAND_CMD_RNDOUT:
808 if (flctl->page_size)
809 set_cmd_regs(mtd, command, (NAND_CMD_RNDOUTSTART << 8)
812 set_cmd_regs(mtd, command, command);
814 set_addr(mtd, column, 0);
816 flctl->read_bytes = mtd->writesize + mtd->oobsize - column;
817 goto read_normal_exit;
819 case NAND_CMD_READID:
820 set_cmd_regs(mtd, command, command);
822 /* READID is always performed using an 8-bit bus */
823 if (flctl->chip.options & NAND_BUSWIDTH_16)
825 set_addr(mtd, column, 0);
827 flctl->read_bytes = 8;
828 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
830 start_translation(flctl);
831 read_fiforeg(flctl, flctl->read_bytes, 0);
832 wait_completion(flctl);
835 case NAND_CMD_ERASE1:
836 flctl->erase1_page_addr = page_addr;
839 case NAND_CMD_ERASE2:
840 set_cmd_regs(mtd, NAND_CMD_ERASE1,
841 (command << 8) | NAND_CMD_ERASE1);
842 set_addr(mtd, -1, flctl->erase1_page_addr);
843 start_translation(flctl);
844 wait_completion(flctl);
848 if (!flctl->page_size) {
849 /* output read command */
850 if (column >= mtd->writesize) {
851 column -= mtd->writesize;
852 read_cmd = NAND_CMD_READOOB;
853 } else if (column < 256) {
854 read_cmd = NAND_CMD_READ0;
857 read_cmd = NAND_CMD_READ1;
860 flctl->seqin_column = column;
861 flctl->seqin_page_addr = page_addr;
862 flctl->seqin_read_cmd = read_cmd;
865 case NAND_CMD_PAGEPROG:
867 if (!flctl->page_size) {
868 set_cmd_regs(mtd, NAND_CMD_SEQIN,
869 flctl->seqin_read_cmd);
870 set_addr(mtd, -1, -1);
871 writel(0, FLDTCNTR(flctl)); /* set 0 size */
872 start_translation(flctl);
873 wait_completion(flctl);
876 /* write page with hwecc */
877 if (flctl->seqin_column == mtd->writesize)
878 execmd_write_oob(mtd);
879 else if (!flctl->seqin_column)
880 execmd_write_page_sector(mtd);
882 printk(KERN_ERR "Invalid address !?\n");
885 set_cmd_regs(mtd, command, (command << 8) | NAND_CMD_SEQIN);
886 set_addr(mtd, flctl->seqin_column, flctl->seqin_page_addr);
887 writel(flctl->index, FLDTCNTR(flctl)); /* set write size */
888 start_translation(flctl);
889 write_fiforeg(flctl, flctl->index, 0);
890 wait_completion(flctl);
893 case NAND_CMD_STATUS:
894 set_cmd_regs(mtd, command, command);
895 set_addr(mtd, -1, -1);
897 flctl->read_bytes = 1;
898 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
899 start_translation(flctl);
900 read_datareg(flctl, 0); /* read and end */
904 set_cmd_regs(mtd, command, command);
905 set_addr(mtd, -1, -1);
907 writel(0, FLDTCNTR(flctl)); /* set 0 size */
908 start_translation(flctl);
909 wait_completion(flctl);
918 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
920 start_translation(flctl);
921 read_fiforeg(flctl, flctl->read_bytes, 0);
922 wait_completion(flctl);
924 pm_runtime_put_sync(&flctl->pdev->dev);
928 static void flctl_select_chip(struct mtd_info *mtd, int chipnr)
930 struct sh_flctl *flctl = mtd_to_flctl(mtd);
935 flctl->flcmncr_base &= ~CE0_ENABLE;
937 pm_runtime_get_sync(&flctl->pdev->dev);
938 writel(flctl->flcmncr_base, FLCMNCR(flctl));
940 if (flctl->qos_request) {
941 dev_pm_qos_remove_request(&flctl->pm_qos);
942 flctl->qos_request = 0;
945 pm_runtime_put_sync(&flctl->pdev->dev);
948 flctl->flcmncr_base |= CE0_ENABLE;
950 if (!flctl->qos_request) {
951 ret = dev_pm_qos_add_request(&flctl->pdev->dev,
953 DEV_PM_QOS_RESUME_LATENCY,
956 dev_err(&flctl->pdev->dev,
957 "PM QoS request failed: %d\n", ret);
958 flctl->qos_request = 1;
962 pm_runtime_get_sync(&flctl->pdev->dev);
963 writel(HOLDEN, FLHOLDCR(flctl));
964 pm_runtime_put_sync(&flctl->pdev->dev);
972 static void flctl_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
974 struct sh_flctl *flctl = mtd_to_flctl(mtd);
976 memcpy(&flctl->done_buff[flctl->index], buf, len);
980 static uint8_t flctl_read_byte(struct mtd_info *mtd)
982 struct sh_flctl *flctl = mtd_to_flctl(mtd);
985 data = flctl->done_buff[flctl->index];
990 static uint16_t flctl_read_word(struct mtd_info *mtd)
992 struct sh_flctl *flctl = mtd_to_flctl(mtd);
993 uint16_t *buf = (uint16_t *)&flctl->done_buff[flctl->index];
999 static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1001 struct sh_flctl *flctl = mtd_to_flctl(mtd);
1003 memcpy(buf, &flctl->done_buff[flctl->index], len);
1004 flctl->index += len;
1007 static int flctl_chip_init_tail(struct mtd_info *mtd)
1009 struct sh_flctl *flctl = mtd_to_flctl(mtd);
1010 struct nand_chip *chip = &flctl->chip;
1012 if (mtd->writesize == 512) {
1013 flctl->page_size = 0;
1014 if (chip->chipsize > (32 << 20)) {
1016 flctl->rw_ADRCNT = ADRCNT_4;
1017 flctl->erase_ADRCNT = ADRCNT_3;
1018 } else if (chip->chipsize > (2 << 16)) {
1019 /* big than 128KB */
1020 flctl->rw_ADRCNT = ADRCNT_3;
1021 flctl->erase_ADRCNT = ADRCNT_2;
1023 flctl->rw_ADRCNT = ADRCNT_2;
1024 flctl->erase_ADRCNT = ADRCNT_1;
1027 flctl->page_size = 1;
1028 if (chip->chipsize > (128 << 20)) {
1029 /* big than 128MB */
1030 flctl->rw_ADRCNT = ADRCNT2_E;
1031 flctl->erase_ADRCNT = ADRCNT_3;
1032 } else if (chip->chipsize > (8 << 16)) {
1033 /* big than 512KB */
1034 flctl->rw_ADRCNT = ADRCNT_4;
1035 flctl->erase_ADRCNT = ADRCNT_2;
1037 flctl->rw_ADRCNT = ADRCNT_3;
1038 flctl->erase_ADRCNT = ADRCNT_1;
1043 if (mtd->writesize == 512) {
1044 mtd_set_ooblayout(mtd, &flctl_4secc_oob_smallpage_ops);
1045 chip->badblock_pattern = &flctl_4secc_smallpage;
1047 mtd_set_ooblayout(mtd, &flctl_4secc_oob_largepage_ops);
1048 chip->badblock_pattern = &flctl_4secc_largepage;
1051 chip->ecc.size = 512;
1052 chip->ecc.bytes = 10;
1053 chip->ecc.strength = 4;
1054 chip->ecc.read_page = flctl_read_page_hwecc;
1055 chip->ecc.write_page = flctl_write_page_hwecc;
1056 chip->ecc.mode = NAND_ECC_HW;
1058 /* 4 symbols ECC enabled */
1059 flctl->flcmncr_base |= _4ECCEN;
1061 chip->ecc.mode = NAND_ECC_SOFT;
1062 chip->ecc.algo = NAND_ECC_HAMMING;
1068 static irqreturn_t flctl_handle_flste(int irq, void *dev_id)
1070 struct sh_flctl *flctl = dev_id;
1072 dev_err(&flctl->pdev->dev, "flste irq: %x\n", readl(FLINTDMACR(flctl)));
1073 writel(flctl->flintdmacr_base, FLINTDMACR(flctl));
1078 struct flctl_soc_config {
1079 unsigned long flcmncr_val;
1080 unsigned has_hwecc:1;
1081 unsigned use_holden:1;
1084 static struct flctl_soc_config flctl_sh7372_config = {
1085 .flcmncr_val = CLK_16B_12L_4H | TYPESEL_SET | SHBUSSEL,
1090 static const struct of_device_id of_flctl_match[] = {
1091 { .compatible = "renesas,shmobile-flctl-sh7372",
1092 .data = &flctl_sh7372_config },
1095 MODULE_DEVICE_TABLE(of, of_flctl_match);
1097 static struct sh_flctl_platform_data *flctl_parse_dt(struct device *dev)
1099 const struct of_device_id *match;
1100 struct flctl_soc_config *config;
1101 struct sh_flctl_platform_data *pdata;
1103 match = of_match_device(of_flctl_match, dev);
1105 config = (struct flctl_soc_config *)match->data;
1107 dev_err(dev, "%s: no OF configuration attached\n", __func__);
1111 pdata = devm_kzalloc(dev, sizeof(struct sh_flctl_platform_data),
1116 /* set SoC specific options */
1117 pdata->flcmncr_val = config->flcmncr_val;
1118 pdata->has_hwecc = config->has_hwecc;
1119 pdata->use_holden = config->use_holden;
1124 static int flctl_probe(struct platform_device *pdev)
1126 struct resource *res;
1127 struct sh_flctl *flctl;
1128 struct mtd_info *flctl_mtd;
1129 struct nand_chip *nand;
1130 struct sh_flctl_platform_data *pdata;
1134 flctl = devm_kzalloc(&pdev->dev, sizeof(struct sh_flctl), GFP_KERNEL);
1138 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1139 flctl->reg = devm_ioremap_resource(&pdev->dev, res);
1140 if (IS_ERR(flctl->reg))
1141 return PTR_ERR(flctl->reg);
1142 flctl->fifo = res->start + 0x24; /* FLDTFIFO */
1144 irq = platform_get_irq(pdev, 0);
1146 dev_err(&pdev->dev, "failed to get flste irq data\n");
1150 ret = devm_request_irq(&pdev->dev, irq, flctl_handle_flste, IRQF_SHARED,
1153 dev_err(&pdev->dev, "request interrupt failed.\n");
1157 if (pdev->dev.of_node)
1158 pdata = flctl_parse_dt(&pdev->dev);
1160 pdata = dev_get_platdata(&pdev->dev);
1163 dev_err(&pdev->dev, "no setup data defined\n");
1167 platform_set_drvdata(pdev, flctl);
1168 nand = &flctl->chip;
1169 flctl_mtd = nand_to_mtd(nand);
1170 nand_set_flash_node(nand, pdev->dev.of_node);
1171 flctl_mtd->dev.parent = &pdev->dev;
1173 flctl->hwecc = pdata->has_hwecc;
1174 flctl->holden = pdata->use_holden;
1175 flctl->flcmncr_base = pdata->flcmncr_val;
1176 flctl->flintdmacr_base = flctl->hwecc ? (STERINTE | ECERB) : STERINTE;
1178 /* Set address of hardware control function */
1179 /* 20 us command delay time */
1180 nand->chip_delay = 20;
1182 nand->read_byte = flctl_read_byte;
1183 nand->read_word = flctl_read_word;
1184 nand->write_buf = flctl_write_buf;
1185 nand->read_buf = flctl_read_buf;
1186 nand->select_chip = flctl_select_chip;
1187 nand->cmdfunc = flctl_cmdfunc;
1189 if (pdata->flcmncr_val & SEL_16BIT)
1190 nand->options |= NAND_BUSWIDTH_16;
1192 pm_runtime_enable(&pdev->dev);
1193 pm_runtime_resume(&pdev->dev);
1195 flctl_setup_dma(flctl);
1197 ret = nand_scan_ident(flctl_mtd, 1, NULL);
1201 if (nand->options & NAND_BUSWIDTH_16) {
1203 * NAND_BUSWIDTH_16 may have been set by nand_scan_ident().
1204 * Add the SEL_16BIT flag in pdata->flcmncr_val and re-assign
1205 * flctl->flcmncr_base to pdata->flcmncr_val.
1207 pdata->flcmncr_val |= SEL_16BIT;
1208 flctl->flcmncr_base = pdata->flcmncr_val;
1211 ret = flctl_chip_init_tail(flctl_mtd);
1215 ret = nand_scan_tail(flctl_mtd);
1219 ret = mtd_device_register(flctl_mtd, pdata->parts, pdata->nr_parts);
1224 flctl_release_dma(flctl);
1225 pm_runtime_disable(&pdev->dev);
1229 static int flctl_remove(struct platform_device *pdev)
1231 struct sh_flctl *flctl = platform_get_drvdata(pdev);
1233 flctl_release_dma(flctl);
1234 nand_release(&flctl->chip);
1235 pm_runtime_disable(&pdev->dev);
1240 static struct platform_driver flctl_driver = {
1241 .remove = flctl_remove,
1244 .of_match_table = of_match_ptr(of_flctl_match),
1248 module_platform_driver_probe(flctl_driver, flctl_probe);
1250 MODULE_LICENSE("GPL");
1251 MODULE_AUTHOR("Yoshihiro Shimoda");
1252 MODULE_DESCRIPTION("SuperH FLCTL driver");
1253 MODULE_ALIAS("platform:sh_flctl");