2 * SuperH FLCTL nand controller
4 * Copyright (c) 2008 Renesas Solutions Corp.
5 * Copyright (c) 2008 Atom Create Engineering Co., Ltd.
7 * Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/completion.h>
27 #include <linux/delay.h>
28 #include <linux/dmaengine.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/interrupt.h>
33 #include <linux/of_device.h>
34 #include <linux/platform_device.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/sh_dma.h>
37 #include <linux/slab.h>
38 #include <linux/string.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/partitions.h>
43 #include <linux/mtd/sh_flctl.h>
45 static int flctl_4secc_ooblayout_sp_ecc(struct mtd_info *mtd, int section,
46 struct mtd_oob_region *oobregion)
48 struct nand_chip *chip = mtd_to_nand(mtd);
53 oobregion->offset = 0;
54 oobregion->length = chip->ecc.bytes;
59 static int flctl_4secc_ooblayout_sp_free(struct mtd_info *mtd, int section,
60 struct mtd_oob_region *oobregion)
65 oobregion->offset = 12;
66 oobregion->length = 4;
71 static const struct mtd_ooblayout_ops flctl_4secc_oob_smallpage_ops = {
72 .ecc = flctl_4secc_ooblayout_sp_ecc,
73 .free = flctl_4secc_ooblayout_sp_free,
76 static int flctl_4secc_ooblayout_lp_ecc(struct mtd_info *mtd, int section,
77 struct mtd_oob_region *oobregion)
79 struct nand_chip *chip = mtd_to_nand(mtd);
81 if (section >= chip->ecc.steps)
84 oobregion->offset = (section * 16) + 6;
85 oobregion->length = chip->ecc.bytes;
90 static int flctl_4secc_ooblayout_lp_free(struct mtd_info *mtd, int section,
91 struct mtd_oob_region *oobregion)
93 struct nand_chip *chip = mtd_to_nand(mtd);
95 if (section >= chip->ecc.steps)
98 oobregion->offset = section * 16;
99 oobregion->length = 6;
102 oobregion->offset += 2;
103 oobregion->length -= 2;
109 static const struct mtd_ooblayout_ops flctl_4secc_oob_largepage_ops = {
110 .ecc = flctl_4secc_ooblayout_lp_ecc,
111 .free = flctl_4secc_ooblayout_lp_free,
114 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
116 static struct nand_bbt_descr flctl_4secc_smallpage = {
117 .options = NAND_BBT_SCAN2NDPAGE,
120 .pattern = scan_ff_pattern,
123 static struct nand_bbt_descr flctl_4secc_largepage = {
124 .options = NAND_BBT_SCAN2NDPAGE,
127 .pattern = scan_ff_pattern,
130 static void empty_fifo(struct sh_flctl *flctl)
132 writel(flctl->flintdmacr_base | AC1CLR | AC0CLR, FLINTDMACR(flctl));
133 writel(flctl->flintdmacr_base, FLINTDMACR(flctl));
136 static void start_translation(struct sh_flctl *flctl)
138 writeb(TRSTRT, FLTRCR(flctl));
141 static void timeout_error(struct sh_flctl *flctl, const char *str)
143 dev_err(&flctl->pdev->dev, "Timeout occurred in %s\n", str);
146 static void wait_completion(struct sh_flctl *flctl)
148 uint32_t timeout = LOOP_TIMEOUT_MAX;
151 if (readb(FLTRCR(flctl)) & TREND) {
152 writeb(0x0, FLTRCR(flctl));
158 timeout_error(flctl, __func__);
159 writeb(0x0, FLTRCR(flctl));
162 static void flctl_dma_complete(void *param)
164 struct sh_flctl *flctl = param;
166 complete(&flctl->dma_complete);
169 static void flctl_release_dma(struct sh_flctl *flctl)
171 if (flctl->chan_fifo0_rx) {
172 dma_release_channel(flctl->chan_fifo0_rx);
173 flctl->chan_fifo0_rx = NULL;
175 if (flctl->chan_fifo0_tx) {
176 dma_release_channel(flctl->chan_fifo0_tx);
177 flctl->chan_fifo0_tx = NULL;
181 static void flctl_setup_dma(struct sh_flctl *flctl)
184 struct dma_slave_config cfg;
185 struct platform_device *pdev = flctl->pdev;
186 struct sh_flctl_platform_data *pdata = dev_get_platdata(&pdev->dev);
192 if (pdata->slave_id_fifo0_tx <= 0 || pdata->slave_id_fifo0_rx <= 0)
195 /* We can only either use DMA for both Tx and Rx or not use it at all */
197 dma_cap_set(DMA_SLAVE, mask);
199 flctl->chan_fifo0_tx = dma_request_channel(mask, shdma_chan_filter,
200 (void *)(uintptr_t)pdata->slave_id_fifo0_tx);
201 dev_dbg(&pdev->dev, "%s: TX: got channel %p\n", __func__,
202 flctl->chan_fifo0_tx);
204 if (!flctl->chan_fifo0_tx)
207 memset(&cfg, 0, sizeof(cfg));
208 cfg.direction = DMA_MEM_TO_DEV;
209 cfg.dst_addr = flctl->fifo;
211 ret = dmaengine_slave_config(flctl->chan_fifo0_tx, &cfg);
215 flctl->chan_fifo0_rx = dma_request_channel(mask, shdma_chan_filter,
216 (void *)(uintptr_t)pdata->slave_id_fifo0_rx);
217 dev_dbg(&pdev->dev, "%s: RX: got channel %p\n", __func__,
218 flctl->chan_fifo0_rx);
220 if (!flctl->chan_fifo0_rx)
223 cfg.direction = DMA_DEV_TO_MEM;
225 cfg.src_addr = flctl->fifo;
226 ret = dmaengine_slave_config(flctl->chan_fifo0_rx, &cfg);
230 init_completion(&flctl->dma_complete);
235 flctl_release_dma(flctl);
238 static void set_addr(struct mtd_info *mtd, int column, int page_addr)
240 struct sh_flctl *flctl = mtd_to_flctl(mtd);
244 addr = page_addr; /* ERASE1 */
245 } else if (page_addr != -1) {
246 /* SEQIN, READ0, etc.. */
247 if (flctl->chip.options & NAND_BUSWIDTH_16)
249 if (flctl->page_size) {
250 addr = column & 0x0FFF;
251 addr |= (page_addr & 0xff) << 16;
252 addr |= ((page_addr >> 8) & 0xff) << 24;
254 if (flctl->rw_ADRCNT == ADRCNT2_E) {
256 addr2 = (page_addr >> 16) & 0xff;
257 writel(addr2, FLADR2(flctl));
261 addr |= (page_addr & 0xff) << 8;
262 addr |= ((page_addr >> 8) & 0xff) << 16;
263 addr |= ((page_addr >> 16) & 0xff) << 24;
266 writel(addr, FLADR(flctl));
269 static void wait_rfifo_ready(struct sh_flctl *flctl)
271 uint32_t timeout = LOOP_TIMEOUT_MAX;
276 val = readl(FLDTCNTR(flctl)) >> 16;
281 timeout_error(flctl, __func__);
284 static void wait_wfifo_ready(struct sh_flctl *flctl)
286 uint32_t len, timeout = LOOP_TIMEOUT_MAX;
290 len = (readl(FLDTCNTR(flctl)) >> 16) & 0xFF;
295 timeout_error(flctl, __func__);
298 static enum flctl_ecc_res_t wait_recfifo_ready
299 (struct sh_flctl *flctl, int sector_number)
301 uint32_t timeout = LOOP_TIMEOUT_MAX;
302 void __iomem *ecc_reg[4];
304 int state = FL_SUCCESS;
308 * First this loops checks in FLDTCNTR if we are ready to read out the
309 * oob data. This is the case if either all went fine without errors or
310 * if the bottom part of the loop corrected the errors or marked them as
311 * uncorrectable and the controller is given time to push the data into
315 /* check if all is ok and we can read out the OOB */
316 size = readl(FLDTCNTR(flctl)) >> 24;
317 if ((size & 0xFF) == 4)
320 /* check if a correction code has been calculated */
321 if (!(readl(FL4ECCCR(flctl)) & _4ECCEND)) {
323 * either we wait for the fifo to be filled or a
324 * correction pattern is being generated
330 /* check for an uncorrectable error */
331 if (readl(FL4ECCCR(flctl)) & _4ECCFA) {
332 /* check if we face a non-empty page */
333 for (i = 0; i < 512; i++) {
334 if (flctl->done_buff[i] != 0xff) {
335 state = FL_ERROR; /* can't correct */
340 if (state == FL_SUCCESS)
341 dev_dbg(&flctl->pdev->dev,
342 "reading empty sector %d, ecc error ignored\n",
345 writel(0, FL4ECCCR(flctl));
349 /* start error correction */
350 ecc_reg[0] = FL4ECCRESULT0(flctl);
351 ecc_reg[1] = FL4ECCRESULT1(flctl);
352 ecc_reg[2] = FL4ECCRESULT2(flctl);
353 ecc_reg[3] = FL4ECCRESULT3(flctl);
355 for (i = 0; i < 3; i++) {
359 data = readl(ecc_reg[i]);
361 if (flctl->page_size)
362 index = (512 * sector_number) +
367 org = flctl->done_buff[index];
368 flctl->done_buff[index] = org ^ (data & 0xFF);
370 state = FL_REPAIRABLE;
371 writel(0, FL4ECCCR(flctl));
374 timeout_error(flctl, __func__);
375 return FL_TIMEOUT; /* timeout */
378 static void wait_wecfifo_ready(struct sh_flctl *flctl)
380 uint32_t timeout = LOOP_TIMEOUT_MAX;
385 len = (readl(FLDTCNTR(flctl)) >> 24) & 0xFF;
390 timeout_error(flctl, __func__);
393 static int flctl_dma_fifo0_transfer(struct sh_flctl *flctl, unsigned long *buf,
394 int len, enum dma_data_direction dir)
396 struct dma_async_tx_descriptor *desc = NULL;
397 struct dma_chan *chan;
398 enum dma_transfer_direction tr_dir;
404 if (dir == DMA_FROM_DEVICE) {
405 chan = flctl->chan_fifo0_rx;
406 tr_dir = DMA_DEV_TO_MEM;
408 chan = flctl->chan_fifo0_tx;
409 tr_dir = DMA_MEM_TO_DEV;
412 dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
415 desc = dmaengine_prep_slave_single(chan, dma_addr, len,
416 tr_dir, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
419 reg = readl(FLINTDMACR(flctl));
421 writel(reg, FLINTDMACR(flctl));
423 desc->callback = flctl_dma_complete;
424 desc->callback_param = flctl;
425 cookie = dmaengine_submit(desc);
426 if (dma_submit_error(cookie)) {
427 ret = dma_submit_error(cookie);
428 dev_warn(&flctl->pdev->dev,
429 "DMA submit failed, falling back to PIO\n");
433 dma_async_issue_pending(chan);
435 /* DMA failed, fall back to PIO */
436 flctl_release_dma(flctl);
437 dev_warn(&flctl->pdev->dev,
438 "DMA failed, falling back to PIO\n");
444 wait_for_completion_timeout(&flctl->dma_complete,
445 msecs_to_jiffies(3000));
448 dmaengine_terminate_all(chan);
449 dev_err(&flctl->pdev->dev, "wait_for_completion_timeout\n");
453 reg = readl(FLINTDMACR(flctl));
455 writel(reg, FLINTDMACR(flctl));
457 dma_unmap_single(chan->device->dev, dma_addr, len, dir);
459 /* ret > 0 is success */
463 static void read_datareg(struct sh_flctl *flctl, int offset)
466 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
468 wait_completion(flctl);
470 data = readl(FLDATAR(flctl));
471 *buf = le32_to_cpu(data);
474 static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
477 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
479 len_4align = (rlen + 3) / 4;
481 /* initiate DMA transfer */
482 if (flctl->chan_fifo0_rx && rlen >= 32 &&
483 flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_FROM_DEVICE) > 0)
484 goto convert; /* DMA success */
486 /* do polling transfer */
487 for (i = 0; i < len_4align; i++) {
488 wait_rfifo_ready(flctl);
489 buf[i] = readl(FLDTFIFO(flctl));
493 for (i = 0; i < len_4align; i++)
494 buf[i] = be32_to_cpu(buf[i]);
497 static enum flctl_ecc_res_t read_ecfiforeg
498 (struct sh_flctl *flctl, uint8_t *buff, int sector)
501 enum flctl_ecc_res_t res;
502 unsigned long *ecc_buf = (unsigned long *)buff;
504 res = wait_recfifo_ready(flctl , sector);
506 if (res != FL_ERROR) {
507 for (i = 0; i < 4; i++) {
508 ecc_buf[i] = readl(FLECFIFO(flctl));
509 ecc_buf[i] = be32_to_cpu(ecc_buf[i]);
516 static void write_fiforeg(struct sh_flctl *flctl, int rlen,
520 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
522 len_4align = (rlen + 3) / 4;
523 for (i = 0; i < len_4align; i++) {
524 wait_wfifo_ready(flctl);
525 writel(cpu_to_be32(buf[i]), FLDTFIFO(flctl));
529 static void write_ec_fiforeg(struct sh_flctl *flctl, int rlen,
533 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
535 len_4align = (rlen + 3) / 4;
537 for (i = 0; i < len_4align; i++)
538 buf[i] = cpu_to_be32(buf[i]);
540 /* initiate DMA transfer */
541 if (flctl->chan_fifo0_tx && rlen >= 32 &&
542 flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_TO_DEVICE) > 0)
543 return; /* DMA success */
545 /* do polling transfer */
546 for (i = 0; i < len_4align; i++) {
547 wait_wecfifo_ready(flctl);
548 writel(buf[i], FLECFIFO(flctl));
552 static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val)
554 struct sh_flctl *flctl = mtd_to_flctl(mtd);
555 uint32_t flcmncr_val = flctl->flcmncr_base & ~SEL_16BIT;
556 uint32_t flcmdcr_val, addr_len_bytes = 0;
558 /* Set SNAND bit if page size is 2048byte */
559 if (flctl->page_size)
560 flcmncr_val |= SNAND_E;
562 flcmncr_val &= ~SNAND_E;
564 /* default FLCMDCR val */
565 flcmdcr_val = DOCMD1_E | DOADR_E;
567 /* Set for FLCMDCR */
569 case NAND_CMD_ERASE1:
570 addr_len_bytes = flctl->erase_ADRCNT;
571 flcmdcr_val |= DOCMD2_E;
574 case NAND_CMD_READOOB:
575 case NAND_CMD_RNDOUT:
576 addr_len_bytes = flctl->rw_ADRCNT;
577 flcmdcr_val |= CDSRC_E;
578 if (flctl->chip.options & NAND_BUSWIDTH_16)
579 flcmncr_val |= SEL_16BIT;
582 /* This case is that cmd is READ0 or READ1 or READ00 */
583 flcmdcr_val &= ~DOADR_E; /* ONLY execute 1st cmd */
585 case NAND_CMD_PAGEPROG:
586 addr_len_bytes = flctl->rw_ADRCNT;
587 flcmdcr_val |= DOCMD2_E | CDSRC_E | SELRW;
588 if (flctl->chip.options & NAND_BUSWIDTH_16)
589 flcmncr_val |= SEL_16BIT;
591 case NAND_CMD_READID:
592 flcmncr_val &= ~SNAND_E;
593 flcmdcr_val |= CDSRC_E;
594 addr_len_bytes = ADRCNT_1;
596 case NAND_CMD_STATUS:
598 flcmncr_val &= ~SNAND_E;
599 flcmdcr_val &= ~(DOADR_E | DOSR_E);
605 /* Set address bytes parameter */
606 flcmdcr_val |= addr_len_bytes;
608 /* Now actually write */
609 writel(flcmncr_val, FLCMNCR(flctl));
610 writel(flcmdcr_val, FLCMDCR(flctl));
611 writel(flcmcdr_val, FLCMCDR(flctl));
614 static int flctl_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
615 uint8_t *buf, int oob_required, int page)
617 chip->read_buf(mtd, buf, mtd->writesize);
619 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
623 static int flctl_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
624 const uint8_t *buf, int oob_required,
627 chip->write_buf(mtd, buf, mtd->writesize);
628 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
632 static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr)
634 struct sh_flctl *flctl = mtd_to_flctl(mtd);
635 int sector, page_sectors;
636 enum flctl_ecc_res_t ecc_result;
638 page_sectors = flctl->page_size ? 4 : 1;
640 set_cmd_regs(mtd, NAND_CMD_READ0,
641 (NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
643 writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE | _4ECCCORRECT,
645 writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl));
646 writel(page_addr << 2, FLADR(flctl));
649 start_translation(flctl);
651 for (sector = 0; sector < page_sectors; sector++) {
652 read_fiforeg(flctl, 512, 512 * sector);
654 ecc_result = read_ecfiforeg(flctl,
655 &flctl->done_buff[mtd->writesize + 16 * sector],
658 switch (ecc_result) {
660 dev_info(&flctl->pdev->dev,
661 "applied ecc on page 0x%x", page_addr);
662 mtd->ecc_stats.corrected++;
665 dev_warn(&flctl->pdev->dev,
666 "page 0x%x contains corrupted data\n",
668 mtd->ecc_stats.failed++;
675 wait_completion(flctl);
677 writel(readl(FLCMNCR(flctl)) & ~(ACM_SACCES_MODE | _4ECCCORRECT),
681 static void execmd_read_oob(struct mtd_info *mtd, int page_addr)
683 struct sh_flctl *flctl = mtd_to_flctl(mtd);
684 int page_sectors = flctl->page_size ? 4 : 1;
687 set_cmd_regs(mtd, NAND_CMD_READ0,
688 (NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
692 for (i = 0; i < page_sectors; i++) {
693 set_addr(mtd, (512 + 16) * i + 512 , page_addr);
694 writel(16, FLDTCNTR(flctl));
696 start_translation(flctl);
697 read_fiforeg(flctl, 16, 16 * i);
698 wait_completion(flctl);
702 static void execmd_write_page_sector(struct mtd_info *mtd)
704 struct sh_flctl *flctl = mtd_to_flctl(mtd);
705 int page_addr = flctl->seqin_page_addr;
706 int sector, page_sectors;
708 page_sectors = flctl->page_size ? 4 : 1;
710 set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
711 (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
714 writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE, FLCMNCR(flctl));
715 writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl));
716 writel(page_addr << 2, FLADR(flctl));
717 start_translation(flctl);
719 for (sector = 0; sector < page_sectors; sector++) {
720 write_fiforeg(flctl, 512, 512 * sector);
721 write_ec_fiforeg(flctl, 16, mtd->writesize + 16 * sector);
724 wait_completion(flctl);
725 writel(readl(FLCMNCR(flctl)) & ~ACM_SACCES_MODE, FLCMNCR(flctl));
728 static void execmd_write_oob(struct mtd_info *mtd)
730 struct sh_flctl *flctl = mtd_to_flctl(mtd);
731 int page_addr = flctl->seqin_page_addr;
732 int sector, page_sectors;
734 page_sectors = flctl->page_size ? 4 : 1;
736 set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
737 (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
739 for (sector = 0; sector < page_sectors; sector++) {
741 set_addr(mtd, sector * 528 + 512, page_addr);
742 writel(16, FLDTCNTR(flctl)); /* set read size */
744 start_translation(flctl);
745 write_fiforeg(flctl, 16, 16 * sector);
746 wait_completion(flctl);
750 static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command,
751 int column, int page_addr)
753 struct sh_flctl *flctl = mtd_to_flctl(mtd);
754 uint32_t read_cmd = 0;
756 pm_runtime_get_sync(&flctl->pdev->dev);
758 flctl->read_bytes = 0;
759 if (command != NAND_CMD_PAGEPROG)
766 /* read page with hwecc */
767 execmd_read_page_sector(mtd, page_addr);
770 if (flctl->page_size)
771 set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
774 set_cmd_regs(mtd, command, command);
776 set_addr(mtd, 0, page_addr);
778 flctl->read_bytes = mtd->writesize + mtd->oobsize;
779 if (flctl->chip.options & NAND_BUSWIDTH_16)
781 flctl->index += column;
782 goto read_normal_exit;
784 case NAND_CMD_READOOB:
786 /* read page with hwecc */
787 execmd_read_oob(mtd, page_addr);
791 if (flctl->page_size) {
792 set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
794 set_addr(mtd, mtd->writesize, page_addr);
796 set_cmd_regs(mtd, command, command);
797 set_addr(mtd, 0, page_addr);
799 flctl->read_bytes = mtd->oobsize;
800 goto read_normal_exit;
802 case NAND_CMD_RNDOUT:
806 if (flctl->page_size)
807 set_cmd_regs(mtd, command, (NAND_CMD_RNDOUTSTART << 8)
810 set_cmd_regs(mtd, command, command);
812 set_addr(mtd, column, 0);
814 flctl->read_bytes = mtd->writesize + mtd->oobsize - column;
815 goto read_normal_exit;
817 case NAND_CMD_READID:
818 set_cmd_regs(mtd, command, command);
820 /* READID is always performed using an 8-bit bus */
821 if (flctl->chip.options & NAND_BUSWIDTH_16)
823 set_addr(mtd, column, 0);
825 flctl->read_bytes = 8;
826 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
828 start_translation(flctl);
829 read_fiforeg(flctl, flctl->read_bytes, 0);
830 wait_completion(flctl);
833 case NAND_CMD_ERASE1:
834 flctl->erase1_page_addr = page_addr;
837 case NAND_CMD_ERASE2:
838 set_cmd_regs(mtd, NAND_CMD_ERASE1,
839 (command << 8) | NAND_CMD_ERASE1);
840 set_addr(mtd, -1, flctl->erase1_page_addr);
841 start_translation(flctl);
842 wait_completion(flctl);
846 if (!flctl->page_size) {
847 /* output read command */
848 if (column >= mtd->writesize) {
849 column -= mtd->writesize;
850 read_cmd = NAND_CMD_READOOB;
851 } else if (column < 256) {
852 read_cmd = NAND_CMD_READ0;
855 read_cmd = NAND_CMD_READ1;
858 flctl->seqin_column = column;
859 flctl->seqin_page_addr = page_addr;
860 flctl->seqin_read_cmd = read_cmd;
863 case NAND_CMD_PAGEPROG:
865 if (!flctl->page_size) {
866 set_cmd_regs(mtd, NAND_CMD_SEQIN,
867 flctl->seqin_read_cmd);
868 set_addr(mtd, -1, -1);
869 writel(0, FLDTCNTR(flctl)); /* set 0 size */
870 start_translation(flctl);
871 wait_completion(flctl);
874 /* write page with hwecc */
875 if (flctl->seqin_column == mtd->writesize)
876 execmd_write_oob(mtd);
877 else if (!flctl->seqin_column)
878 execmd_write_page_sector(mtd);
880 printk(KERN_ERR "Invalid address !?\n");
883 set_cmd_regs(mtd, command, (command << 8) | NAND_CMD_SEQIN);
884 set_addr(mtd, flctl->seqin_column, flctl->seqin_page_addr);
885 writel(flctl->index, FLDTCNTR(flctl)); /* set write size */
886 start_translation(flctl);
887 write_fiforeg(flctl, flctl->index, 0);
888 wait_completion(flctl);
891 case NAND_CMD_STATUS:
892 set_cmd_regs(mtd, command, command);
893 set_addr(mtd, -1, -1);
895 flctl->read_bytes = 1;
896 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
897 start_translation(flctl);
898 read_datareg(flctl, 0); /* read and end */
902 set_cmd_regs(mtd, command, command);
903 set_addr(mtd, -1, -1);
905 writel(0, FLDTCNTR(flctl)); /* set 0 size */
906 start_translation(flctl);
907 wait_completion(flctl);
916 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
918 start_translation(flctl);
919 read_fiforeg(flctl, flctl->read_bytes, 0);
920 wait_completion(flctl);
922 pm_runtime_put_sync(&flctl->pdev->dev);
926 static void flctl_select_chip(struct mtd_info *mtd, int chipnr)
928 struct sh_flctl *flctl = mtd_to_flctl(mtd);
933 flctl->flcmncr_base &= ~CE0_ENABLE;
935 pm_runtime_get_sync(&flctl->pdev->dev);
936 writel(flctl->flcmncr_base, FLCMNCR(flctl));
938 if (flctl->qos_request) {
939 dev_pm_qos_remove_request(&flctl->pm_qos);
940 flctl->qos_request = 0;
943 pm_runtime_put_sync(&flctl->pdev->dev);
946 flctl->flcmncr_base |= CE0_ENABLE;
948 if (!flctl->qos_request) {
949 ret = dev_pm_qos_add_request(&flctl->pdev->dev,
951 DEV_PM_QOS_RESUME_LATENCY,
954 dev_err(&flctl->pdev->dev,
955 "PM QoS request failed: %d\n", ret);
956 flctl->qos_request = 1;
960 pm_runtime_get_sync(&flctl->pdev->dev);
961 writel(HOLDEN, FLHOLDCR(flctl));
962 pm_runtime_put_sync(&flctl->pdev->dev);
970 static void flctl_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
972 struct sh_flctl *flctl = mtd_to_flctl(mtd);
974 memcpy(&flctl->done_buff[flctl->index], buf, len);
978 static uint8_t flctl_read_byte(struct mtd_info *mtd)
980 struct sh_flctl *flctl = mtd_to_flctl(mtd);
983 data = flctl->done_buff[flctl->index];
988 static uint16_t flctl_read_word(struct mtd_info *mtd)
990 struct sh_flctl *flctl = mtd_to_flctl(mtd);
991 uint16_t *buf = (uint16_t *)&flctl->done_buff[flctl->index];
997 static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
999 struct sh_flctl *flctl = mtd_to_flctl(mtd);
1001 memcpy(buf, &flctl->done_buff[flctl->index], len);
1002 flctl->index += len;
1005 static int flctl_chip_init_tail(struct mtd_info *mtd)
1007 struct sh_flctl *flctl = mtd_to_flctl(mtd);
1008 struct nand_chip *chip = &flctl->chip;
1010 if (mtd->writesize == 512) {
1011 flctl->page_size = 0;
1012 if (chip->chipsize > (32 << 20)) {
1014 flctl->rw_ADRCNT = ADRCNT_4;
1015 flctl->erase_ADRCNT = ADRCNT_3;
1016 } else if (chip->chipsize > (2 << 16)) {
1017 /* big than 128KB */
1018 flctl->rw_ADRCNT = ADRCNT_3;
1019 flctl->erase_ADRCNT = ADRCNT_2;
1021 flctl->rw_ADRCNT = ADRCNT_2;
1022 flctl->erase_ADRCNT = ADRCNT_1;
1025 flctl->page_size = 1;
1026 if (chip->chipsize > (128 << 20)) {
1027 /* big than 128MB */
1028 flctl->rw_ADRCNT = ADRCNT2_E;
1029 flctl->erase_ADRCNT = ADRCNT_3;
1030 } else if (chip->chipsize > (8 << 16)) {
1031 /* big than 512KB */
1032 flctl->rw_ADRCNT = ADRCNT_4;
1033 flctl->erase_ADRCNT = ADRCNT_2;
1035 flctl->rw_ADRCNT = ADRCNT_3;
1036 flctl->erase_ADRCNT = ADRCNT_1;
1041 if (mtd->writesize == 512) {
1042 mtd_set_ooblayout(mtd, &flctl_4secc_oob_smallpage_ops);
1043 chip->badblock_pattern = &flctl_4secc_smallpage;
1045 mtd_set_ooblayout(mtd, &flctl_4secc_oob_largepage_ops);
1046 chip->badblock_pattern = &flctl_4secc_largepage;
1049 chip->ecc.size = 512;
1050 chip->ecc.bytes = 10;
1051 chip->ecc.strength = 4;
1052 chip->ecc.read_page = flctl_read_page_hwecc;
1053 chip->ecc.write_page = flctl_write_page_hwecc;
1054 chip->ecc.mode = NAND_ECC_HW;
1056 /* 4 symbols ECC enabled */
1057 flctl->flcmncr_base |= _4ECCEN;
1059 chip->ecc.mode = NAND_ECC_SOFT;
1060 chip->ecc.algo = NAND_ECC_HAMMING;
1066 static irqreturn_t flctl_handle_flste(int irq, void *dev_id)
1068 struct sh_flctl *flctl = dev_id;
1070 dev_err(&flctl->pdev->dev, "flste irq: %x\n", readl(FLINTDMACR(flctl)));
1071 writel(flctl->flintdmacr_base, FLINTDMACR(flctl));
1076 struct flctl_soc_config {
1077 unsigned long flcmncr_val;
1078 unsigned has_hwecc:1;
1079 unsigned use_holden:1;
1082 static struct flctl_soc_config flctl_sh7372_config = {
1083 .flcmncr_val = CLK_16B_12L_4H | TYPESEL_SET | SHBUSSEL,
1088 static const struct of_device_id of_flctl_match[] = {
1089 { .compatible = "renesas,shmobile-flctl-sh7372",
1090 .data = &flctl_sh7372_config },
1093 MODULE_DEVICE_TABLE(of, of_flctl_match);
1095 static struct sh_flctl_platform_data *flctl_parse_dt(struct device *dev)
1097 const struct of_device_id *match;
1098 struct flctl_soc_config *config;
1099 struct sh_flctl_platform_data *pdata;
1101 match = of_match_device(of_flctl_match, dev);
1103 config = (struct flctl_soc_config *)match->data;
1105 dev_err(dev, "%s: no OF configuration attached\n", __func__);
1109 pdata = devm_kzalloc(dev, sizeof(struct sh_flctl_platform_data),
1114 /* set SoC specific options */
1115 pdata->flcmncr_val = config->flcmncr_val;
1116 pdata->has_hwecc = config->has_hwecc;
1117 pdata->use_holden = config->use_holden;
1122 static int flctl_probe(struct platform_device *pdev)
1124 struct resource *res;
1125 struct sh_flctl *flctl;
1126 struct mtd_info *flctl_mtd;
1127 struct nand_chip *nand;
1128 struct sh_flctl_platform_data *pdata;
1132 flctl = devm_kzalloc(&pdev->dev, sizeof(struct sh_flctl), GFP_KERNEL);
1136 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1137 flctl->reg = devm_ioremap_resource(&pdev->dev, res);
1138 if (IS_ERR(flctl->reg))
1139 return PTR_ERR(flctl->reg);
1140 flctl->fifo = res->start + 0x24; /* FLDTFIFO */
1142 irq = platform_get_irq(pdev, 0);
1144 dev_err(&pdev->dev, "failed to get flste irq data\n");
1148 ret = devm_request_irq(&pdev->dev, irq, flctl_handle_flste, IRQF_SHARED,
1151 dev_err(&pdev->dev, "request interrupt failed.\n");
1155 if (pdev->dev.of_node)
1156 pdata = flctl_parse_dt(&pdev->dev);
1158 pdata = dev_get_platdata(&pdev->dev);
1161 dev_err(&pdev->dev, "no setup data defined\n");
1165 platform_set_drvdata(pdev, flctl);
1166 nand = &flctl->chip;
1167 flctl_mtd = nand_to_mtd(nand);
1168 nand_set_flash_node(nand, pdev->dev.of_node);
1169 flctl_mtd->dev.parent = &pdev->dev;
1171 flctl->hwecc = pdata->has_hwecc;
1172 flctl->holden = pdata->use_holden;
1173 flctl->flcmncr_base = pdata->flcmncr_val;
1174 flctl->flintdmacr_base = flctl->hwecc ? (STERINTE | ECERB) : STERINTE;
1176 /* Set address of hardware control function */
1177 /* 20 us command delay time */
1178 nand->chip_delay = 20;
1180 nand->read_byte = flctl_read_byte;
1181 nand->read_word = flctl_read_word;
1182 nand->write_buf = flctl_write_buf;
1183 nand->read_buf = flctl_read_buf;
1184 nand->select_chip = flctl_select_chip;
1185 nand->cmdfunc = flctl_cmdfunc;
1187 if (pdata->flcmncr_val & SEL_16BIT)
1188 nand->options |= NAND_BUSWIDTH_16;
1190 pm_runtime_enable(&pdev->dev);
1191 pm_runtime_resume(&pdev->dev);
1193 flctl_setup_dma(flctl);
1195 ret = nand_scan_ident(flctl_mtd, 1, NULL);
1199 if (nand->options & NAND_BUSWIDTH_16) {
1201 * NAND_BUSWIDTH_16 may have been set by nand_scan_ident().
1202 * Add the SEL_16BIT flag in pdata->flcmncr_val and re-assign
1203 * flctl->flcmncr_base to pdata->flcmncr_val.
1205 pdata->flcmncr_val |= SEL_16BIT;
1206 flctl->flcmncr_base = pdata->flcmncr_val;
1209 ret = flctl_chip_init_tail(flctl_mtd);
1213 ret = nand_scan_tail(flctl_mtd);
1217 ret = mtd_device_register(flctl_mtd, pdata->parts, pdata->nr_parts);
1222 flctl_release_dma(flctl);
1223 pm_runtime_disable(&pdev->dev);
1227 static int flctl_remove(struct platform_device *pdev)
1229 struct sh_flctl *flctl = platform_get_drvdata(pdev);
1231 flctl_release_dma(flctl);
1232 nand_release(&flctl->chip);
1233 pm_runtime_disable(&pdev->dev);
1238 static struct platform_driver flctl_driver = {
1239 .remove = flctl_remove,
1242 .of_match_table = of_match_ptr(of_flctl_match),
1246 module_platform_driver_probe(flctl_driver, flctl_probe);
1248 MODULE_LICENSE("GPL");
1249 MODULE_AUTHOR("Yoshihiro Shimoda");
1250 MODULE_DESCRIPTION("SuperH FLCTL driver");
1251 MODULE_ALIAS("platform:sh_flctl");