1 /* linux/drivers/mtd/nand/s3c2410.c
3 * Copyright © 2004-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
7 * Samsung S3C2410/S3C2440/S3C2412 NAND driver
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #define pr_fmt(fmt) "nand-s3c2410: " fmt
26 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
30 #include <linux/module.h>
31 #include <linux/types.h>
32 #include <linux/kernel.h>
33 #include <linux/string.h>
35 #include <linux/ioport.h>
36 #include <linux/platform_device.h>
37 #include <linux/delay.h>
38 #include <linux/err.h>
39 #include <linux/slab.h>
40 #include <linux/clk.h>
41 #include <linux/cpufreq.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
46 #include <linux/mtd/partitions.h>
48 #include <linux/platform_data/mtd-nand-s3c2410.h>
50 #define S3C2410_NFREG(x) (x)
52 #define S3C2410_NFCONF S3C2410_NFREG(0x00)
53 #define S3C2410_NFCMD S3C2410_NFREG(0x04)
54 #define S3C2410_NFADDR S3C2410_NFREG(0x08)
55 #define S3C2410_NFDATA S3C2410_NFREG(0x0C)
56 #define S3C2410_NFSTAT S3C2410_NFREG(0x10)
57 #define S3C2410_NFECC S3C2410_NFREG(0x14)
58 #define S3C2440_NFCONT S3C2410_NFREG(0x04)
59 #define S3C2440_NFCMD S3C2410_NFREG(0x08)
60 #define S3C2440_NFADDR S3C2410_NFREG(0x0C)
61 #define S3C2440_NFDATA S3C2410_NFREG(0x10)
62 #define S3C2440_NFSTAT S3C2410_NFREG(0x20)
63 #define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
64 #define S3C2412_NFSTAT S3C2410_NFREG(0x28)
65 #define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
66 #define S3C2410_NFCONF_EN (1<<15)
67 #define S3C2410_NFCONF_INITECC (1<<12)
68 #define S3C2410_NFCONF_nFCE (1<<11)
69 #define S3C2410_NFCONF_TACLS(x) ((x)<<8)
70 #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
71 #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
72 #define S3C2410_NFSTAT_BUSY (1<<0)
73 #define S3C2440_NFCONF_TACLS(x) ((x)<<12)
74 #define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
75 #define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
76 #define S3C2440_NFCONT_INITECC (1<<4)
77 #define S3C2440_NFCONT_nFCE (1<<1)
78 #define S3C2440_NFCONT_ENABLE (1<<0)
79 #define S3C2440_NFSTAT_READY (1<<0)
80 #define S3C2412_NFCONF_NANDBOOT (1<<31)
81 #define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
82 #define S3C2412_NFCONT_nFCE0 (1<<1)
83 #define S3C2412_NFSTAT_READY (1<<0)
85 /* new oob placement block for use with hardware ecc generation
87 static int s3c2410_ooblayout_ecc(struct mtd_info *mtd, int section,
88 struct mtd_oob_region *oobregion)
93 oobregion->offset = 0;
94 oobregion->length = 3;
99 static int s3c2410_ooblayout_free(struct mtd_info *mtd, int section,
100 struct mtd_oob_region *oobregion)
105 oobregion->offset = 8;
106 oobregion->length = 8;
111 static const struct mtd_ooblayout_ops s3c2410_ooblayout_ops = {
112 .ecc = s3c2410_ooblayout_ecc,
113 .free = s3c2410_ooblayout_free,
116 /* controller and mtd information */
118 struct s3c2410_nand_info;
121 * struct s3c2410_nand_mtd - driver MTD structure
122 * @mtd: The MTD instance to pass to the MTD layer.
123 * @chip: The NAND chip information.
124 * @set: The platform information supplied for this set of NAND chips.
125 * @info: Link back to the hardware information.
126 * @scan_res: The result from calling nand_scan_ident().
128 struct s3c2410_nand_mtd {
129 struct nand_chip chip;
130 struct s3c2410_nand_set *set;
131 struct s3c2410_nand_info *info;
141 enum s3c_nand_clk_state {
147 /* overview of the s3c2410 nand state */
150 * struct s3c2410_nand_info - NAND controller state.
151 * @mtds: An array of MTD instances on this controoler.
152 * @platform: The platform data for this board.
153 * @device: The platform device we bound to.
154 * @clk: The clock resource for this controller.
155 * @regs: The area mapped for the hardware registers.
156 * @sel_reg: Pointer to the register controlling the NAND selection.
157 * @sel_bit: The bit in @sel_reg to select the NAND chip.
158 * @mtd_count: The number of MTDs created from this controller.
159 * @save_sel: The contents of @sel_reg to be saved over suspend.
160 * @clk_rate: The clock rate from @clk.
161 * @clk_state: The current clock state.
162 * @cpu_type: The exact type of this controller.
164 struct s3c2410_nand_info {
166 struct nand_hw_control controller;
167 struct s3c2410_nand_mtd *mtds;
168 struct s3c2410_platform_nand *platform;
171 struct device *device;
174 void __iomem *sel_reg;
177 unsigned long save_sel;
178 unsigned long clk_rate;
179 enum s3c_nand_clk_state clk_state;
181 enum s3c_cpu_type cpu_type;
183 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
184 struct notifier_block freq_transition;
188 /* conversion functions */
190 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
192 return container_of(mtd_to_nand(mtd), struct s3c2410_nand_mtd,
196 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
198 return s3c2410_nand_mtd_toours(mtd)->info;
201 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
203 return platform_get_drvdata(dev);
206 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
208 return dev_get_platdata(&dev->dev);
211 static inline int allow_clk_suspend(struct s3c2410_nand_info *info)
213 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
221 * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock.
222 * @info: The controller instance.
223 * @new_state: State to which clock should be set.
225 static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info,
226 enum s3c_nand_clk_state new_state)
228 if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND)
231 if (info->clk_state == CLOCK_ENABLE) {
232 if (new_state != CLOCK_ENABLE)
233 clk_disable_unprepare(info->clk);
235 if (new_state == CLOCK_ENABLE)
236 clk_prepare_enable(info->clk);
239 info->clk_state = new_state;
242 /* timing calculations */
244 #define NS_IN_KHZ 1000000
247 * s3c_nand_calc_rate - calculate timing data.
248 * @wanted: The cycle time in nanoseconds.
249 * @clk: The clock rate in kHz.
250 * @max: The maximum divider value.
252 * Calculate the timing value from the given parameters.
254 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
258 result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ);
260 pr_debug("result %d from %ld, %d\n", result, clk, wanted);
263 pr_err("%d ns is too big for current clock rate %ld\n",
274 #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
276 /* controller setup */
279 * s3c2410_nand_setrate - setup controller timing information.
280 * @info: The controller instance.
282 * Given the information supplied by the platform, calculate and set
283 * the necessary timing registers in the hardware to generate the
284 * necessary timing cycles to the hardware.
286 static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
288 struct s3c2410_platform_nand *plat = info->platform;
289 int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
290 int tacls, twrph0, twrph1;
291 unsigned long clkrate = clk_get_rate(info->clk);
292 unsigned long uninitialized_var(set), cfg, uninitialized_var(mask);
295 /* calculate the timing information for the controller */
297 info->clk_rate = clkrate;
298 clkrate /= 1000; /* turn clock into kHz for ease of use */
301 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
302 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
303 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
305 /* default timings */
311 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
312 dev_err(info->device, "cannot get suitable timings\n");
316 dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
317 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate),
318 twrph1, to_ns(twrph1, clkrate));
320 switch (info->cpu_type) {
322 mask = (S3C2410_NFCONF_TACLS(3) |
323 S3C2410_NFCONF_TWRPH0(7) |
324 S3C2410_NFCONF_TWRPH1(7));
325 set = S3C2410_NFCONF_EN;
326 set |= S3C2410_NFCONF_TACLS(tacls - 1);
327 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
328 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
333 mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) |
334 S3C2440_NFCONF_TWRPH0(7) |
335 S3C2440_NFCONF_TWRPH1(7));
337 set = S3C2440_NFCONF_TACLS(tacls - 1);
338 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
339 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
346 local_irq_save(flags);
348 cfg = readl(info->regs + S3C2410_NFCONF);
351 writel(cfg, info->regs + S3C2410_NFCONF);
353 local_irq_restore(flags);
355 dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
361 * s3c2410_nand_inithw - basic hardware initialisation
362 * @info: The hardware state.
364 * Do the basic initialisation of the hardware, using s3c2410_nand_setrate()
365 * to setup the hardware access speeds and set the controller to be enabled.
367 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
371 ret = s3c2410_nand_setrate(info);
375 switch (info->cpu_type) {
382 /* enable the controller and de-assert nFCE */
384 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
391 * s3c2410_nand_select_chip - select the given nand chip
392 * @mtd: The MTD instance for this chip.
393 * @chip: The chip number.
395 * This is called by the MTD layer to either select a given chip for the
396 * @mtd instance, or to indicate that the access has finished and the
397 * chip can be de-selected.
399 * The routine ensures that the nFCE line is correctly setup, and any
400 * platform specific selection code is called to route nFCE to the specific
403 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
405 struct s3c2410_nand_info *info;
406 struct s3c2410_nand_mtd *nmtd;
407 struct nand_chip *this = mtd_to_nand(mtd);
410 nmtd = nand_get_controller_data(this);
414 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
416 cur = readl(info->sel_reg);
419 cur |= info->sel_bit;
421 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
422 dev_err(info->device, "invalid chip %d\n", chip);
426 if (info->platform != NULL) {
427 if (info->platform->select_chip != NULL)
428 (info->platform->select_chip) (nmtd->set, chip);
431 cur &= ~info->sel_bit;
434 writel(cur, info->sel_reg);
437 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
440 /* s3c2410_nand_hwcontrol
442 * Issue command and address cycles to the chip
445 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
448 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
450 if (cmd == NAND_CMD_NONE)
454 writeb(cmd, info->regs + S3C2410_NFCMD);
456 writeb(cmd, info->regs + S3C2410_NFADDR);
459 /* command and control functions */
461 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
464 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
466 if (cmd == NAND_CMD_NONE)
470 writeb(cmd, info->regs + S3C2440_NFCMD);
472 writeb(cmd, info->regs + S3C2440_NFADDR);
475 /* s3c2410_nand_devready()
477 * returns 0 if the nand is busy, 1 if it is ready
480 static int s3c2410_nand_devready(struct mtd_info *mtd)
482 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
483 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
486 static int s3c2440_nand_devready(struct mtd_info *mtd)
488 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
489 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
492 static int s3c2412_nand_devready(struct mtd_info *mtd)
494 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
495 return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
498 /* ECC handling functions */
500 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
501 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
502 u_char *read_ecc, u_char *calc_ecc)
504 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
505 unsigned int diff0, diff1, diff2;
506 unsigned int bit, byte;
508 pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
510 diff0 = read_ecc[0] ^ calc_ecc[0];
511 diff1 = read_ecc[1] ^ calc_ecc[1];
512 diff2 = read_ecc[2] ^ calc_ecc[2];
514 pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n",
515 __func__, 3, read_ecc, 3, calc_ecc,
516 diff0, diff1, diff2);
518 if (diff0 == 0 && diff1 == 0 && diff2 == 0)
519 return 0; /* ECC is ok */
521 /* sometimes people do not think about using the ECC, so check
522 * to see if we have an 0xff,0xff,0xff read ECC and then ignore
523 * the error, on the assumption that this is an un-eccd page.
525 if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
526 && info->platform->ignore_unset_ecc)
529 /* Can we correct this ECC (ie, one row and column change).
530 * Note, this is similar to the 256 error code on smartmedia */
532 if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
533 ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
534 ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
535 /* calculate the bit position of the error */
537 bit = ((diff2 >> 3) & 1) |
541 /* calculate the byte position of the error */
543 byte = ((diff2 << 7) & 0x100) |
544 ((diff1 << 0) & 0x80) |
545 ((diff1 << 1) & 0x40) |
546 ((diff1 << 2) & 0x20) |
547 ((diff1 << 3) & 0x10) |
548 ((diff0 >> 4) & 0x08) |
549 ((diff0 >> 3) & 0x04) |
550 ((diff0 >> 2) & 0x02) |
551 ((diff0 >> 1) & 0x01);
553 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
556 dat[byte] ^= (1 << bit);
560 /* if there is only one bit difference in the ECC, then
561 * one of only a row or column parity has changed, which
562 * means the error is most probably in the ECC itself */
564 diff0 |= (diff1 << 8);
565 diff0 |= (diff2 << 16);
567 /* equal to "(diff0 & ~(1 << __ffs(diff0)))" */
568 if ((diff0 & (diff0 - 1)) == 0)
576 * These allow the s3c2410 and s3c2440 to use the controller's ECC
577 * generator block to ECC the data as it passes through]
580 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
582 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
585 ctrl = readl(info->regs + S3C2410_NFCONF);
586 ctrl |= S3C2410_NFCONF_INITECC;
587 writel(ctrl, info->regs + S3C2410_NFCONF);
590 static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
592 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
595 ctrl = readl(info->regs + S3C2440_NFCONT);
596 writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC,
597 info->regs + S3C2440_NFCONT);
600 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
602 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
605 ctrl = readl(info->regs + S3C2440_NFCONT);
606 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
609 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
612 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
614 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
615 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
616 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
618 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
623 static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
626 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
627 unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
630 ecc_code[1] = ecc >> 8;
631 ecc_code[2] = ecc >> 16;
633 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
638 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
641 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
642 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
645 ecc_code[1] = ecc >> 8;
646 ecc_code[2] = ecc >> 16;
648 pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
654 /* over-ride the standard functions for a little more speed. We can
655 * use read/write block to move the data buffers to/from the controller
658 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
660 struct nand_chip *this = mtd_to_nand(mtd);
661 readsb(this->IO_ADDR_R, buf, len);
664 static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
666 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
668 readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);
670 /* cleanup if we've got less than a word to do */
674 for (; len & 3; len--)
675 *buf++ = readb(info->regs + S3C2440_NFDATA);
679 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
682 struct nand_chip *this = mtd_to_nand(mtd);
683 writesb(this->IO_ADDR_W, buf, len);
686 static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
689 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
691 writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);
693 /* cleanup any fractional write */
697 for (; len & 3; len--, buf++)
698 writeb(*buf, info->regs + S3C2440_NFDATA);
702 /* cpufreq driver support */
704 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
706 static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
707 unsigned long val, void *data)
709 struct s3c2410_nand_info *info;
710 unsigned long newclk;
712 info = container_of(nb, struct s3c2410_nand_info, freq_transition);
713 newclk = clk_get_rate(info->clk);
715 if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
716 (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
717 s3c2410_nand_setrate(info);
723 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
725 info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
727 return cpufreq_register_notifier(&info->freq_transition,
728 CPUFREQ_TRANSITION_NOTIFIER);
732 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
734 cpufreq_unregister_notifier(&info->freq_transition,
735 CPUFREQ_TRANSITION_NOTIFIER);
739 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
745 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
750 /* device management functions */
752 static int s3c24xx_nand_remove(struct platform_device *pdev)
754 struct s3c2410_nand_info *info = to_nand_info(pdev);
759 s3c2410_nand_cpufreq_deregister(info);
761 /* Release all our mtds and their partitions, then go through
762 * freeing the resources used
765 if (info->mtds != NULL) {
766 struct s3c2410_nand_mtd *ptr = info->mtds;
769 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
770 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
771 nand_release(&ptr->chip);
775 /* free the common resources */
777 if (!IS_ERR(info->clk))
778 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
783 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
784 struct s3c2410_nand_mtd *mtd,
785 struct s3c2410_nand_set *set)
788 struct mtd_info *mtdinfo = nand_to_mtd(&mtd->chip);
790 mtdinfo->name = set->name;
792 return mtd_device_parse_register(mtdinfo, NULL, NULL,
793 set->partitions, set->nr_partitions);
800 * s3c2410_nand_init_chip - initialise a single instance of an chip
801 * @info: The base NAND controller the chip is on.
802 * @nmtd: The new controller MTD instance to fill in.
803 * @set: The information passed from the board specific platform data.
805 * Initialise the given @nmtd from the information in @info and @set. This
806 * readies the structure for use with the MTD layer functions by ensuring
807 * all pointers are setup and the necessary control routines selected.
809 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
810 struct s3c2410_nand_mtd *nmtd,
811 struct s3c2410_nand_set *set)
813 struct nand_chip *chip = &nmtd->chip;
814 void __iomem *regs = info->regs;
816 chip->write_buf = s3c2410_nand_write_buf;
817 chip->read_buf = s3c2410_nand_read_buf;
818 chip->select_chip = s3c2410_nand_select_chip;
819 chip->chip_delay = 50;
820 nand_set_controller_data(chip, nmtd);
821 chip->options = set->options;
822 chip->controller = &info->controller;
824 switch (info->cpu_type) {
826 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
827 info->sel_reg = regs + S3C2410_NFCONF;
828 info->sel_bit = S3C2410_NFCONF_nFCE;
829 chip->cmd_ctrl = s3c2410_nand_hwcontrol;
830 chip->dev_ready = s3c2410_nand_devready;
834 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
835 info->sel_reg = regs + S3C2440_NFCONT;
836 info->sel_bit = S3C2440_NFCONT_nFCE;
837 chip->cmd_ctrl = s3c2440_nand_hwcontrol;
838 chip->dev_ready = s3c2440_nand_devready;
839 chip->read_buf = s3c2440_nand_read_buf;
840 chip->write_buf = s3c2440_nand_write_buf;
844 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
845 info->sel_reg = regs + S3C2440_NFCONT;
846 info->sel_bit = S3C2412_NFCONT_nFCE0;
847 chip->cmd_ctrl = s3c2440_nand_hwcontrol;
848 chip->dev_ready = s3c2412_nand_devready;
850 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
851 dev_info(info->device, "System booted from NAND\n");
856 chip->IO_ADDR_R = chip->IO_ADDR_W;
861 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
862 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
863 chip->ecc.correct = s3c2410_nand_correct_data;
864 chip->ecc.mode = NAND_ECC_HW;
865 chip->ecc.strength = 1;
867 switch (info->cpu_type) {
869 chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
870 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
874 chip->ecc.hwctl = s3c2412_nand_enable_hwecc;
875 chip->ecc.calculate = s3c2412_nand_calculate_ecc;
879 chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
880 chip->ecc.calculate = s3c2440_nand_calculate_ecc;
884 chip->ecc.mode = NAND_ECC_SOFT;
885 chip->ecc.algo = NAND_ECC_HAMMING;
888 if (set->disable_ecc)
889 chip->ecc.mode = NAND_ECC_NONE;
891 switch (chip->ecc.mode) {
893 dev_info(info->device, "NAND ECC disabled\n");
896 dev_info(info->device, "NAND soft ECC\n");
899 dev_info(info->device, "NAND hardware ECC\n");
902 dev_info(info->device, "NAND ECC UNKNOWN\n");
906 /* If you use u-boot BBT creation code, specifying this flag will
907 * let the kernel fish out the BBT from the NAND, and also skip the
908 * full NAND scan that can take 1/2s or so. Little things... */
909 if (set->flash_bbt) {
910 chip->bbt_options |= NAND_BBT_USE_FLASH;
911 chip->options |= NAND_SKIP_BBTSCAN;
916 * s3c2410_nand_update_chip - post probe update
917 * @info: The controller instance.
918 * @nmtd: The driver version of the MTD instance.
920 * This routine is called after the chip probe has successfully completed
921 * and the relevant per-chip information updated. This call ensure that
922 * we update the internal state accordingly.
924 * The internal state is currently limited to the ECC state information.
926 static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
927 struct s3c2410_nand_mtd *nmtd)
929 struct nand_chip *chip = &nmtd->chip;
931 dev_dbg(info->device, "chip %p => page shift %d\n",
932 chip, chip->page_shift);
934 if (chip->ecc.mode != NAND_ECC_HW)
937 /* change the behaviour depending on whether we are using
938 * the large or small page nand device */
940 if (chip->page_shift > 10) {
941 chip->ecc.size = 256;
944 chip->ecc.size = 512;
946 mtd_set_ooblayout(nand_to_mtd(chip), &s3c2410_ooblayout_ops);
950 /* s3c24xx_nand_probe
952 * called by device layer when it finds a device matching
953 * one our driver can handled. This code checks to see if
954 * it can allocate all necessary resources then calls the
955 * nand layer to look for devices
957 static int s3c24xx_nand_probe(struct platform_device *pdev)
959 struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
960 enum s3c_cpu_type cpu_type;
961 struct s3c2410_nand_info *info;
962 struct s3c2410_nand_mtd *nmtd;
963 struct s3c2410_nand_set *sets;
964 struct resource *res;
970 cpu_type = platform_get_device_id(pdev)->driver_data;
972 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
978 platform_set_drvdata(pdev, info);
980 nand_hw_control_init(&info->controller);
982 /* get the clock source and enable it */
984 info->clk = devm_clk_get(&pdev->dev, "nand");
985 if (IS_ERR(info->clk)) {
986 dev_err(&pdev->dev, "failed to get clock\n");
991 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
993 /* allocate and map the resource */
995 /* currently we assume we have the one resource */
996 res = pdev->resource;
997 size = resource_size(res);
999 info->device = &pdev->dev;
1000 info->platform = plat;
1001 info->cpu_type = cpu_type;
1003 info->regs = devm_ioremap_resource(&pdev->dev, res);
1004 if (IS_ERR(info->regs)) {
1005 err = PTR_ERR(info->regs);
1009 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
1011 /* initialise the hardware */
1013 err = s3c2410_nand_inithw(info);
1017 sets = (plat != NULL) ? plat->sets : NULL;
1018 nr_sets = (plat != NULL) ? plat->nr_sets : 1;
1020 info->mtd_count = nr_sets;
1022 /* allocate our information */
1024 size = nr_sets * sizeof(*info->mtds);
1025 info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1026 if (info->mtds == NULL) {
1031 /* initialise all possible chips */
1035 for (setno = 0; setno < nr_sets; setno++, nmtd++) {
1036 struct mtd_info *mtd = nand_to_mtd(&nmtd->chip);
1038 pr_debug("initialising set %d (%p, info %p)\n",
1041 mtd->dev.parent = &pdev->dev;
1042 s3c2410_nand_init_chip(info, nmtd, sets);
1044 nmtd->scan_res = nand_scan_ident(mtd,
1045 (sets) ? sets->nr_chips : 1,
1048 if (nmtd->scan_res == 0) {
1049 s3c2410_nand_update_chip(info, nmtd);
1050 nand_scan_tail(mtd);
1051 s3c2410_nand_add_partition(info, nmtd, sets);
1058 err = s3c2410_nand_cpufreq_register(info);
1060 dev_err(&pdev->dev, "failed to init cpufreq support\n");
1064 if (allow_clk_suspend(info)) {
1065 dev_info(&pdev->dev, "clock idle support enabled\n");
1066 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1072 s3c24xx_nand_remove(pdev);
1082 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
1084 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1087 info->save_sel = readl(info->sel_reg);
1089 /* For the moment, we must ensure nFCE is high during
1090 * the time we are suspended. This really should be
1091 * handled by suspending the MTDs we are using, but
1092 * that is currently not the case. */
1094 writel(info->save_sel | info->sel_bit, info->sel_reg);
1096 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
1102 static int s3c24xx_nand_resume(struct platform_device *dev)
1104 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1108 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1109 s3c2410_nand_inithw(info);
1111 /* Restore the state of the nFCE line. */
1113 sel = readl(info->sel_reg);
1114 sel &= ~info->sel_bit;
1115 sel |= info->save_sel & info->sel_bit;
1116 writel(sel, info->sel_reg);
1118 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1125 #define s3c24xx_nand_suspend NULL
1126 #define s3c24xx_nand_resume NULL
1129 /* driver device registration */
1131 static const struct platform_device_id s3c24xx_driver_ids[] = {
1133 .name = "s3c2410-nand",
1134 .driver_data = TYPE_S3C2410,
1136 .name = "s3c2440-nand",
1137 .driver_data = TYPE_S3C2440,
1139 .name = "s3c2412-nand",
1140 .driver_data = TYPE_S3C2412,
1142 .name = "s3c6400-nand",
1143 .driver_data = TYPE_S3C2412, /* compatible with 2412 */
1148 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1150 static struct platform_driver s3c24xx_nand_driver = {
1151 .probe = s3c24xx_nand_probe,
1152 .remove = s3c24xx_nand_remove,
1153 .suspend = s3c24xx_nand_suspend,
1154 .resume = s3c24xx_nand_resume,
1155 .id_table = s3c24xx_driver_ids,
1157 .name = "s3c24xx-nand",
1161 module_platform_driver(s3c24xx_nand_driver);
1163 MODULE_LICENSE("GPL");
1164 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1165 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");