drivers/mtd/nand/raw/socrates_nand.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Copyright © 2008 Ilya Yanok, Emcraft Systems
   4  */
   5
   6 #include <linux/slab.h>
   7 #include <linux/module.h>
   8 #include <linux/mtd/mtd.h>
   9 #include <linux/mtd/rawnand.h>
  10 #include <linux/mtd/partitions.h>
  11 #include <linux/of_address.h>
  12 #include <linux/of_platform.h>
  13 #include <linux/io.h>
  14
  15 #define FPGA_NAND_CMD_MASK              (0x7 << 28)
  16 #define FPGA_NAND_CMD_COMMAND           (0x0 << 28)
  17 #define FPGA_NAND_CMD_ADDR              (0x1 << 28)
  18 #define FPGA_NAND_CMD_READ              (0x2 << 28)
  19 #define FPGA_NAND_CMD_WRITE             (0x3 << 28)
  20 #define FPGA_NAND_BUSY                  (0x1 << 15)
  21 #define FPGA_NAND_ENABLE                (0x1 << 31)
  22 #define FPGA_NAND_DATA_SHIFT            16
  23
  24 struct socrates_nand_host {
  25         struct nand_controller  controller;
  26         struct nand_chip        nand_chip;
  27         void __iomem            *io_base;
  28         struct device           *dev;
  29 };
  30
  31 /**
  32  * socrates_nand_write_buf -  write buffer to chip
  33  * @this:       NAND chip object
  34  * @buf:        data buffer
  35  * @len:        number of bytes to write
  36  */
  37 static void socrates_nand_write_buf(struct nand_chip *this, const uint8_t *buf,
  38                                     int len)
  39 {
  40         int i;
  41         struct socrates_nand_host *host = nand_get_controller_data(this);
  42
  43         for (i = 0; i < len; i++) {
  44                 out_be32(host->io_base, FPGA_NAND_ENABLE |
  45                                 FPGA_NAND_CMD_WRITE |
  46                                 (buf[i] << FPGA_NAND_DATA_SHIFT));
  47         }
  48 }
  49
  50 /**
  51  * socrates_nand_read_buf -  read chip data into buffer
  52  * @this:       NAND chip object
  53  * @buf:        buffer to store date
  54  * @len:        number of bytes to read
  55  */
  56 static void socrates_nand_read_buf(struct nand_chip *this, uint8_t *buf,
  57                                    int len)
  58 {
  59         int i;
  60         struct socrates_nand_host *host = nand_get_controller_data(this);
  61         uint32_t val;
  62
  63         val = FPGA_NAND_ENABLE | FPGA_NAND_CMD_READ;
  64
  65         out_be32(host->io_base, val);
  66         for (i = 0; i < len; i++) {
  67                 buf[i] = (in_be32(host->io_base) >>
  68                                 FPGA_NAND_DATA_SHIFT) & 0xff;
  69         }
  70 }
  71
  72 /**
  73  * socrates_nand_read_byte -  read one byte from the chip
  74  * @mtd:        MTD device structure
  75  */
  76 static uint8_t socrates_nand_read_byte(struct nand_chip *this)
  77 {
  78         uint8_t byte;
  79         socrates_nand_read_buf(this, &byte, sizeof(byte));
  80         return byte;
  81 }
  82
  83 /*
  84  * Hardware specific access to control-lines
  85  */
  86 static void socrates_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd,
  87                                    unsigned int ctrl)
  88 {
  89         struct socrates_nand_host *host = nand_get_controller_data(nand_chip);
  90         uint32_t val;
  91
  92         if (cmd == NAND_CMD_NONE)
  93                 return;
  94
  95         if (ctrl & NAND_CLE)
  96                 val = FPGA_NAND_CMD_COMMAND;
  97         else
  98                 val = FPGA_NAND_CMD_ADDR;
  99
 100         if (ctrl & NAND_NCE)
 101                 val |= FPGA_NAND_ENABLE;
 102
 103         val |= (cmd & 0xff) << FPGA_NAND_DATA_SHIFT;
 104
 105         out_be32(host->io_base, val);
 106 }
 107
 108 /*
 109  * Read the Device Ready pin.
 110  */
 111 static int socrates_nand_device_ready(struct nand_chip *nand_chip)
 112 {
 113         struct socrates_nand_host *host = nand_get_controller_data(nand_chip);
 114
 115         if (in_be32(host->io_base) & FPGA_NAND_BUSY)
 116                 return 0; /* busy */
 117         return 1;
 118 }
 119
 120 static int socrates_attach_chip(struct nand_chip *chip)
 121 {
 122         if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
 123             chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
 124                 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
 125
 126         return 0;
 127 }
 128
 129 static const struct nand_controller_ops socrates_ops = {
 130         .attach_chip = socrates_attach_chip,
 131 };
 132
 133 /*
 134  * Probe for the NAND device.
 135  */
 136 static int socrates_nand_probe(struct platform_device *ofdev)
 137 {
 138         struct socrates_nand_host *host;
 139         struct mtd_info *mtd;
 140         struct nand_chip *nand_chip;
 141         int res;
 142
 143         /* Allocate memory for the device structure (and zero it) */
 144         host = devm_kzalloc(&ofdev->dev, sizeof(*host), GFP_KERNEL);
 145         if (!host)
 146                 return -ENOMEM;
 147
 148         host->io_base = of_iomap(ofdev->dev.of_node, 0);
 149         if (host->io_base == NULL) {
 150                 dev_err(&ofdev->dev, "ioremap failed\n");
 151                 return -EIO;
 152         }
 153
 154         nand_chip = &host->nand_chip;
 155         mtd = nand_to_mtd(nand_chip);
 156         host->dev = &ofdev->dev;
 157
 158         nand_controller_init(&host->controller);
 159         host->controller.ops = &socrates_ops;
 160         nand_chip->controller = &host->controller;
 161
 162         /* link the private data structures */
 163         nand_set_controller_data(nand_chip, host);
 164         nand_set_flash_node(nand_chip, ofdev->dev.of_node);
 165         mtd->name = "socrates_nand";
 166         mtd->dev.parent = &ofdev->dev;
 167
 168         nand_chip->legacy.cmd_ctrl = socrates_nand_cmd_ctrl;
 169         nand_chip->legacy.read_byte = socrates_nand_read_byte;
 170         nand_chip->legacy.write_buf = socrates_nand_write_buf;
 171         nand_chip->legacy.read_buf = socrates_nand_read_buf;
 172         nand_chip->legacy.dev_ready = socrates_nand_device_ready;
 173
 174         /* TODO: I have no idea what real delay is. */
 175         nand_chip->legacy.chip_delay = 20;      /* 20us command delay time */
 176
 177         /*
 178          * This driver assumes that the default ECC engine should be TYPE_SOFT.
 179          * Set ->engine_type before registering the NAND devices in order to
 180          * provide a driver specific default value.
 181          */
 182         nand_chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
 183
 184         dev_set_drvdata(&ofdev->dev, host);
 185
 186         res = nand_scan(nand_chip, 1);
 187         if (res)
 188                 goto out;
 189
 190         res = mtd_device_register(mtd, NULL, 0);
 191         if (!res)
 192                 return res;
 193
 194         nand_cleanup(nand_chip);
 195
 196 out:
 197         iounmap(host->io_base);
 198         return res;
 199 }
 200
 201 /*
 202  * Remove a NAND device.
 203  */
 204 static int socrates_nand_remove(struct platform_device *ofdev)
 205 {
 206         struct socrates_nand_host *host = dev_get_drvdata(&ofdev->dev);
 207         struct nand_chip *chip = &host->nand_chip;
 208         int ret;
 209
 210         ret = mtd_device_unregister(nand_to_mtd(chip));
 211         WARN_ON(ret);
 212         nand_cleanup(chip);
 213
 214         iounmap(host->io_base);
 215
 216         return 0;
 217 }
 218
 219 static const struct of_device_id socrates_nand_match[] =
 220 {
 221         {
 222                 .compatible   = "abb,socrates-nand",
 223         },
 224         {},
 225 };
 226
 227 MODULE_DEVICE_TABLE(of, socrates_nand_match);
 228
 229 static struct platform_driver socrates_nand_driver = {
 230         .driver = {
 231                 .name = "socrates_nand",
 232                 .of_match_table = socrates_nand_match,
 233         },
 234         .probe          = socrates_nand_probe,
 235         .remove         = socrates_nand_remove,
 236 };
 237
 238 module_platform_driver(socrates_nand_driver);
 239
 240 MODULE_LICENSE("GPL");
 241 MODULE_AUTHOR("Ilya Yanok");
 242 MODULE_DESCRIPTION("NAND driver for Socrates board");