2 * NAND support for Marvell Orion SoC platforms
4 * Tzachi Perelstein <tzachi@marvell.com>
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/rawnand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
21 #include <linux/sizes.h>
22 #include <linux/platform_data/mtd-orion_nand.h>
24 struct orion_nand_info {
25 struct nand_controller controller;
26 struct nand_chip chip;
30 static void orion_nand_cmd_ctrl(struct nand_chip *nc, int cmd,
33 struct orion_nand_data *board = nand_get_controller_data(nc);
36 if (cmd == NAND_CMD_NONE)
40 offs = (1 << board->cle);
41 else if (ctrl & NAND_ALE)
42 offs = (1 << board->ale);
46 if (nc->options & NAND_BUSWIDTH_16)
49 writeb(cmd, nc->legacy.IO_ADDR_W + offs);
52 static void orion_nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
54 void __iomem *io_base = chip->legacy.IO_ADDR_R;
55 #if defined(__LINUX_ARM_ARCH__) && __LINUX_ARM_ARCH__ >= 5
60 while (len && (unsigned long)buf & 7) {
61 *buf++ = readb(io_base);
64 #if defined(__LINUX_ARM_ARCH__) && __LINUX_ARM_ARCH__ >= 5
65 buf64 = (uint64_t *)buf;
68 * Since GCC has no proper constraint (PR 43518)
69 * force x variable to r2/r3 registers as ldrd instruction
70 * requires first register to be even.
72 register uint64_t x asm ("r2");
74 asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base));
79 readsl(io_base, buf, len/4);
83 buf[i++] = readb(io_base);
86 static int orion_nand_attach_chip(struct nand_chip *chip)
88 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
89 chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
90 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
95 static const struct nand_controller_ops orion_nand_ops = {
96 .attach_chip = orion_nand_attach_chip,
99 static int __init orion_nand_probe(struct platform_device *pdev)
101 struct orion_nand_info *info;
102 struct mtd_info *mtd;
103 struct nand_chip *nc;
104 struct orion_nand_data *board;
105 struct resource *res;
106 void __iomem *io_base;
110 info = devm_kzalloc(&pdev->dev,
111 sizeof(struct orion_nand_info),
116 mtd = nand_to_mtd(nc);
118 nand_controller_init(&info->controller);
119 info->controller.ops = &orion_nand_ops;
120 nc->controller = &info->controller;
122 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
123 io_base = devm_ioremap_resource(&pdev->dev, res);
126 return PTR_ERR(io_base);
128 if (pdev->dev.of_node) {
129 board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data),
133 if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
134 board->cle = (u8)val;
137 if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
138 board->ale = (u8)val;
141 if (!of_property_read_u32(pdev->dev.of_node,
143 board->width = (u8)val * 8;
146 if (!of_property_read_u32(pdev->dev.of_node,
148 board->chip_delay = (u8)val;
150 board = dev_get_platdata(&pdev->dev);
153 mtd->dev.parent = &pdev->dev;
155 nand_set_controller_data(nc, board);
156 nand_set_flash_node(nc, pdev->dev.of_node);
157 nc->legacy.IO_ADDR_R = nc->legacy.IO_ADDR_W = io_base;
158 nc->legacy.cmd_ctrl = orion_nand_cmd_ctrl;
159 nc->legacy.read_buf = orion_nand_read_buf;
161 if (board->chip_delay)
162 nc->legacy.chip_delay = board->chip_delay;
164 WARN(board->width > 16,
165 "%d bit bus width out of range",
168 if (board->width == 16)
169 nc->options |= NAND_BUSWIDTH_16;
171 platform_set_drvdata(pdev, info);
173 /* Not all platforms can gate the clock, so it is not
174 an error if the clock does not exists. */
175 info->clk = devm_clk_get(&pdev->dev, NULL);
176 if (IS_ERR(info->clk)) {
177 ret = PTR_ERR(info->clk);
178 if (ret == -ENOENT) {
181 dev_err(&pdev->dev, "failed to get clock!\n");
186 ret = clk_prepare_enable(info->clk);
188 dev_err(&pdev->dev, "failed to prepare clock!\n");
193 * This driver assumes that the default ECC engine should be TYPE_SOFT.
194 * Set ->engine_type before registering the NAND devices in order to
195 * provide a driver specific default value.
197 nc->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
199 ret = nand_scan(nc, 1);
203 mtd->name = "orion_nand";
204 ret = mtd_device_register(mtd, board->parts, board->nr_parts);
213 clk_disable_unprepare(info->clk);
217 static int orion_nand_remove(struct platform_device *pdev)
219 struct orion_nand_info *info = platform_get_drvdata(pdev);
220 struct nand_chip *chip = &info->chip;
223 ret = mtd_device_unregister(nand_to_mtd(chip));
228 clk_disable_unprepare(info->clk);
234 static const struct of_device_id orion_nand_of_match_table[] = {
235 { .compatible = "marvell,orion-nand", },
238 MODULE_DEVICE_TABLE(of, orion_nand_of_match_table);
241 static struct platform_driver orion_nand_driver = {
242 .remove = orion_nand_remove,
244 .name = "orion_nand",
245 .of_match_table = of_match_ptr(orion_nand_of_match_table),
249 module_platform_driver_probe(orion_nand_driver, orion_nand_probe);
251 MODULE_LICENSE("GPL");
252 MODULE_AUTHOR("Tzachi Perelstein");
253 MODULE_DESCRIPTION("NAND glue for Orion platforms");
254 MODULE_ALIAS("platform:orion_nand");