2 * MTK ECC controller driver.
3 * Copyright (C) 2016 MediaTek Inc.
4 * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
5 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/interrupt.h>
20 #include <linux/clk.h>
21 #include <linux/module.h>
22 #include <linux/iopoll.h>
24 #include <linux/of_platform.h>
25 #include <linux/mutex.h>
29 #define ECC_IDLE_MASK BIT(0)
30 #define ECC_IRQ_EN BIT(0)
31 #define ECC_PG_IRQ_SEL BIT(1)
32 #define ECC_OP_ENABLE (1)
33 #define ECC_OP_DISABLE (0)
35 #define ECC_ENCCON (0x00)
36 #define ECC_ENCCNFG (0x04)
37 #define ECC_MS_SHIFT (16)
38 #define ECC_ENCDIADDR (0x08)
39 #define ECC_ENCIDLE (0x0C)
40 #define ECC_DECCON (0x100)
41 #define ECC_DECCNFG (0x104)
42 #define DEC_EMPTY_EN BIT(31)
43 #define DEC_CNFG_CORRECT (0x3 << 12)
44 #define ECC_DECIDLE (0x10C)
45 #define ECC_DECENUM0 (0x114)
47 #define ECC_TIMEOUT (500000)
49 #define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
50 #define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
55 const u8 *ecc_strength;
65 const struct mtk_ecc_caps *caps;
69 struct completion done;
76 /* ecc strength that each IP supports */
77 static const u8 ecc_strength_mt2701[] = {
78 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
79 40, 44, 48, 52, 56, 60
82 static const u8 ecc_strength_mt2712[] = {
83 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
84 40, 44, 48, 52, 56, 60, 68, 72, 80
87 static const u8 ecc_strength_mt7622[] = {
100 static int mt2701_ecc_regs[] = {
101 [ECC_ENCPAR00] = 0x10,
102 [ECC_ENCIRQ_EN] = 0x80,
103 [ECC_ENCIRQ_STA] = 0x84,
104 [ECC_DECDONE] = 0x124,
105 [ECC_DECIRQ_EN] = 0x200,
106 [ECC_DECIRQ_STA] = 0x204,
109 static int mt2712_ecc_regs[] = {
110 [ECC_ENCPAR00] = 0x300,
111 [ECC_ENCIRQ_EN] = 0x80,
112 [ECC_ENCIRQ_STA] = 0x84,
113 [ECC_DECDONE] = 0x124,
114 [ECC_DECIRQ_EN] = 0x200,
115 [ECC_DECIRQ_STA] = 0x204,
118 static int mt7622_ecc_regs[] = {
119 [ECC_ENCPAR00] = 0x10,
120 [ECC_ENCIRQ_EN] = 0x30,
121 [ECC_ENCIRQ_STA] = 0x34,
122 [ECC_DECDONE] = 0x11c,
123 [ECC_DECIRQ_EN] = 0x140,
124 [ECC_DECIRQ_STA] = 0x144,
127 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
128 enum mtk_ecc_operation op)
130 struct device *dev = ecc->dev;
134 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
138 dev_warn(dev, "%s NOT idle\n",
139 op == ECC_ENCODE ? "encoder" : "decoder");
142 static irqreturn_t mtk_ecc_irq(int irq, void *id)
144 struct mtk_ecc *ecc = id;
147 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
150 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
151 if (dec & ecc->sectors) {
153 * Clear decode IRQ status once again to ensure that
154 * there will be no extra IRQ.
156 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
158 complete(&ecc->done);
163 enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
166 complete(&ecc->done);
174 static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
176 u32 ecc_bit, dec_sz, enc_sz;
179 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
180 if (ecc->caps->ecc_strength[i] == config->strength)
184 if (i == ecc->caps->num_ecc_strength) {
185 dev_err(ecc->dev, "invalid ecc strength %d\n",
192 if (config->op == ECC_ENCODE) {
193 /* configure ECC encoder (in bits) */
194 enc_sz = config->len << 3;
196 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
197 reg |= (enc_sz << ECC_MS_SHIFT);
198 writel(reg, ecc->regs + ECC_ENCCNFG);
200 if (config->mode != ECC_NFI_MODE)
201 writel(lower_32_bits(config->addr),
202 ecc->regs + ECC_ENCDIADDR);
205 /* configure ECC decoder (in bits) */
206 dec_sz = (config->len << 3) +
207 config->strength * ecc->caps->parity_bits;
209 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
210 reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
212 writel(reg, ecc->regs + ECC_DECCNFG);
215 ecc->sectors = 1 << (config->sectors - 1);
221 void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
227 stats->corrected = 0;
230 for (i = 0; i < sectors; i++) {
231 offset = (i >> 2) << 2;
232 err = readl(ecc->regs + ECC_DECENUM0 + offset);
233 err = err >> ((i % 4) * ecc->caps->err_shift);
234 err &= ecc->caps->err_mask;
235 if (err == ecc->caps->err_mask) {
236 /* uncorrectable errors */
241 stats->corrected += err;
242 bitflips = max_t(u32, bitflips, err);
245 stats->bitflips = bitflips;
247 EXPORT_SYMBOL(mtk_ecc_get_stats);
249 void mtk_ecc_release(struct mtk_ecc *ecc)
251 clk_disable_unprepare(ecc->clk);
252 put_device(ecc->dev);
254 EXPORT_SYMBOL(mtk_ecc_release);
256 static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
258 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
259 writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
261 mtk_ecc_wait_idle(ecc, ECC_DECODE);
262 writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
265 static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
267 struct platform_device *pdev;
270 pdev = of_find_device_by_node(np);
271 if (!pdev || !platform_get_drvdata(pdev))
272 return ERR_PTR(-EPROBE_DEFER);
274 get_device(&pdev->dev);
275 ecc = platform_get_drvdata(pdev);
276 clk_prepare_enable(ecc->clk);
277 mtk_ecc_hw_init(ecc);
282 struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
284 struct mtk_ecc *ecc = NULL;
285 struct device_node *np;
287 np = of_parse_phandle(of_node, "ecc-engine", 0);
289 ecc = mtk_ecc_get(np);
295 EXPORT_SYMBOL(of_mtk_ecc_get);
297 int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
299 enum mtk_ecc_operation op = config->op;
303 ret = mutex_lock_interruptible(&ecc->lock);
305 dev_err(ecc->dev, "interrupted when attempting to lock\n");
309 mtk_ecc_wait_idle(ecc, op);
311 ret = mtk_ecc_config(ecc, config);
313 mutex_unlock(&ecc->lock);
317 if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
318 init_completion(&ecc->done);
319 reg_val = ECC_IRQ_EN;
321 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
322 * means this chip can only generate one ecc irq during page
323 * read / write. If is 0, generate one ecc irq each ecc step.
325 if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
326 reg_val |= ECC_PG_IRQ_SEL;
327 if (op == ECC_ENCODE)
328 writew(reg_val, ecc->regs +
329 ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
331 writew(reg_val, ecc->regs +
332 ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
335 writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
339 EXPORT_SYMBOL(mtk_ecc_enable);
341 void mtk_ecc_disable(struct mtk_ecc *ecc)
343 enum mtk_ecc_operation op = ECC_ENCODE;
345 /* find out the running operation */
346 if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
350 mtk_ecc_wait_idle(ecc, op);
351 if (op == ECC_DECODE) {
353 * Clear decode IRQ status in case there is a timeout to wait
356 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
357 writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
359 writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
362 writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
364 mutex_unlock(&ecc->lock);
366 EXPORT_SYMBOL(mtk_ecc_disable);
368 int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
372 ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
374 dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
375 (op == ECC_ENCODE) ? "encoder" : "decoder");
381 EXPORT_SYMBOL(mtk_ecc_wait_done);
383 int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
390 addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
391 ret = dma_mapping_error(ecc->dev, addr);
393 dev_err(ecc->dev, "dma mapping error\n");
397 config->op = ECC_ENCODE;
399 ret = mtk_ecc_enable(ecc, config);
401 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
405 ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
409 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
411 /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
412 len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
414 /* write the parity bytes generated by the ECC back to temp buffer */
415 __ioread32_copy(ecc->eccdata,
416 ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
419 /* copy into possibly unaligned OOB region with actual length */
420 memcpy(data + bytes, ecc->eccdata, len);
423 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
424 mtk_ecc_disable(ecc);
428 EXPORT_SYMBOL(mtk_ecc_encode);
430 void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
432 const u8 *ecc_strength = ecc->caps->ecc_strength;
435 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
436 if (*p <= ecc_strength[i]) {
438 *p = ecc_strength[i];
439 else if (*p != ecc_strength[i])
440 *p = ecc_strength[i - 1];
445 *p = ecc_strength[ecc->caps->num_ecc_strength - 1];
447 EXPORT_SYMBOL(mtk_ecc_adjust_strength);
449 unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
451 return ecc->caps->parity_bits;
453 EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
455 static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
458 .ecc_strength = ecc_strength_mt2701,
459 .ecc_regs = mt2701_ecc_regs,
460 .num_ecc_strength = 20,
466 static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
469 .ecc_strength = ecc_strength_mt2712,
470 .ecc_regs = mt2712_ecc_regs,
471 .num_ecc_strength = 23,
477 static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
480 .ecc_strength = ecc_strength_mt7622,
481 .ecc_regs = mt7622_ecc_regs,
482 .num_ecc_strength = 5,
488 static const struct of_device_id mtk_ecc_dt_match[] = {
490 .compatible = "mediatek,mt2701-ecc",
491 .data = &mtk_ecc_caps_mt2701,
493 .compatible = "mediatek,mt2712-ecc",
494 .data = &mtk_ecc_caps_mt2712,
496 .compatible = "mediatek,mt7622-ecc",
497 .data = &mtk_ecc_caps_mt7622,
502 static int mtk_ecc_probe(struct platform_device *pdev)
504 struct device *dev = &pdev->dev;
506 struct resource *res;
507 u32 max_eccdata_size;
510 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
514 ecc->caps = of_device_get_match_data(dev);
516 max_eccdata_size = ecc->caps->num_ecc_strength - 1;
517 max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
518 max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
519 max_eccdata_size = round_up(max_eccdata_size, 4);
520 ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
524 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
525 ecc->regs = devm_ioremap_resource(dev, res);
526 if (IS_ERR(ecc->regs)) {
527 dev_err(dev, "failed to map regs: %ld\n", PTR_ERR(ecc->regs));
528 return PTR_ERR(ecc->regs);
531 ecc->clk = devm_clk_get(dev, NULL);
532 if (IS_ERR(ecc->clk)) {
533 dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
534 return PTR_ERR(ecc->clk);
537 irq = platform_get_irq(pdev, 0);
539 dev_err(dev, "failed to get irq: %d\n", irq);
543 ret = dma_set_mask(dev, DMA_BIT_MASK(32));
545 dev_err(dev, "failed to set DMA mask\n");
549 ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
551 dev_err(dev, "failed to request irq\n");
556 mutex_init(&ecc->lock);
557 platform_set_drvdata(pdev, ecc);
558 dev_info(dev, "probed\n");
563 #ifdef CONFIG_PM_SLEEP
564 static int mtk_ecc_suspend(struct device *dev)
566 struct mtk_ecc *ecc = dev_get_drvdata(dev);
568 clk_disable_unprepare(ecc->clk);
573 static int mtk_ecc_resume(struct device *dev)
575 struct mtk_ecc *ecc = dev_get_drvdata(dev);
578 ret = clk_prepare_enable(ecc->clk);
580 dev_err(dev, "failed to enable clk\n");
587 static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
590 MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
592 static struct platform_driver mtk_ecc_driver = {
593 .probe = mtk_ecc_probe,
596 .of_match_table = of_match_ptr(mtk_ecc_dt_match),
597 #ifdef CONFIG_PM_SLEEP
598 .pm = &mtk_ecc_pm_ops,
603 module_platform_driver(mtk_ecc_driver);
605 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
606 MODULE_DESCRIPTION("MTK Nand ECC Driver");
607 MODULE_LICENSE("GPL");