1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
4 * Copyright 2009 Semihalf.
6 * Approved as OSADL project by a majority of OSADL members and funded
7 * by OSADL membership fees in 2009; for details see www.osadl.org.
9 * Based on original driver from Freescale Semiconductor
10 * written by John Rigby <jrigby@freescale.com> on basis of mxc_nand.c.
11 * Reworked and extended by Piotr Ziecik <kosmo@semihalf.com>.
14 #include <linux/module.h>
15 #include <linux/clk.h>
16 #include <linux/gfp.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/rawnand.h>
23 #include <linux/mtd/partitions.h>
24 #include <linux/of_address.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_platform.h>
29 #include <asm/mpc5121.h>
31 /* Addresses for NFC MAIN RAM BUFFER areas */
32 #define NFC_MAIN_AREA(n) ((n) * 0x200)
34 /* Addresses for NFC SPARE BUFFER areas */
35 #define NFC_SPARE_BUFFERS 8
36 #define NFC_SPARE_LEN 0x40
37 #define NFC_SPARE_AREA(n) (0x1000 + ((n) * NFC_SPARE_LEN))
39 /* MPC5121 NFC registers */
40 #define NFC_BUF_ADDR 0x1E04
41 #define NFC_FLASH_ADDR 0x1E06
42 #define NFC_FLASH_CMD 0x1E08
43 #define NFC_CONFIG 0x1E0A
44 #define NFC_ECC_STATUS1 0x1E0C
45 #define NFC_ECC_STATUS2 0x1E0E
46 #define NFC_SPAS 0x1E10
47 #define NFC_WRPROT 0x1E12
48 #define NFC_NF_WRPRST 0x1E18
49 #define NFC_CONFIG1 0x1E1A
50 #define NFC_CONFIG2 0x1E1C
51 #define NFC_UNLOCKSTART_BLK0 0x1E20
52 #define NFC_UNLOCKEND_BLK0 0x1E22
53 #define NFC_UNLOCKSTART_BLK1 0x1E24
54 #define NFC_UNLOCKEND_BLK1 0x1E26
55 #define NFC_UNLOCKSTART_BLK2 0x1E28
56 #define NFC_UNLOCKEND_BLK2 0x1E2A
57 #define NFC_UNLOCKSTART_BLK3 0x1E2C
58 #define NFC_UNLOCKEND_BLK3 0x1E2E
60 /* Bit Definitions: NFC_BUF_ADDR */
61 #define NFC_RBA_MASK (7 << 0)
62 #define NFC_ACTIVE_CS_SHIFT 5
63 #define NFC_ACTIVE_CS_MASK (3 << NFC_ACTIVE_CS_SHIFT)
65 /* Bit Definitions: NFC_CONFIG */
66 #define NFC_BLS_UNLOCKED (1 << 1)
68 /* Bit Definitions: NFC_CONFIG1 */
69 #define NFC_ECC_4BIT (1 << 0)
70 #define NFC_FULL_PAGE_DMA (1 << 1)
71 #define NFC_SPARE_ONLY (1 << 2)
72 #define NFC_ECC_ENABLE (1 << 3)
73 #define NFC_INT_MASK (1 << 4)
74 #define NFC_BIG_ENDIAN (1 << 5)
75 #define NFC_RESET (1 << 6)
76 #define NFC_CE (1 << 7)
77 #define NFC_ONE_CYCLE (1 << 8)
78 #define NFC_PPB_32 (0 << 9)
79 #define NFC_PPB_64 (1 << 9)
80 #define NFC_PPB_128 (2 << 9)
81 #define NFC_PPB_256 (3 << 9)
82 #define NFC_PPB_MASK (3 << 9)
83 #define NFC_FULL_PAGE_INT (1 << 11)
85 /* Bit Definitions: NFC_CONFIG2 */
86 #define NFC_COMMAND (1 << 0)
87 #define NFC_ADDRESS (1 << 1)
88 #define NFC_INPUT (1 << 2)
89 #define NFC_OUTPUT (1 << 3)
90 #define NFC_ID (1 << 4)
91 #define NFC_STATUS (1 << 5)
92 #define NFC_CMD_FAIL (1 << 15)
93 #define NFC_INT (1 << 15)
95 /* Bit Definitions: NFC_WRPROT */
96 #define NFC_WPC_LOCK_TIGHT (1 << 0)
97 #define NFC_WPC_LOCK (1 << 1)
98 #define NFC_WPC_UNLOCK (1 << 2)
100 #define DRV_NAME "mpc5121_nfc"
103 #define NFC_RESET_TIMEOUT 1000 /* 1 ms */
104 #define NFC_TIMEOUT (HZ / 10) /* 1/10 s */
106 struct mpc5121_nfc_prv {
107 struct nand_controller controller;
108 struct nand_chip chip;
112 wait_queue_head_t irq_waitq;
119 static void mpc5121_nfc_done(struct mtd_info *mtd);
121 /* Read NFC register */
122 static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
124 struct nand_chip *chip = mtd_to_nand(mtd);
125 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
127 return in_be16(prv->regs + reg);
130 /* Write NFC register */
131 static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
133 struct nand_chip *chip = mtd_to_nand(mtd);
134 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
136 out_be16(prv->regs + reg, val);
139 /* Set bits in NFC register */
140 static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
142 nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
145 /* Clear bits in NFC register */
146 static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
148 nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
151 /* Invoke address cycle */
152 static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
154 nfc_write(mtd, NFC_FLASH_ADDR, addr);
155 nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
156 mpc5121_nfc_done(mtd);
159 /* Invoke command cycle */
160 static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
162 nfc_write(mtd, NFC_FLASH_CMD, cmd);
163 nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
164 mpc5121_nfc_done(mtd);
167 /* Send data from NFC buffers to NAND flash */
168 static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
170 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
171 nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
172 mpc5121_nfc_done(mtd);
175 /* Receive data from NAND flash */
176 static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
178 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
179 nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
180 mpc5121_nfc_done(mtd);
183 /* Receive ID from NAND flash */
184 static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
186 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
187 nfc_write(mtd, NFC_CONFIG2, NFC_ID);
188 mpc5121_nfc_done(mtd);
191 /* Receive status from NAND flash */
192 static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
194 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
195 nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
196 mpc5121_nfc_done(mtd);
199 /* NFC interrupt handler */
200 static irqreturn_t mpc5121_nfc_irq(int irq, void *data)
202 struct mtd_info *mtd = data;
203 struct nand_chip *chip = mtd_to_nand(mtd);
204 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
206 nfc_set(mtd, NFC_CONFIG1, NFC_INT_MASK);
207 wake_up(&prv->irq_waitq);
212 /* Wait for operation complete */
213 static void mpc5121_nfc_done(struct mtd_info *mtd)
215 struct nand_chip *chip = mtd_to_nand(mtd);
216 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
219 if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) == 0) {
220 nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK);
221 rv = wait_event_timeout(prv->irq_waitq,
222 (nfc_read(mtd, NFC_CONFIG2) & NFC_INT), NFC_TIMEOUT);
226 "Timeout while waiting for interrupt.\n");
229 nfc_clear(mtd, NFC_CONFIG2, NFC_INT);
232 /* Do address cycle(s) */
233 static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
235 struct nand_chip *chip = mtd_to_nand(mtd);
236 u32 pagemask = chip->pagemask;
239 mpc5121_nfc_send_addr(mtd, column);
240 if (mtd->writesize > 512)
241 mpc5121_nfc_send_addr(mtd, column >> 8);
246 mpc5121_nfc_send_addr(mtd, page & 0xFF);
253 /* Control chip select signals */
254 static void mpc5121_nfc_select_chip(struct nand_chip *nand, int chip)
256 struct mtd_info *mtd = nand_to_mtd(nand);
259 nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
263 nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
264 nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
266 nfc_set(mtd, NFC_CONFIG1, NFC_CE);
269 /* Init external chip select logic on ADS5121 board */
270 static int ads5121_chipselect_init(struct mtd_info *mtd)
272 struct nand_chip *chip = mtd_to_nand(mtd);
273 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
274 struct device_node *dn;
276 dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld");
278 prv->csreg = of_iomap(dn, 0);
283 /* CPLD Register 9 controls NAND /CE Lines */
291 /* Control chips select signal on ADS5121 board */
292 static void ads5121_select_chip(struct nand_chip *nand, int chip)
294 struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
297 v = in_8(prv->csreg);
301 mpc5121_nfc_select_chip(nand, 0);
304 mpc5121_nfc_select_chip(nand, -1);
306 out_8(prv->csreg, v);
309 /* Read NAND Ready/Busy signal */
310 static int mpc5121_nfc_dev_ready(struct nand_chip *nand)
313 * NFC handles ready/busy signal internally. Therefore, this function
314 * always returns status as ready.
319 /* Write command to NAND flash */
320 static void mpc5121_nfc_command(struct nand_chip *chip, unsigned command,
321 int column, int page)
323 struct mtd_info *mtd = nand_to_mtd(chip);
324 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
326 prv->column = (column >= 0) ? column : 0;
330 case NAND_CMD_PAGEPROG:
331 mpc5121_nfc_send_prog_page(mtd);
334 * NFC does not support sub-page reads and writes,
335 * so emulate them using full page transfers.
343 command = NAND_CMD_READ0;
347 case NAND_CMD_READOOB:
349 command = NAND_CMD_READ0;
354 mpc5121_nfc_command(chip, NAND_CMD_READ0, column, page);
358 case NAND_CMD_ERASE1:
359 case NAND_CMD_ERASE2:
360 case NAND_CMD_READID:
361 case NAND_CMD_STATUS:
368 mpc5121_nfc_send_cmd(mtd, command);
369 mpc5121_nfc_addr_cycle(mtd, column, page);
373 if (mtd->writesize > 512)
374 mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
375 mpc5121_nfc_send_read_page(mtd);
378 case NAND_CMD_READID:
379 mpc5121_nfc_send_read_id(mtd);
382 case NAND_CMD_STATUS:
383 mpc5121_nfc_send_read_status(mtd);
384 if (chip->options & NAND_BUSWIDTH_16)
392 /* Copy data from/to NFC spare buffers. */
393 static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
394 u8 *buffer, uint size, int wr)
396 struct nand_chip *nand = mtd_to_nand(mtd);
397 struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
398 uint o, s, sbsize, blksize;
401 * NAND spare area is available through NFC spare buffers.
402 * The NFC divides spare area into (page_size / 512) chunks.
403 * Each chunk is placed into separate spare memory area, using
404 * first (spare_size / num_of_chunks) bytes of the buffer.
406 * For NAND device in which the spare area is not divided fully
407 * by the number of chunks, number of used bytes in each spare
408 * buffer is rounded down to the nearest even number of bytes,
409 * and all remaining bytes are added to the last used spare area.
411 * For more information read section 26.6.10 of MPC5121e
412 * Microcontroller Reference Manual, Rev. 3.
415 /* Calculate number of valid bytes in each spare buffer */
416 sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
419 /* Calculate spare buffer number */
421 if (s > NFC_SPARE_BUFFERS - 1)
422 s = NFC_SPARE_BUFFERS - 1;
425 * Calculate offset to requested data block in selected spare
426 * buffer and its size.
428 o = offset - (s * sbsize);
429 blksize = min(sbsize - o, size);
432 memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
435 memcpy_fromio(buffer,
436 prv->regs + NFC_SPARE_AREA(s) + o, blksize);
444 /* Copy data from/to NFC main and spare buffers */
445 static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len,
448 struct nand_chip *chip = mtd_to_nand(mtd);
449 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
450 uint c = prv->column;
453 /* Handle spare area access */
454 if (prv->spareonly || c >= mtd->writesize) {
455 /* Calculate offset from beginning of spare area */
456 if (c >= mtd->writesize)
460 mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
465 * Handle main area access - limit copy length to prevent
466 * crossing main/spare boundary.
468 l = min((uint)len, mtd->writesize - c);
472 memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
474 memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
476 /* Handle crossing main/spare boundary */
480 mpc5121_nfc_buf_copy(mtd, buf, len, wr);
484 /* Read data from NFC buffers */
485 static void mpc5121_nfc_read_buf(struct nand_chip *chip, u_char *buf, int len)
487 mpc5121_nfc_buf_copy(nand_to_mtd(chip), buf, len, 0);
490 /* Write data to NFC buffers */
491 static void mpc5121_nfc_write_buf(struct nand_chip *chip, const u_char *buf,
494 mpc5121_nfc_buf_copy(nand_to_mtd(chip), (u_char *)buf, len, 1);
497 /* Read byte from NFC buffers */
498 static u8 mpc5121_nfc_read_byte(struct nand_chip *chip)
502 mpc5121_nfc_read_buf(chip, &tmp, sizeof(tmp));
508 * Read NFC configuration from Reset Config Word
510 * NFC is configured during reset in basis of information stored
511 * in Reset Config Word. There is no other way to set NAND block
512 * size, spare size and bus width.
514 static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
516 struct nand_chip *chip = mtd_to_nand(mtd);
517 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
518 struct mpc512x_reset_module *rm;
519 struct device_node *rmnode;
520 uint rcw_pagesize = 0;
521 uint rcw_sparesize = 0;
527 rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
529 dev_err(prv->dev, "Missing 'fsl,mpc5121-reset' "
530 "node in device tree!\n");
534 rm = of_iomap(rmnode, 0);
536 dev_err(prv->dev, "Error mapping reset module node!\n");
541 rcwh = in_be32(&rm->rcwhr);
543 /* Bit 6: NFC bus width */
544 rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
546 /* Bit 7: NFC Page/Spare size */
547 ps = (rcwh >> 7) & 0x1;
549 /* Bits [22:21]: ROM Location */
550 romloc = (rcwh >> 21) & 0x3;
552 /* Decode RCW bits */
553 switch ((ps << 2) | romloc) {
576 mtd->writesize = rcw_pagesize;
577 mtd->oobsize = rcw_sparesize;
579 chip->options |= NAND_BUSWIDTH_16;
581 dev_notice(prv->dev, "Configured for "
582 "%u-bit NAND, page size %u "
584 rcw_width * 8, rcw_pagesize,
592 /* Free driver resources */
593 static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
595 struct nand_chip *chip = mtd_to_nand(mtd);
596 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
598 clk_disable_unprepare(prv->clk);
604 static int mpc5121_nfc_attach_chip(struct nand_chip *chip)
606 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
607 chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
608 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
613 static const struct nand_controller_ops mpc5121_nfc_ops = {
614 .attach_chip = mpc5121_nfc_attach_chip,
617 static int mpc5121_nfc_probe(struct platform_device *op)
619 struct device_node *dn = op->dev.of_node;
621 struct device *dev = &op->dev;
622 struct mpc5121_nfc_prv *prv;
624 struct mtd_info *mtd;
625 struct nand_chip *chip;
626 unsigned long regs_paddr, regs_size;
627 const __be32 *chips_no;
633 * Check SoC revision. This driver supports only NFC
634 * in MPC5121 revision 2 and MPC5123 revision 3.
636 rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
637 if ((rev != 2) && (rev != 3)) {
638 dev_err(dev, "SoC revision %u is not supported!\n", rev);
642 prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
647 mtd = nand_to_mtd(chip);
649 nand_controller_init(&prv->controller);
650 prv->controller.ops = &mpc5121_nfc_ops;
651 chip->controller = &prv->controller;
653 mtd->dev.parent = dev;
654 nand_set_controller_data(chip, prv);
655 nand_set_flash_node(chip, dn);
658 /* Read NFC configuration from Reset Config Word */
659 retval = mpc5121_nfc_read_hw_config(mtd);
661 dev_err(dev, "Unable to read NFC config!\n");
665 prv->irq = irq_of_parse_and_map(dn, 0);
666 if (prv->irq == NO_IRQ) {
667 dev_err(dev, "Error mapping IRQ!\n");
671 retval = of_address_to_resource(dn, 0, &res);
673 dev_err(dev, "Error parsing memory region!\n");
677 chips_no = of_get_property(dn, "chips", &len);
678 if (!chips_no || len != sizeof(*chips_no)) {
679 dev_err(dev, "Invalid/missing 'chips' property!\n");
683 regs_paddr = res.start;
684 regs_size = resource_size(&res);
686 if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
687 dev_err(dev, "Error requesting memory region!\n");
691 prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
693 dev_err(dev, "Error mapping memory region!\n");
697 mtd->name = "MPC5121 NAND";
698 chip->legacy.dev_ready = mpc5121_nfc_dev_ready;
699 chip->legacy.cmdfunc = mpc5121_nfc_command;
700 chip->legacy.read_byte = mpc5121_nfc_read_byte;
701 chip->legacy.read_buf = mpc5121_nfc_read_buf;
702 chip->legacy.write_buf = mpc5121_nfc_write_buf;
703 chip->legacy.select_chip = mpc5121_nfc_select_chip;
704 chip->legacy.set_features = nand_get_set_features_notsupp;
705 chip->legacy.get_features = nand_get_set_features_notsupp;
706 chip->bbt_options = NAND_BBT_USE_FLASH;
708 /* Support external chip-select logic on ADS5121 board */
709 if (of_machine_is_compatible("fsl,mpc5121ads")) {
710 retval = ads5121_chipselect_init(mtd);
712 dev_err(dev, "Chipselect init error!\n");
716 chip->legacy.select_chip = ads5121_select_chip;
719 /* Enable NFC clock */
720 clk = devm_clk_get(dev, "ipg");
722 dev_err(dev, "Unable to acquire NFC clock!\n");
723 retval = PTR_ERR(clk);
726 retval = clk_prepare_enable(clk);
728 dev_err(dev, "Unable to enable NFC clock!\n");
733 /* Reset NAND Flash controller */
734 nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
735 while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
736 if (resettime++ >= NFC_RESET_TIMEOUT) {
737 dev_err(dev, "Timeout while resetting NFC!\n");
745 /* Enable write to NFC memory */
746 nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
748 /* Enable write to all NAND pages */
749 nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
750 nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
751 nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
755 * - Big Endian transfers,
756 * - Interrupt after full page read/write.
758 nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
761 /* Set spare area size */
762 nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
764 init_waitqueue_head(&prv->irq_waitq);
765 retval = devm_request_irq(dev, prv->irq, &mpc5121_nfc_irq, 0, DRV_NAME,
768 dev_err(dev, "Error requesting IRQ!\n");
773 * This driver assumes that the default ECC engine should be TYPE_SOFT.
774 * Set ->engine_type before registering the NAND devices in order to
775 * provide a driver specific default value.
777 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
779 /* Detect NAND chips */
780 retval = nand_scan(chip, be32_to_cpup(chips_no));
782 dev_err(dev, "NAND Flash not found !\n");
786 /* Set erase block size */
787 switch (mtd->erasesize / mtd->writesize) {
789 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
793 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
797 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
801 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
805 dev_err(dev, "Unsupported NAND flash!\n");
810 dev_set_drvdata(dev, mtd);
812 /* Register device in MTD */
813 retval = mtd_device_register(mtd, NULL, 0);
815 dev_err(dev, "Error adding MTD device!\n");
821 mpc5121_nfc_free(dev, mtd);
825 static int mpc5121_nfc_remove(struct platform_device *op)
827 struct device *dev = &op->dev;
828 struct mtd_info *mtd = dev_get_drvdata(dev);
831 ret = mtd_device_unregister(mtd);
833 nand_cleanup(mtd_to_nand(mtd));
834 mpc5121_nfc_free(dev, mtd);
839 static const struct of_device_id mpc5121_nfc_match[] = {
840 { .compatible = "fsl,mpc5121-nfc", },
843 MODULE_DEVICE_TABLE(of, mpc5121_nfc_match);
845 static struct platform_driver mpc5121_nfc_driver = {
846 .probe = mpc5121_nfc_probe,
847 .remove = mpc5121_nfc_remove,
850 .of_match_table = mpc5121_nfc_match,
854 module_platform_driver(mpc5121_nfc_driver);
856 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
857 MODULE_DESCRIPTION("MPC5121 NAND MTD driver");
858 MODULE_LICENSE("GPL");