drivers/mtd/nand/raw/lpc32xx_mlc.c

   1 /*
   2  * Driver for NAND MLC Controller in LPC32xx
   3  *
   4  * Author: Roland Stigge <stigge@antcom.de>
   5  *
   6  * Copyright © 2011 WORK Microwave GmbH
   7  * Copyright © 2011, 2012 Roland Stigge
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  *
  20  * NAND Flash Controller Operation:
  21  * - Read: Auto Decode
  22  * - Write: Auto Encode
  23  * - Tested Page Sizes: 2048, 4096
  24  */
  25
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/rawnand.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/clk.h>
  33 #include <linux/err.h>
  34 #include <linux/delay.h>
  35 #include <linux/completion.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/of.h>
  38 #include <linux/of_gpio.h>
  39 #include <linux/mtd/lpc32xx_mlc.h>
  40 #include <linux/io.h>
  41 #include <linux/mm.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/dmaengine.h>
  44 #include <linux/mtd/nand_ecc.h>
  45
  46 #define DRV_NAME "lpc32xx_mlc"
  47
  48 /**********************************************************************
  49 * MLC NAND controller register offsets
  50 **********************************************************************/
  51
  52 #define MLC_BUFF(x)                     (x + 0x00000)
  53 #define MLC_DATA(x)                     (x + 0x08000)
  54 #define MLC_CMD(x)                      (x + 0x10000)
  55 #define MLC_ADDR(x)                     (x + 0x10004)
  56 #define MLC_ECC_ENC_REG(x)              (x + 0x10008)
  57 #define MLC_ECC_DEC_REG(x)              (x + 0x1000C)
  58 #define MLC_ECC_AUTO_ENC_REG(x)         (x + 0x10010)
  59 #define MLC_ECC_AUTO_DEC_REG(x)         (x + 0x10014)
  60 #define MLC_RPR(x)                      (x + 0x10018)
  61 #define MLC_WPR(x)                      (x + 0x1001C)
  62 #define MLC_RUBP(x)                     (x + 0x10020)
  63 #define MLC_ROBP(x)                     (x + 0x10024)
  64 #define MLC_SW_WP_ADD_LOW(x)            (x + 0x10028)
  65 #define MLC_SW_WP_ADD_HIG(x)            (x + 0x1002C)
  66 #define MLC_ICR(x)                      (x + 0x10030)
  67 #define MLC_TIME_REG(x)                 (x + 0x10034)
  68 #define MLC_IRQ_MR(x)                   (x + 0x10038)
  69 #define MLC_IRQ_SR(x)                   (x + 0x1003C)
  70 #define MLC_LOCK_PR(x)                  (x + 0x10044)
  71 #define MLC_ISR(x)                      (x + 0x10048)
  72 #define MLC_CEH(x)                      (x + 0x1004C)
  73
  74 /**********************************************************************
  75 * MLC_CMD bit definitions
  76 **********************************************************************/
  77 #define MLCCMD_RESET                    0xFF
  78
  79 /**********************************************************************
  80 * MLC_ICR bit definitions
  81 **********************************************************************/
  82 #define MLCICR_WPROT                    (1 << 3)
  83 #define MLCICR_LARGEBLOCK               (1 << 2)
  84 #define MLCICR_LONGADDR                 (1 << 1)
  85 #define MLCICR_16BIT                    (1 << 0)  /* unsupported by LPC32x0! */
  86
  87 /**********************************************************************
  88 * MLC_TIME_REG bit definitions
  89 **********************************************************************/
  90 #define MLCTIMEREG_TCEA_DELAY(n)        (((n) & 0x03) << 24)
  91 #define MLCTIMEREG_BUSY_DELAY(n)        (((n) & 0x1F) << 19)
  92 #define MLCTIMEREG_NAND_TA(n)           (((n) & 0x07) << 16)
  93 #define MLCTIMEREG_RD_HIGH(n)           (((n) & 0x0F) << 12)
  94 #define MLCTIMEREG_RD_LOW(n)            (((n) & 0x0F) << 8)
  95 #define MLCTIMEREG_WR_HIGH(n)           (((n) & 0x0F) << 4)
  96 #define MLCTIMEREG_WR_LOW(n)            (((n) & 0x0F) << 0)
  97
  98 /**********************************************************************
  99 * MLC_IRQ_MR and MLC_IRQ_SR bit definitions
 100 **********************************************************************/
 101 #define MLCIRQ_NAND_READY               (1 << 5)
 102 #define MLCIRQ_CONTROLLER_READY         (1 << 4)
 103 #define MLCIRQ_DECODE_FAILURE           (1 << 3)
 104 #define MLCIRQ_DECODE_ERROR             (1 << 2)
 105 #define MLCIRQ_ECC_READY                (1 << 1)
 106 #define MLCIRQ_WRPROT_FAULT             (1 << 0)
 107
 108 /**********************************************************************
 109 * MLC_LOCK_PR bit definitions
 110 **********************************************************************/
 111 #define MLCLOCKPR_MAGIC                 0xA25E
 112
 113 /**********************************************************************
 114 * MLC_ISR bit definitions
 115 **********************************************************************/
 116 #define MLCISR_DECODER_FAILURE          (1 << 6)
 117 #define MLCISR_ERRORS                   ((1 << 4) | (1 << 5))
 118 #define MLCISR_ERRORS_DETECTED          (1 << 3)
 119 #define MLCISR_ECC_READY                (1 << 2)
 120 #define MLCISR_CONTROLLER_READY         (1 << 1)
 121 #define MLCISR_NAND_READY               (1 << 0)
 122
 123 /**********************************************************************
 124 * MLC_CEH bit definitions
 125 **********************************************************************/
 126 #define MLCCEH_NORMAL                   (1 << 0)
 127
 128 struct lpc32xx_nand_cfg_mlc {
 129         uint32_t tcea_delay;
 130         uint32_t busy_delay;
 131         uint32_t nand_ta;
 132         uint32_t rd_high;
 133         uint32_t rd_low;
 134         uint32_t wr_high;
 135         uint32_t wr_low;
 136         int wp_gpio;
 137         struct mtd_partition *parts;
 138         unsigned num_parts;
 139 };
 140
 141 static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section,
 142                                  struct mtd_oob_region *oobregion)
 143 {
 144         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 145
 146         if (section >= nand_chip->ecc.steps)
 147                 return -ERANGE;
 148
 149         oobregion->offset = ((section + 1) * 16) - nand_chip->ecc.bytes;
 150         oobregion->length = nand_chip->ecc.bytes;
 151
 152         return 0;
 153 }
 154
 155 static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section,
 156                                   struct mtd_oob_region *oobregion)
 157 {
 158         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 159
 160         if (section >= nand_chip->ecc.steps)
 161                 return -ERANGE;
 162
 163         oobregion->offset = 16 * section;
 164         oobregion->length = 16 - nand_chip->ecc.bytes;
 165
 166         return 0;
 167 }
 168
 169 static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = {
 170         .ecc = lpc32xx_ooblayout_ecc,
 171         .free = lpc32xx_ooblayout_free,
 172 };
 173
 174 static struct nand_bbt_descr lpc32xx_nand_bbt = {
 175         .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB |
 176                    NAND_BBT_WRITE,
 177         .pages = { 524224, 0, 0, 0, 0, 0, 0, 0 },
 178 };
 179
 180 static struct nand_bbt_descr lpc32xx_nand_bbt_mirror = {
 181         .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB |
 182                    NAND_BBT_WRITE,
 183         .pages = { 524160, 0, 0, 0, 0, 0, 0, 0 },
 184 };
 185
 186 struct lpc32xx_nand_host {
 187         struct platform_device  *pdev;
 188         struct nand_chip        nand_chip;
 189         struct lpc32xx_mlc_platform_data *pdata;
 190         struct clk              *clk;
 191         void __iomem            *io_base;
 192         int                     irq;
 193         struct lpc32xx_nand_cfg_mlc     *ncfg;
 194         struct completion       comp_nand;
 195         struct completion       comp_controller;
 196         uint32_t llptr;
 197         /*
 198          * Physical addresses of ECC buffer, DMA data buffers, OOB data buffer
 199          */
 200         dma_addr_t              oob_buf_phy;
 201         /*
 202          * Virtual addresses of ECC buffer, DMA data buffers, OOB data buffer
 203          */
 204         uint8_t                 *oob_buf;
 205         /* Physical address of DMA base address */
 206         dma_addr_t              io_base_phy;
 207
 208         struct completion       comp_dma;
 209         struct dma_chan         *dma_chan;
 210         struct dma_slave_config dma_slave_config;
 211         struct scatterlist      sgl;
 212         uint8_t                 *dma_buf;
 213         uint8_t                 *dummy_buf;
 214         int                     mlcsubpages; /* number of 512bytes-subpages */
 215 };
 216
 217 /*
 218  * Activate/Deactivate DMA Operation:
 219  *
 220  * Using the PL080 DMA Controller for transferring the 512 byte subpages
 221  * instead of doing readl() / writel() in a loop slows it down significantly.
 222  * Measurements via getnstimeofday() upon 512 byte subpage reads reveal:
 223  *
 224  * - readl() of 128 x 32 bits in a loop: ~20us
 225  * - DMA read of 512 bytes (32 bit, 4...128 words bursts): ~60us
 226  * - DMA read of 512 bytes (32 bit, no bursts): ~100us
 227  *
 228  * This applies to the transfer itself. In the DMA case: only the
 229  * wait_for_completion() (DMA setup _not_ included).
 230  *
 231  * Note that the 512 bytes subpage transfer is done directly from/to a
 232  * FIFO/buffer inside the NAND controller. Most of the time (~400-800us for a
 233  * 2048 bytes page) is spent waiting for the NAND IRQ, anyway. (The NAND
 234  * controller transferring data between its internal buffer to/from the NAND
 235  * chip.)
 236  *
 237  * Therefore, using the PL080 DMA is disabled by default, for now.
 238  *
 239  */
 240 static int use_dma;
 241
 242 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
 243 {
 244         uint32_t clkrate, tmp;
 245
 246         /* Reset MLC controller */
 247         writel(MLCCMD_RESET, MLC_CMD(host->io_base));
 248         udelay(1000);
 249
 250         /* Get base clock for MLC block */
 251         clkrate = clk_get_rate(host->clk);
 252         if (clkrate == 0)
 253                 clkrate = 104000000;
 254
 255         /* Unlock MLC_ICR
 256          * (among others, will be locked again automatically) */
 257         writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
 258
 259         /* Configure MLC Controller: Large Block, 5 Byte Address */
 260         tmp = MLCICR_LARGEBLOCK | MLCICR_LONGADDR;
 261         writel(tmp, MLC_ICR(host->io_base));
 262
 263         /* Unlock MLC_TIME_REG
 264          * (among others, will be locked again automatically) */
 265         writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
 266
 267         /* Compute clock setup values, see LPC and NAND manual */
 268         tmp = 0;
 269         tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1);
 270         tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1);
 271         tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1);
 272         tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1);
 273         tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low);
 274         tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1);
 275         tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low);
 276         writel(tmp, MLC_TIME_REG(host->io_base));
 277
 278         /* Enable IRQ for CONTROLLER_READY and NAND_READY */
 279         writeb(MLCIRQ_CONTROLLER_READY | MLCIRQ_NAND_READY,
 280                         MLC_IRQ_MR(host->io_base));
 281
 282         /* Normal nCE operation: nCE controlled by controller */
 283         writel(MLCCEH_NORMAL, MLC_CEH(host->io_base));
 284 }
 285
 286 /*
 287  * Hardware specific access to control lines
 288  */
 289 static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 290                                   unsigned int ctrl)
 291 {
 292         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 293         struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
 294
 295         if (cmd != NAND_CMD_NONE) {
 296                 if (ctrl & NAND_CLE)
 297                         writel(cmd, MLC_CMD(host->io_base));
 298                 else
 299                         writel(cmd, MLC_ADDR(host->io_base));
 300         }
 301 }
 302
 303 /*
 304  * Read Device Ready (NAND device _and_ controller ready)
 305  */
 306 static int lpc32xx_nand_device_ready(struct mtd_info *mtd)
 307 {
 308         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 309         struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
 310
 311         if ((readb(MLC_ISR(host->io_base)) &
 312              (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) ==
 313             (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY))
 314                 return  1;
 315
 316         return 0;
 317 }
 318
 319 static irqreturn_t lpc3xxx_nand_irq(int irq, struct lpc32xx_nand_host *host)
 320 {
 321         uint8_t sr;
 322
 323         /* Clear interrupt flag by reading status */
 324         sr = readb(MLC_IRQ_SR(host->io_base));
 325         if (sr & MLCIRQ_NAND_READY)
 326                 complete(&host->comp_nand);
 327         if (sr & MLCIRQ_CONTROLLER_READY)
 328                 complete(&host->comp_controller);
 329
 330         return IRQ_HANDLED;
 331 }
 332
 333 static int lpc32xx_waitfunc_nand(struct mtd_info *mtd, struct nand_chip *chip)
 334 {
 335         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 336
 337         if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)
 338                 goto exit;
 339
 340         wait_for_completion(&host->comp_nand);
 341
 342         while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) {
 343                 /* Seems to be delayed sometimes by controller */
 344                 dev_dbg(&mtd->dev, "Warning: NAND not ready.\n");
 345                 cpu_relax();
 346         }
 347
 348 exit:
 349         return NAND_STATUS_READY;
 350 }
 351
 352 static int lpc32xx_waitfunc_controller(struct mtd_info *mtd,
 353                                        struct nand_chip *chip)
 354 {
 355         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 356
 357         if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY)
 358                 goto exit;
 359
 360         wait_for_completion(&host->comp_controller);
 361
 362         while (!(readb(MLC_ISR(host->io_base)) &
 363                  MLCISR_CONTROLLER_READY)) {
 364                 dev_dbg(&mtd->dev, "Warning: Controller not ready.\n");
 365                 cpu_relax();
 366         }
 367
 368 exit:
 369         return NAND_STATUS_READY;
 370 }
 371
 372 static int lpc32xx_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
 373 {
 374         lpc32xx_waitfunc_nand(mtd, chip);
 375         lpc32xx_waitfunc_controller(mtd, chip);
 376
 377         return NAND_STATUS_READY;
 378 }
 379
 380 /*
 381  * Enable NAND write protect
 382  */
 383 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
 384 {
 385         if (gpio_is_valid(host->ncfg->wp_gpio))
 386                 gpio_set_value(host->ncfg->wp_gpio, 0);
 387 }
 388
 389 /*
 390  * Disable NAND write protect
 391  */
 392 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
 393 {
 394         if (gpio_is_valid(host->ncfg->wp_gpio))
 395                 gpio_set_value(host->ncfg->wp_gpio, 1);
 396 }
 397
 398 static void lpc32xx_dma_complete_func(void *completion)
 399 {
 400         complete(completion);
 401 }
 402
 403 static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len,
 404                             enum dma_transfer_direction dir)
 405 {
 406         struct nand_chip *chip = mtd_to_nand(mtd);
 407         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 408         struct dma_async_tx_descriptor *desc;
 409         int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 410         int res;
 411
 412         sg_init_one(&host->sgl, mem, len);
 413
 414         res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
 415                          DMA_BIDIRECTIONAL);
 416         if (res != 1) {
 417                 dev_err(mtd->dev.parent, "Failed to map sg list\n");
 418                 return -ENXIO;
 419         }
 420         desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
 421                                        flags);
 422         if (!desc) {
 423                 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
 424                 goto out1;
 425         }
 426
 427         init_completion(&host->comp_dma);
 428         desc->callback = lpc32xx_dma_complete_func;
 429         desc->callback_param = &host->comp_dma;
 430
 431         dmaengine_submit(desc);
 432         dma_async_issue_pending(host->dma_chan);
 433
 434         wait_for_completion_timeout(&host->comp_dma, msecs_to_jiffies(1000));
 435
 436         dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
 437                      DMA_BIDIRECTIONAL);
 438         return 0;
 439 out1:
 440         dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
 441                      DMA_BIDIRECTIONAL);
 442         return -ENXIO;
 443 }
 444
 445 static int lpc32xx_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 446                              uint8_t *buf, int oob_required, int page)
 447 {
 448         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 449         int i, j;
 450         uint8_t *oobbuf = chip->oob_poi;
 451         uint32_t mlc_isr;
 452         int res;
 453         uint8_t *dma_buf;
 454         bool dma_mapped;
 455
 456         if ((void *)buf <= high_memory) {
 457                 dma_buf = buf;
 458                 dma_mapped = true;
 459         } else {
 460                 dma_buf = host->dma_buf;
 461                 dma_mapped = false;
 462         }
 463
 464         /* Writing Command and Address */
 465         nand_read_page_op(chip, page, 0, NULL, 0);
 466
 467         /* For all sub-pages */
 468         for (i = 0; i < host->mlcsubpages; i++) {
 469                 /* Start Auto Decode Command */
 470                 writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base));
 471
 472                 /* Wait for Controller Ready */
 473                 lpc32xx_waitfunc_controller(mtd, chip);
 474
 475                 /* Check ECC Error status */
 476                 mlc_isr = readl(MLC_ISR(host->io_base));
 477                 if (mlc_isr & MLCISR_DECODER_FAILURE) {
 478                         mtd->ecc_stats.failed++;
 479                         dev_warn(&mtd->dev, "%s: DECODER_FAILURE\n", __func__);
 480                 } else if (mlc_isr & MLCISR_ERRORS_DETECTED) {
 481                         mtd->ecc_stats.corrected += ((mlc_isr >> 4) & 0x3) + 1;
 482                 }
 483
 484                 /* Read 512 + 16 Bytes */
 485                 if (use_dma) {
 486                         res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512,
 487                                                DMA_DEV_TO_MEM);
 488                         if (res)
 489                                 return res;
 490                 } else {
 491                         for (j = 0; j < (512 >> 2); j++) {
 492                                 *((uint32_t *)(buf)) =
 493                                         readl(MLC_BUFF(host->io_base));
 494                                 buf += 4;
 495                         }
 496                 }
 497                 for (j = 0; j < (16 >> 2); j++) {
 498                         *((uint32_t *)(oobbuf)) =
 499                                 readl(MLC_BUFF(host->io_base));
 500                         oobbuf += 4;
 501                 }
 502         }
 503
 504         if (use_dma && !dma_mapped)
 505                 memcpy(buf, dma_buf, mtd->writesize);
 506
 507         return 0;
 508 }
 509
 510 static int lpc32xx_write_page_lowlevel(struct mtd_info *mtd,
 511                                        struct nand_chip *chip,
 512                                        const uint8_t *buf, int oob_required,
 513                                        int page)
 514 {
 515         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 516         const uint8_t *oobbuf = chip->oob_poi;
 517         uint8_t *dma_buf = (uint8_t *)buf;
 518         int res;
 519         int i, j;
 520
 521         if (use_dma && (void *)buf >= high_memory) {
 522                 dma_buf = host->dma_buf;
 523                 memcpy(dma_buf, buf, mtd->writesize);
 524         }
 525
 526         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
 527
 528         for (i = 0; i < host->mlcsubpages; i++) {
 529                 /* Start Encode */
 530                 writeb(0x00, MLC_ECC_ENC_REG(host->io_base));
 531
 532                 /* Write 512 + 6 Bytes to Buffer */
 533                 if (use_dma) {
 534                         res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512,
 535                                                DMA_MEM_TO_DEV);
 536                         if (res)
 537                                 return res;
 538                 } else {
 539                         for (j = 0; j < (512 >> 2); j++) {
 540                                 writel(*((uint32_t *)(buf)),
 541                                        MLC_BUFF(host->io_base));
 542                                 buf += 4;
 543                         }
 544                 }
 545                 writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base));
 546                 oobbuf += 4;
 547                 writew(*((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base));
 548                 oobbuf += 12;
 549
 550                 /* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */
 551                 writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base));
 552
 553                 /* Wait for Controller Ready */
 554                 lpc32xx_waitfunc_controller(mtd, chip);
 555         }
 556
 557         return nand_prog_page_end_op(chip);
 558 }
 559
 560 static int lpc32xx_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 561                             int page)
 562 {
 563         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 564
 565         /* Read whole page - necessary with MLC controller! */
 566         lpc32xx_read_page(mtd, chip, host->dummy_buf, 1, page);
 567
 568         return 0;
 569 }
 570
 571 static int lpc32xx_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 572                               int page)
 573 {
 574         /* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */
 575         return 0;
 576 }
 577
 578 /* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */
 579 static void lpc32xx_ecc_enable(struct mtd_info *mtd, int mode)
 580 {
 581         /* Always enabled! */
 582 }
 583
 584 static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host)
 585 {
 586         struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
 587         dma_cap_mask_t mask;
 588
 589         if (!host->pdata || !host->pdata->dma_filter) {
 590                 dev_err(mtd->dev.parent, "no DMA platform data\n");
 591                 return -ENOENT;
 592         }
 593
 594         dma_cap_zero(mask);
 595         dma_cap_set(DMA_SLAVE, mask);
 596         host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
 597                                              "nand-mlc");
 598         if (!host->dma_chan) {
 599                 dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
 600                 return -EBUSY;
 601         }
 602
 603         /*
 604          * Set direction to a sensible value even if the dmaengine driver
 605          * should ignore it. With the default (DMA_MEM_TO_MEM), the amba-pl08x
 606          * driver criticizes it as "alien transfer direction".
 607          */
 608         host->dma_slave_config.direction = DMA_DEV_TO_MEM;
 609         host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 610         host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 611         host->dma_slave_config.src_maxburst = 128;
 612         host->dma_slave_config.dst_maxburst = 128;
 613         /* DMA controller does flow control: */
 614         host->dma_slave_config.device_fc = false;
 615         host->dma_slave_config.src_addr = MLC_BUFF(host->io_base_phy);
 616         host->dma_slave_config.dst_addr = MLC_BUFF(host->io_base_phy);
 617         if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
 618                 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
 619                 goto out1;
 620         }
 621
 622         return 0;
 623 out1:
 624         dma_release_channel(host->dma_chan);
 625         return -ENXIO;
 626 }
 627
 628 static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev)
 629 {
 630         struct lpc32xx_nand_cfg_mlc *ncfg;
 631         struct device_node *np = dev->of_node;
 632
 633         ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
 634         if (!ncfg)
 635                 return NULL;
 636
 637         of_property_read_u32(np, "nxp,tcea-delay", &ncfg->tcea_delay);
 638         of_property_read_u32(np, "nxp,busy-delay", &ncfg->busy_delay);
 639         of_property_read_u32(np, "nxp,nand-ta", &ncfg->nand_ta);
 640         of_property_read_u32(np, "nxp,rd-high", &ncfg->rd_high);
 641         of_property_read_u32(np, "nxp,rd-low", &ncfg->rd_low);
 642         of_property_read_u32(np, "nxp,wr-high", &ncfg->wr_high);
 643         of_property_read_u32(np, "nxp,wr-low", &ncfg->wr_low);
 644
 645         if (!ncfg->tcea_delay || !ncfg->busy_delay || !ncfg->nand_ta ||
 646             !ncfg->rd_high || !ncfg->rd_low || !ncfg->wr_high ||
 647             !ncfg->wr_low) {
 648                 dev_err(dev, "chip parameters not specified correctly\n");
 649                 return NULL;
 650         }
 651
 652         ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0);
 653
 654         return ncfg;
 655 }
 656
 657 static int lpc32xx_nand_attach_chip(struct nand_chip *chip)
 658 {
 659         struct mtd_info *mtd = nand_to_mtd(chip);
 660         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 661         struct device *dev = &host->pdev->dev;
 662
 663         host->dma_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
 664         if (!host->dma_buf)
 665                 return -ENOMEM;
 666
 667         host->dummy_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
 668         if (!host->dummy_buf)
 669                 return -ENOMEM;
 670
 671         chip->ecc.mode = NAND_ECC_HW;
 672         chip->ecc.size = 512;
 673         mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
 674         host->mlcsubpages = mtd->writesize / 512;
 675
 676         return 0;
 677 }
 678
 679 static const struct nand_controller_ops lpc32xx_nand_controller_ops = {
 680         .attach_chip = lpc32xx_nand_attach_chip,
 681 };
 682
 683 /*
 684  * Probe for NAND controller
 685  */
 686 static int lpc32xx_nand_probe(struct platform_device *pdev)
 687 {
 688         struct lpc32xx_nand_host *host;
 689         struct mtd_info *mtd;
 690         struct nand_chip *nand_chip;
 691         struct resource *rc;
 692         int res;
 693
 694         /* Allocate memory for the device structure (and zero it) */
 695         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 696         if (!host)
 697                 return -ENOMEM;
 698
 699         host->pdev = pdev;
 700
 701         rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 702         host->io_base = devm_ioremap_resource(&pdev->dev, rc);
 703         if (IS_ERR(host->io_base))
 704                 return PTR_ERR(host->io_base);
 705
 706         host->io_base_phy = rc->start;
 707
 708         nand_chip = &host->nand_chip;
 709         mtd = nand_to_mtd(nand_chip);
 710         if (pdev->dev.of_node)
 711                 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
 712         if (!host->ncfg) {
 713                 dev_err(&pdev->dev,
 714                         "Missing or bad NAND config from device tree\n");
 715                 return -ENOENT;
 716         }
 717         if (host->ncfg->wp_gpio == -EPROBE_DEFER)
 718                 return -EPROBE_DEFER;
 719         if (gpio_is_valid(host->ncfg->wp_gpio) &&
 720                         gpio_request(host->ncfg->wp_gpio, "NAND WP")) {
 721                 dev_err(&pdev->dev, "GPIO not available\n");
 722                 return -EBUSY;
 723         }
 724         lpc32xx_wp_disable(host);
 725
 726         host->pdata = dev_get_platdata(&pdev->dev);
 727
 728         /* link the private data structures */
 729         nand_set_controller_data(nand_chip, host);
 730         nand_set_flash_node(nand_chip, pdev->dev.of_node);
 731         mtd->dev.parent = &pdev->dev;
 732
 733         /* Get NAND clock */
 734         host->clk = clk_get(&pdev->dev, NULL);
 735         if (IS_ERR(host->clk)) {
 736                 dev_err(&pdev->dev, "Clock initialization failure\n");
 737                 res = -ENOENT;
 738                 goto free_gpio;
 739         }
 740         res = clk_prepare_enable(host->clk);
 741         if (res)
 742                 goto put_clk;
 743
 744         nand_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
 745         nand_chip->dev_ready = lpc32xx_nand_device_ready;
 746         nand_chip->chip_delay = 25; /* us */
 747         nand_chip->IO_ADDR_R = MLC_DATA(host->io_base);
 748         nand_chip->IO_ADDR_W = MLC_DATA(host->io_base);
 749
 750         /* Init NAND controller */
 751         lpc32xx_nand_setup(host);
 752
 753         platform_set_drvdata(pdev, host);
 754
 755         /* Initialize function pointers */
 756         nand_chip->ecc.hwctl = lpc32xx_ecc_enable;
 757         nand_chip->ecc.read_page_raw = lpc32xx_read_page;
 758         nand_chip->ecc.read_page = lpc32xx_read_page;
 759         nand_chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel;
 760         nand_chip->ecc.write_page = lpc32xx_write_page_lowlevel;
 761         nand_chip->ecc.write_oob = lpc32xx_write_oob;
 762         nand_chip->ecc.read_oob = lpc32xx_read_oob;
 763         nand_chip->ecc.strength = 4;
 764         nand_chip->ecc.bytes = 10;
 765         nand_chip->waitfunc = lpc32xx_waitfunc;
 766
 767         nand_chip->options = NAND_NO_SUBPAGE_WRITE;
 768         nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
 769         nand_chip->bbt_td = &lpc32xx_nand_bbt;
 770         nand_chip->bbt_md = &lpc32xx_nand_bbt_mirror;
 771
 772         if (use_dma) {
 773                 res = lpc32xx_dma_setup(host);
 774                 if (res) {
 775                         res = -EIO;
 776                         goto unprepare_clk;
 777                 }
 778         }
 779
 780         /* initially clear interrupt status */
 781         readb(MLC_IRQ_SR(host->io_base));
 782
 783         init_completion(&host->comp_nand);
 784         init_completion(&host->comp_controller);
 785
 786         host->irq = platform_get_irq(pdev, 0);
 787         if (host->irq < 0) {
 788                 dev_err(&pdev->dev, "failed to get platform irq\n");
 789                 res = -EINVAL;
 790                 goto release_dma_chan;
 791         }
 792
 793         if (request_irq(host->irq, (irq_handler_t)&lpc3xxx_nand_irq,
 794                         IRQF_TRIGGER_HIGH, DRV_NAME, host)) {
 795                 dev_err(&pdev->dev, "Error requesting NAND IRQ\n");
 796                 res = -ENXIO;
 797                 goto release_dma_chan;
 798         }
 799
 800         /*
 801          * Scan to find existence of the device and get the type of NAND device:
 802          * SMALL block or LARGE block.
 803          */
 804         nand_chip->dummy_controller.ops = &lpc32xx_nand_controller_ops;
 805         res = nand_scan(nand_chip, 1);
 806         if (res)
 807                 goto free_irq;
 808
 809         mtd->name = DRV_NAME;
 810
 811         res = mtd_device_register(mtd, host->ncfg->parts,
 812                                   host->ncfg->num_parts);
 813         if (res)
 814                 goto cleanup_nand;
 815
 816         return 0;
 817
 818 cleanup_nand:
 819         nand_cleanup(nand_chip);
 820 free_irq:
 821         free_irq(host->irq, host);
 822 release_dma_chan:
 823         if (use_dma)
 824                 dma_release_channel(host->dma_chan);
 825 unprepare_clk:
 826         clk_disable_unprepare(host->clk);
 827 put_clk:
 828         clk_put(host->clk);
 829 free_gpio:
 830         lpc32xx_wp_enable(host);
 831         gpio_free(host->ncfg->wp_gpio);
 832
 833         return res;
 834 }
 835
 836 /*
 837  * Remove NAND device
 838  */
 839 static int lpc32xx_nand_remove(struct platform_device *pdev)
 840 {
 841         struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
 842
 843         nand_release(&host->nand_chip);
 844         free_irq(host->irq, host);
 845         if (use_dma)
 846                 dma_release_channel(host->dma_chan);
 847
 848         clk_disable_unprepare(host->clk);
 849         clk_put(host->clk);
 850
 851         lpc32xx_wp_enable(host);
 852         gpio_free(host->ncfg->wp_gpio);
 853
 854         return 0;
 855 }
 856
 857 #ifdef CONFIG_PM
 858 static int lpc32xx_nand_resume(struct platform_device *pdev)
 859 {
 860         struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
 861         int ret;
 862
 863         /* Re-enable NAND clock */
 864         ret = clk_prepare_enable(host->clk);
 865         if (ret)
 866                 return ret;
 867
 868         /* Fresh init of NAND controller */
 869         lpc32xx_nand_setup(host);
 870
 871         /* Disable write protect */
 872         lpc32xx_wp_disable(host);
 873
 874         return 0;
 875 }
 876
 877 static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
 878 {
 879         struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
 880
 881         /* Enable write protect for safety */
 882         lpc32xx_wp_enable(host);
 883
 884         /* Disable clock */
 885         clk_disable_unprepare(host->clk);
 886         return 0;
 887 }
 888
 889 #else
 890 #define lpc32xx_nand_resume NULL
 891 #define lpc32xx_nand_suspend NULL
 892 #endif
 893
 894 static const struct of_device_id lpc32xx_nand_match[] = {
 895         { .compatible = "nxp,lpc3220-mlc" },
 896         { /* sentinel */ },
 897 };
 898 MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
 899
 900 static struct platform_driver lpc32xx_nand_driver = {
 901         .probe          = lpc32xx_nand_probe,
 902         .remove         = lpc32xx_nand_remove,
 903         .resume         = lpc32xx_nand_resume,
 904         .suspend        = lpc32xx_nand_suspend,
 905         .driver         = {
 906                 .name   = DRV_NAME,
 907                 .of_match_table = lpc32xx_nand_match,
 908         },
 909 };
 910
 911 module_platform_driver(lpc32xx_nand_driver);
 912
 913 MODULE_LICENSE("GPL");
 914 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
 915 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX MLC controller");