drivers/mtd/nand/raw/jz4740_nand.c

   1 /*
   2  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
   3  *  JZ4740 SoC NAND controller driver
   4  *
   5  *  This program is free software; you can redistribute it and/or modify it
   6  *  under  the terms of the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the License, or (at your
   8  *  option) any later version.
   9  *
  10  *  You should have received a copy of the GNU General Public License along
  11  *  with this program; if not, write to the Free Software Foundation, Inc.,
  12  *  675 Mass Ave, Cambridge, MA 02139, USA.
  13  *
  14  */
  15
  16 #include <linux/io.h>
  17 #include <linux/ioport.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/rawnand.h>
  25 #include <linux/mtd/partitions.h>
  26
  27 #include <linux/gpio/consumer.h>
  28
  29 #include <linux/platform_data/jz4740/jz4740_nand.h>
  30
  31 #define JZ_REG_NAND_CTRL        0x50
  32 #define JZ_REG_NAND_ECC_CTRL    0x100
  33 #define JZ_REG_NAND_DATA        0x104
  34 #define JZ_REG_NAND_PAR0        0x108
  35 #define JZ_REG_NAND_PAR1        0x10C
  36 #define JZ_REG_NAND_PAR2        0x110
  37 #define JZ_REG_NAND_IRQ_STAT    0x114
  38 #define JZ_REG_NAND_IRQ_CTRL    0x118
  39 #define JZ_REG_NAND_ERR(x)      (0x11C + ((x) << 2))
  40
  41 #define JZ_NAND_ECC_CTRL_PAR_READY      BIT(4)
  42 #define JZ_NAND_ECC_CTRL_ENCODING       BIT(3)
  43 #define JZ_NAND_ECC_CTRL_RS             BIT(2)
  44 #define JZ_NAND_ECC_CTRL_RESET          BIT(1)
  45 #define JZ_NAND_ECC_CTRL_ENABLE         BIT(0)
  46
  47 #define JZ_NAND_STATUS_ERR_COUNT        (BIT(31) | BIT(30) | BIT(29))
  48 #define JZ_NAND_STATUS_PAD_FINISH       BIT(4)
  49 #define JZ_NAND_STATUS_DEC_FINISH       BIT(3)
  50 #define JZ_NAND_STATUS_ENC_FINISH       BIT(2)
  51 #define JZ_NAND_STATUS_UNCOR_ERROR      BIT(1)
  52 #define JZ_NAND_STATUS_ERROR            BIT(0)
  53
  54 #define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
  55 #define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
  56 #define JZ_NAND_CTRL_ASSERT_CHIP_MASK 0xaa
  57
  58 #define JZ_NAND_MEM_CMD_OFFSET 0x08000
  59 #define JZ_NAND_MEM_ADDR_OFFSET 0x10000
  60
  61 struct jz_nand {
  62         struct nand_chip chip;
  63         void __iomem *base;
  64         struct resource *mem;
  65
  66         unsigned char banks[JZ_NAND_NUM_BANKS];
  67         void __iomem *bank_base[JZ_NAND_NUM_BANKS];
  68         struct resource *bank_mem[JZ_NAND_NUM_BANKS];
  69
  70         int selected_bank;
  71
  72         struct gpio_desc *busy_gpio;
  73         bool is_reading;
  74 };
  75
  76 static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
  77 {
  78         return container_of(mtd_to_nand(mtd), struct jz_nand, chip);
  79 }
  80
  81 static void jz_nand_select_chip(struct mtd_info *mtd, int chipnr)
  82 {
  83         struct jz_nand *nand = mtd_to_jz_nand(mtd);
  84         struct nand_chip *chip = mtd_to_nand(mtd);
  85         uint32_t ctrl;
  86         int banknr;
  87
  88         ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
  89         ctrl &= ~JZ_NAND_CTRL_ASSERT_CHIP_MASK;
  90
  91         if (chipnr == -1) {
  92                 banknr = -1;
  93         } else {
  94                 banknr = nand->banks[chipnr] - 1;
  95                 chip->IO_ADDR_R = nand->bank_base[banknr];
  96                 chip->IO_ADDR_W = nand->bank_base[banknr];
  97         }
  98         writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
  99
 100         nand->selected_bank = banknr;
 101 }
 102
 103 static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
 104 {
 105         struct jz_nand *nand = mtd_to_jz_nand(mtd);
 106         struct nand_chip *chip = mtd_to_nand(mtd);
 107         uint32_t reg;
 108         void __iomem *bank_base = nand->bank_base[nand->selected_bank];
 109
 110         BUG_ON(nand->selected_bank < 0);
 111
 112         if (ctrl & NAND_CTRL_CHANGE) {
 113                 BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
 114                 if (ctrl & NAND_ALE)
 115                         bank_base += JZ_NAND_MEM_ADDR_OFFSET;
 116                 else if (ctrl & NAND_CLE)
 117                         bank_base += JZ_NAND_MEM_CMD_OFFSET;
 118                 chip->IO_ADDR_W = bank_base;
 119
 120                 reg = readl(nand->base + JZ_REG_NAND_CTRL);
 121                 if (ctrl & NAND_NCE)
 122                         reg |= JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
 123                 else
 124                         reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
 125                 writel(reg, nand->base + JZ_REG_NAND_CTRL);
 126         }
 127         if (dat != NAND_CMD_NONE)
 128                 writeb(dat, chip->IO_ADDR_W);
 129 }
 130
 131 static int jz_nand_dev_ready(struct mtd_info *mtd)
 132 {
 133         struct jz_nand *nand = mtd_to_jz_nand(mtd);
 134         return gpiod_get_value_cansleep(nand->busy_gpio);
 135 }
 136
 137 static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
 138 {
 139         struct jz_nand *nand = mtd_to_jz_nand(mtd);
 140         uint32_t reg;
 141
 142         writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
 143         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 144
 145         reg |= JZ_NAND_ECC_CTRL_RESET;
 146         reg |= JZ_NAND_ECC_CTRL_ENABLE;
 147         reg |= JZ_NAND_ECC_CTRL_RS;
 148
 149         switch (mode) {
 150         case NAND_ECC_READ:
 151                 reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
 152                 nand->is_reading = true;
 153                 break;
 154         case NAND_ECC_WRITE:
 155                 reg |= JZ_NAND_ECC_CTRL_ENCODING;
 156                 nand->is_reading = false;
 157                 break;
 158         default:
 159                 break;
 160         }
 161
 162         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 163 }
 164
 165 static int jz_nand_calculate_ecc_rs(struct mtd_info *mtd, const uint8_t *dat,
 166         uint8_t *ecc_code)
 167 {
 168         struct jz_nand *nand = mtd_to_jz_nand(mtd);
 169         uint32_t reg, status;
 170         int i;
 171         unsigned int timeout = 1000;
 172         static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4,
 173                                                 0x8b, 0xff, 0xb7, 0x6f};
 174
 175         if (nand->is_reading)
 176                 return 0;
 177
 178         do {
 179                 status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
 180         } while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout);
 181
 182         if (timeout == 0)
 183             return -1;
 184
 185         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 186         reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
 187         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 188
 189         for (i = 0; i < 9; ++i)
 190                 ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
 191
 192         /* If the written data is completly 0xff, we also want to write 0xff as
 193          * ecc, otherwise we will get in trouble when doing subpage writes. */
 194         if (memcmp(ecc_code, empty_block_ecc, 9) == 0)
 195                 memset(ecc_code, 0xff, 9);
 196
 197         return 0;
 198 }
 199
 200 static void jz_nand_correct_data(uint8_t *dat, int index, int mask)
 201 {
 202         int offset = index & 0x7;
 203         uint16_t data;
 204
 205         index += (index >> 3);
 206
 207         data = dat[index];
 208         data |= dat[index+1] << 8;
 209
 210         mask ^= (data >> offset) & 0x1ff;
 211         data &= ~(0x1ff << offset);
 212         data |= (mask << offset);
 213
 214         dat[index] = data & 0xff;
 215         dat[index+1] = (data >> 8) & 0xff;
 216 }
 217
 218 static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat,
 219         uint8_t *read_ecc, uint8_t *calc_ecc)
 220 {
 221         struct jz_nand *nand = mtd_to_jz_nand(mtd);
 222         int i, error_count, index;
 223         uint32_t reg, status, error;
 224         unsigned int timeout = 1000;
 225
 226         for (i = 0; i < 9; ++i)
 227                 writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
 228
 229         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 230         reg |= JZ_NAND_ECC_CTRL_PAR_READY;
 231         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 232
 233         do {
 234                 status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
 235         } while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout);
 236
 237         if (timeout == 0)
 238                 return -ETIMEDOUT;
 239
 240         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 241         reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
 242         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 243
 244         if (status & JZ_NAND_STATUS_ERROR) {
 245                 if (status & JZ_NAND_STATUS_UNCOR_ERROR)
 246                         return -EBADMSG;
 247
 248                 error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
 249
 250                 for (i = 0; i < error_count; ++i) {
 251                         error = readl(nand->base + JZ_REG_NAND_ERR(i));
 252                         index = ((error >> 16) & 0x1ff) - 1;
 253                         if (index >= 0 && index < 512)
 254                                 jz_nand_correct_data(dat, index, error & 0x1ff);
 255                 }
 256
 257                 return error_count;
 258         }
 259
 260         return 0;
 261 }
 262
 263 static int jz_nand_ioremap_resource(struct platform_device *pdev,
 264         const char *name, struct resource **res, void *__iomem *base)
 265 {
 266         int ret;
 267
 268         *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
 269         if (!*res) {
 270                 dev_err(&pdev->dev, "Failed to get platform %s memory\n", name);
 271                 ret = -ENXIO;
 272                 goto err;
 273         }
 274
 275         *res = request_mem_region((*res)->start, resource_size(*res),
 276                                 pdev->name);
 277         if (!*res) {
 278                 dev_err(&pdev->dev, "Failed to request %s memory region\n", name);
 279                 ret = -EBUSY;
 280                 goto err;
 281         }
 282
 283         *base = ioremap((*res)->start, resource_size(*res));
 284         if (!*base) {
 285                 dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name);
 286                 ret = -EBUSY;
 287                 goto err_release_mem;
 288         }
 289
 290         return 0;
 291
 292 err_release_mem:
 293         release_mem_region((*res)->start, resource_size(*res));
 294 err:
 295         *res = NULL;
 296         *base = NULL;
 297         return ret;
 298 }
 299
 300 static inline void jz_nand_iounmap_resource(struct resource *res,
 301                                             void __iomem *base)
 302 {
 303         iounmap(base);
 304         release_mem_region(res->start, resource_size(res));
 305 }
 306
 307 static int jz_nand_detect_bank(struct platform_device *pdev,
 308                                struct jz_nand *nand, unsigned char bank,
 309                                size_t chipnr, uint8_t *nand_maf_id,
 310                                uint8_t *nand_dev_id)
 311 {
 312         int ret;
 313         char res_name[6];
 314         uint32_t ctrl;
 315         struct nand_chip *chip = &nand->chip;
 316         struct mtd_info *mtd = nand_to_mtd(chip);
 317         u8 id[2];
 318
 319         /* Request I/O resource. */
 320         sprintf(res_name, "bank%d", bank);
 321         ret = jz_nand_ioremap_resource(pdev, res_name,
 322                                         &nand->bank_mem[bank - 1],
 323                                         &nand->bank_base[bank - 1]);
 324         if (ret)
 325                 return ret;
 326
 327         /* Enable chip in bank. */
 328         ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
 329         ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
 330         writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
 331
 332         if (chipnr == 0) {
 333                 /* Detect first chip. */
 334                 ret = nand_scan(chip, 1);
 335                 if (ret)
 336                         goto notfound_id;
 337
 338                 /* Retrieve the IDs from the first chip. */
 339                 chip->select_chip(mtd, 0);
 340                 nand_reset_op(chip);
 341                 nand_readid_op(chip, 0, id, sizeof(id));
 342                 *nand_maf_id = id[0];
 343                 *nand_dev_id = id[1];
 344         } else {
 345                 /* Detect additional chip. */
 346                 chip->select_chip(mtd, chipnr);
 347                 nand_reset_op(chip);
 348                 nand_readid_op(chip, 0, id, sizeof(id));
 349                 if (*nand_maf_id != id[0] || *nand_dev_id != id[1]) {
 350                         ret = -ENODEV;
 351                         goto notfound_id;
 352                 }
 353
 354                 /* Update size of the MTD. */
 355                 chip->numchips++;
 356                 mtd->size += chip->chipsize;
 357         }
 358
 359         dev_info(&pdev->dev, "Found chip %zu on bank %i\n", chipnr, bank);
 360         return 0;
 361
 362 notfound_id:
 363         dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
 364         ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
 365         writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
 366         jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
 367                                  nand->bank_base[bank - 1]);
 368         return ret;
 369 }
 370
 371 static int jz_nand_attach_chip(struct nand_chip *chip)
 372 {
 373         struct mtd_info *mtd = nand_to_mtd(chip);
 374         struct device *dev = mtd->dev.parent;
 375         struct jz_nand_platform_data *pdata = dev_get_platdata(dev);
 376         struct platform_device *pdev = to_platform_device(dev);
 377
 378         if (pdata && pdata->ident_callback)
 379                 pdata->ident_callback(pdev, mtd, &pdata->partitions,
 380                                       &pdata->num_partitions);
 381
 382         return 0;
 383 }
 384
 385 static const struct nand_controller_ops jz_nand_controller_ops = {
 386         .attach_chip = jz_nand_attach_chip,
 387 };
 388
 389 static int jz_nand_probe(struct platform_device *pdev)
 390 {
 391         int ret;
 392         struct jz_nand *nand;
 393         struct nand_chip *chip;
 394         struct mtd_info *mtd;
 395         struct jz_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 396         size_t chipnr, bank_idx;
 397         uint8_t nand_maf_id = 0, nand_dev_id = 0;
 398
 399         nand = kzalloc(sizeof(*nand), GFP_KERNEL);
 400         if (!nand)
 401                 return -ENOMEM;
 402
 403         ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
 404         if (ret)
 405                 goto err_free;
 406
 407         nand->busy_gpio = devm_gpiod_get_optional(&pdev->dev, "busy", GPIOD_IN);
 408         if (IS_ERR(nand->busy_gpio)) {
 409                 ret = PTR_ERR(nand->busy_gpio);
 410                 dev_err(&pdev->dev, "Failed to request busy gpio %d\n",
 411                     ret);
 412                 goto err_iounmap_mmio;
 413         }
 414
 415         chip            = &nand->chip;
 416         mtd             = nand_to_mtd(chip);
 417         mtd->dev.parent = &pdev->dev;
 418         mtd->name       = "jz4740-nand";
 419
 420         chip->ecc.hwctl         = jz_nand_hwctl;
 421         chip->ecc.calculate     = jz_nand_calculate_ecc_rs;
 422         chip->ecc.correct       = jz_nand_correct_ecc_rs;
 423         chip->ecc.mode          = NAND_ECC_HW_OOB_FIRST;
 424         chip->ecc.size          = 512;
 425         chip->ecc.bytes         = 9;
 426         chip->ecc.strength      = 4;
 427         chip->ecc.options       = NAND_ECC_GENERIC_ERASED_CHECK;
 428
 429         chip->chip_delay = 50;
 430         chip->cmd_ctrl = jz_nand_cmd_ctrl;
 431         chip->select_chip = jz_nand_select_chip;
 432         chip->dummy_controller.ops = &jz_nand_controller_ops;
 433
 434         if (nand->busy_gpio)
 435                 chip->dev_ready = jz_nand_dev_ready;
 436
 437         platform_set_drvdata(pdev, nand);
 438
 439         /* We are going to autodetect NAND chips in the banks specified in the
 440          * platform data. Although nand_scan_ident() can detect multiple chips,
 441          * it requires those chips to be numbered consecuitively, which is not
 442          * always the case for external memory banks. And a fixed chip-to-bank
 443          * mapping is not practical either, since for example Dingoo units
 444          * produced at different times have NAND chips in different banks.
 445          */
 446         chipnr = 0;
 447         for (bank_idx = 0; bank_idx < JZ_NAND_NUM_BANKS; bank_idx++) {
 448                 unsigned char bank;
 449
 450                 /* If there is no platform data, look for NAND in bank 1,
 451                  * which is the most likely bank since it is the only one
 452                  * that can be booted from.
 453                  */
 454                 bank = pdata ? pdata->banks[bank_idx] : bank_idx ^ 1;
 455                 if (bank == 0)
 456                         break;
 457                 if (bank > JZ_NAND_NUM_BANKS) {
 458                         dev_warn(&pdev->dev,
 459                                 "Skipping non-existing bank: %d\n", bank);
 460                         continue;
 461                 }
 462                 /* The detection routine will directly or indirectly call
 463                  * jz_nand_select_chip(), so nand->banks has to contain the
 464                  * bank we're checking.
 465                  */
 466                 nand->banks[chipnr] = bank;
 467                 if (jz_nand_detect_bank(pdev, nand, bank, chipnr,
 468                                         &nand_maf_id, &nand_dev_id) == 0)
 469                         chipnr++;
 470                 else
 471                         nand->banks[chipnr] = 0;
 472         }
 473         if (chipnr == 0) {
 474                 dev_err(&pdev->dev, "No NAND chips found\n");
 475                 goto err_iounmap_mmio;
 476         }
 477
 478         ret = mtd_device_register(mtd, pdata ? pdata->partitions : NULL,
 479                                   pdata ? pdata->num_partitions : 0);
 480
 481         if (ret) {
 482                 dev_err(&pdev->dev, "Failed to add mtd device\n");
 483                 goto err_cleanup_nand;
 484         }
 485
 486         dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
 487
 488         return 0;
 489
 490 err_cleanup_nand:
 491         nand_cleanup(chip);
 492         while (chipnr--) {
 493                 unsigned char bank = nand->banks[chipnr];
 494                 jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
 495                                          nand->bank_base[bank - 1]);
 496         }
 497         writel(0, nand->base + JZ_REG_NAND_CTRL);
 498 err_iounmap_mmio:
 499         jz_nand_iounmap_resource(nand->mem, nand->base);
 500 err_free:
 501         kfree(nand);
 502         return ret;
 503 }
 504
 505 static int jz_nand_remove(struct platform_device *pdev)
 506 {
 507         struct jz_nand *nand = platform_get_drvdata(pdev);
 508         size_t i;
 509
 510         nand_release(&nand->chip);
 511
 512         /* Deassert and disable all chips */
 513         writel(0, nand->base + JZ_REG_NAND_CTRL);
 514
 515         for (i = 0; i < JZ_NAND_NUM_BANKS; ++i) {
 516                 unsigned char bank = nand->banks[i];
 517                 if (bank != 0) {
 518                         jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
 519                                                  nand->bank_base[bank - 1]);
 520                 }
 521         }
 522
 523         jz_nand_iounmap_resource(nand->mem, nand->base);
 524
 525         kfree(nand);
 526
 527         return 0;
 528 }
 529
 530 static struct platform_driver jz_nand_driver = {
 531         .probe = jz_nand_probe,
 532         .remove = jz_nand_remove,
 533         .driver = {
 534                 .name = "jz4740-nand",
 535         },
 536 };
 537
 538 module_platform_driver(jz_nand_driver);
 539
 540 MODULE_LICENSE("GPL");
 541 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 542 MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC");
 543 MODULE_ALIAS("platform:jz4740-nand");