drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Ingenic JZ47xx NAND driver
   4  *
   5  * Copyright (c) 2015 Imagination Technologies
   6  * Author: Alex Smith <alex.smith@imgtec.com>
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <linux/init.h>
  11 #include <linux/io.h>
  12 #include <linux/list.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_device.h>
  17 #include <linux/gpio/consumer.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/slab.h>
  20 #include <linux/mtd/mtd.h>
  21 #include <linux/mtd/rawnand.h>
  22 #include <linux/mtd/partitions.h>
  23
  24 #include <linux/jz4780-nemc.h>
  25
  26 #include "ingenic_ecc.h"
  27
  28 #define DRV_NAME        "ingenic-nand"
  29
  30 struct jz_soc_info {
  31         unsigned long data_offset;
  32         unsigned long addr_offset;
  33         unsigned long cmd_offset;
  34         const struct mtd_ooblayout_ops *oob_layout;
  35         bool oob_first;
  36 };
  37
  38 struct ingenic_nand_cs {
  39         unsigned int bank;
  40         void __iomem *base;
  41 };
  42
  43 struct ingenic_nfc {
  44         struct device *dev;
  45         struct ingenic_ecc *ecc;
  46         const struct jz_soc_info *soc_info;
  47         struct nand_controller controller;
  48         unsigned int num_banks;
  49         struct list_head chips;
  50         struct ingenic_nand_cs cs[];
  51 };
  52
  53 struct ingenic_nand {
  54         struct nand_chip chip;
  55         struct list_head chip_list;
  56
  57         struct gpio_desc *busy_gpio;
  58         struct gpio_desc *wp_gpio;
  59         unsigned int reading: 1;
  60 };
  61
  62 static inline struct ingenic_nand *to_ingenic_nand(struct mtd_info *mtd)
  63 {
  64         return container_of(mtd_to_nand(mtd), struct ingenic_nand, chip);
  65 }
  66
  67 static inline struct ingenic_nfc *to_ingenic_nfc(struct nand_controller *ctrl)
  68 {
  69         return container_of(ctrl, struct ingenic_nfc, controller);
  70 }
  71
  72 static int qi_lb60_ooblayout_ecc(struct mtd_info *mtd, int section,
  73                                  struct mtd_oob_region *oobregion)
  74 {
  75         struct nand_chip *chip = mtd_to_nand(mtd);
  76         struct nand_ecc_ctrl *ecc = &chip->ecc;
  77
  78         if (section || !ecc->total)
  79                 return -ERANGE;
  80
  81         oobregion->length = ecc->total;
  82         oobregion->offset = 12;
  83
  84         return 0;
  85 }
  86
  87 static int qi_lb60_ooblayout_free(struct mtd_info *mtd, int section,
  88                                   struct mtd_oob_region *oobregion)
  89 {
  90         struct nand_chip *chip = mtd_to_nand(mtd);
  91         struct nand_ecc_ctrl *ecc = &chip->ecc;
  92
  93         if (section)
  94                 return -ERANGE;
  95
  96         oobregion->length = mtd->oobsize - ecc->total - 12;
  97         oobregion->offset = 12 + ecc->total;
  98
  99         return 0;
 100 }
 101
 102 static const struct mtd_ooblayout_ops qi_lb60_ooblayout_ops = {
 103         .ecc = qi_lb60_ooblayout_ecc,
 104         .free = qi_lb60_ooblayout_free,
 105 };
 106
 107 static int jz4725b_ooblayout_ecc(struct mtd_info *mtd, int section,
 108                                  struct mtd_oob_region *oobregion)
 109 {
 110         struct nand_chip *chip = mtd_to_nand(mtd);
 111         struct nand_ecc_ctrl *ecc = &chip->ecc;
 112
 113         if (section || !ecc->total)
 114                 return -ERANGE;
 115
 116         oobregion->length = ecc->total;
 117         oobregion->offset = 3;
 118
 119         return 0;
 120 }
 121
 122 static int jz4725b_ooblayout_free(struct mtd_info *mtd, int section,
 123                                   struct mtd_oob_region *oobregion)
 124 {
 125         struct nand_chip *chip = mtd_to_nand(mtd);
 126         struct nand_ecc_ctrl *ecc = &chip->ecc;
 127
 128         if (section)
 129                 return -ERANGE;
 130
 131         oobregion->length = mtd->oobsize - ecc->total - 3;
 132         oobregion->offset = 3 + ecc->total;
 133
 134         return 0;
 135 }
 136
 137 static const struct mtd_ooblayout_ops jz4725b_ooblayout_ops = {
 138         .ecc = jz4725b_ooblayout_ecc,
 139         .free = jz4725b_ooblayout_free,
 140 };
 141
 142 static void ingenic_nand_ecc_hwctl(struct nand_chip *chip, int mode)
 143 {
 144         struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
 145
 146         nand->reading = (mode == NAND_ECC_READ);
 147 }
 148
 149 static int ingenic_nand_ecc_calculate(struct nand_chip *chip, const u8 *dat,
 150                                       u8 *ecc_code)
 151 {
 152         struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
 153         struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
 154         struct ingenic_ecc_params params;
 155
 156         /*
 157          * Don't need to generate the ECC when reading, the ECC engine does it
 158          * for us as part of decoding/correction.
 159          */
 160         if (nand->reading)
 161                 return 0;
 162
 163         params.size = nand->chip.ecc.size;
 164         params.bytes = nand->chip.ecc.bytes;
 165         params.strength = nand->chip.ecc.strength;
 166
 167         return ingenic_ecc_calculate(nfc->ecc, &params, dat, ecc_code);
 168 }
 169
 170 static int ingenic_nand_ecc_correct(struct nand_chip *chip, u8 *dat,
 171                                     u8 *read_ecc, u8 *calc_ecc)
 172 {
 173         struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
 174         struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
 175         struct ingenic_ecc_params params;
 176
 177         params.size = nand->chip.ecc.size;
 178         params.bytes = nand->chip.ecc.bytes;
 179         params.strength = nand->chip.ecc.strength;
 180
 181         return ingenic_ecc_correct(nfc->ecc, &params, dat, read_ecc);
 182 }
 183
 184 static int ingenic_nand_attach_chip(struct nand_chip *chip)
 185 {
 186         struct mtd_info *mtd = nand_to_mtd(chip);
 187         struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
 188         int eccbytes;
 189
 190         if (chip->ecc.strength == 4) {
 191                 /* JZ4740 uses 9 bytes of ECC to correct maximum 4 errors */
 192                 chip->ecc.bytes = 9;
 193         } else {
 194                 chip->ecc.bytes = fls((1 + 8) * chip->ecc.size) *
 195                                   (chip->ecc.strength / 8);
 196         }
 197
 198         switch (chip->ecc.engine_type) {
 199         case NAND_ECC_ENGINE_TYPE_ON_HOST:
 200                 if (!nfc->ecc) {
 201                         dev_err(nfc->dev, "HW ECC selected, but ECC controller not found\n");
 202                         return -ENODEV;
 203                 }
 204
 205                 chip->ecc.hwctl = ingenic_nand_ecc_hwctl;
 206                 chip->ecc.calculate = ingenic_nand_ecc_calculate;
 207                 chip->ecc.correct = ingenic_nand_ecc_correct;
 208                 fallthrough;
 209         case NAND_ECC_ENGINE_TYPE_SOFT:
 210                 dev_info(nfc->dev, "using %s (strength %d, size %d, bytes %d)\n",
 211                          (nfc->ecc) ? "hardware ECC" : "software ECC",
 212                          chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
 213                 break;
 214         case NAND_ECC_ENGINE_TYPE_NONE:
 215                 dev_info(nfc->dev, "not using ECC\n");
 216                 break;
 217         default:
 218                 dev_err(nfc->dev, "ECC mode %d not supported\n",
 219                         chip->ecc.engine_type);
 220                 return -EINVAL;
 221         }
 222
 223         /* The NAND core will generate the ECC layout for SW ECC */
 224         if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
 225                 return 0;
 226
 227         /* Generate ECC layout. ECC codes are right aligned in the OOB area. */
 228         eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
 229
 230         if (eccbytes > mtd->oobsize - 2) {
 231                 dev_err(nfc->dev,
 232                         "invalid ECC config: required %d ECC bytes, but only %d are available",
 233                         eccbytes, mtd->oobsize - 2);
 234                 return -EINVAL;
 235         }
 236
 237         /*
 238          * The generic layout for BBT markers will most likely overlap with our
 239          * ECC bytes in the OOB, so move the BBT markers outside the OOB area.
 240          */
 241         if (chip->bbt_options & NAND_BBT_USE_FLASH)
 242                 chip->bbt_options |= NAND_BBT_NO_OOB;
 243
 244         if (nfc->soc_info->oob_first)
 245                 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
 246
 247         /* For legacy reasons we use a different layout on the qi,lb60 board. */
 248         if (of_machine_is_compatible("qi,lb60"))
 249                 mtd_set_ooblayout(mtd, &qi_lb60_ooblayout_ops);
 250         else if (nfc->soc_info->oob_layout)
 251                 mtd_set_ooblayout(mtd, nfc->soc_info->oob_layout);
 252         else
 253                 mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
 254
 255         return 0;
 256 }
 257
 258 static int ingenic_nand_exec_instr(struct nand_chip *chip,
 259                                    struct ingenic_nand_cs *cs,
 260                                    const struct nand_op_instr *instr)
 261 {
 262         struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
 263         struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
 264         unsigned int i;
 265
 266         switch (instr->type) {
 267         case NAND_OP_CMD_INSTR:
 268                 writeb(instr->ctx.cmd.opcode,
 269                        cs->base + nfc->soc_info->cmd_offset);
 270                 return 0;
 271         case NAND_OP_ADDR_INSTR:
 272                 for (i = 0; i < instr->ctx.addr.naddrs; i++)
 273                         writeb(instr->ctx.addr.addrs[i],
 274                                cs->base + nfc->soc_info->addr_offset);
 275                 return 0;
 276         case NAND_OP_DATA_IN_INSTR:
 277                 if (instr->ctx.data.force_8bit ||
 278                     !(chip->options & NAND_BUSWIDTH_16))
 279                         ioread8_rep(cs->base + nfc->soc_info->data_offset,
 280                                     instr->ctx.data.buf.in,
 281                                     instr->ctx.data.len);
 282                 else
 283                         ioread16_rep(cs->base + nfc->soc_info->data_offset,
 284                                      instr->ctx.data.buf.in,
 285                                      instr->ctx.data.len);
 286                 return 0;
 287         case NAND_OP_DATA_OUT_INSTR:
 288                 if (instr->ctx.data.force_8bit ||
 289                     !(chip->options & NAND_BUSWIDTH_16))
 290                         iowrite8_rep(cs->base + nfc->soc_info->data_offset,
 291                                      instr->ctx.data.buf.out,
 292                                      instr->ctx.data.len);
 293                 else
 294                         iowrite16_rep(cs->base + nfc->soc_info->data_offset,
 295                                       instr->ctx.data.buf.out,
 296                                       instr->ctx.data.len);
 297                 return 0;
 298         case NAND_OP_WAITRDY_INSTR:
 299                 if (!nand->busy_gpio)
 300                         return nand_soft_waitrdy(chip,
 301                                                  instr->ctx.waitrdy.timeout_ms);
 302
 303                 return nand_gpio_waitrdy(chip, nand->busy_gpio,
 304                                          instr->ctx.waitrdy.timeout_ms);
 305         default:
 306                 break;
 307         }
 308
 309         return -EINVAL;
 310 }
 311
 312 static int ingenic_nand_exec_op(struct nand_chip *chip,
 313                                 const struct nand_operation *op,
 314                                 bool check_only)
 315 {
 316         struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
 317         struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
 318         struct ingenic_nand_cs *cs;
 319         unsigned int i;
 320         int ret = 0;
 321
 322         if (check_only)
 323                 return 0;
 324
 325         cs = &nfc->cs[op->cs];
 326         jz4780_nemc_assert(nfc->dev, cs->bank, true);
 327         for (i = 0; i < op->ninstrs; i++) {
 328                 ret = ingenic_nand_exec_instr(chip, cs, &op->instrs[i]);
 329                 if (ret)
 330                         break;
 331
 332                 if (op->instrs[i].delay_ns)
 333                         ndelay(op->instrs[i].delay_ns);
 334         }
 335         jz4780_nemc_assert(nfc->dev, cs->bank, false);
 336
 337         return ret;
 338 }
 339
 340 static const struct nand_controller_ops ingenic_nand_controller_ops = {
 341         .attach_chip = ingenic_nand_attach_chip,
 342         .exec_op = ingenic_nand_exec_op,
 343 };
 344
 345 static int ingenic_nand_init_chip(struct platform_device *pdev,
 346                                   struct ingenic_nfc *nfc,
 347                                   struct device_node *np,
 348                                   unsigned int chipnr)
 349 {
 350         struct device *dev = &pdev->dev;
 351         struct ingenic_nand *nand;
 352         struct ingenic_nand_cs *cs;
 353         struct nand_chip *chip;
 354         struct mtd_info *mtd;
 355         const __be32 *reg;
 356         int ret = 0;
 357
 358         cs = &nfc->cs[chipnr];
 359
 360         reg = of_get_property(np, "reg", NULL);
 361         if (!reg)
 362                 return -EINVAL;
 363
 364         cs->bank = be32_to_cpu(*reg);
 365
 366         jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
 367
 368         cs->base = devm_platform_ioremap_resource(pdev, chipnr);
 369         if (IS_ERR(cs->base))
 370                 return PTR_ERR(cs->base);
 371
 372         nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
 373         if (!nand)
 374                 return -ENOMEM;
 375
 376         nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
 377
 378         if (IS_ERR(nand->busy_gpio)) {
 379                 ret = PTR_ERR(nand->busy_gpio);
 380                 dev_err(dev, "failed to request busy GPIO: %d\n", ret);
 381                 return ret;
 382         }
 383
 384         /*
 385          * The rb-gpios semantics was undocumented and qi,lb60 (along with
 386          * the ingenic driver) got it wrong. The active state encodes the
 387          * NAND ready state, which is high level. Since there's no signal
 388          * inverter on this board, it should be active-high. Let's fix that
 389          * here for older DTs so we can re-use the generic nand_gpio_waitrdy()
 390          * helper, and be consistent with what other drivers do.
 391          */
 392         if (of_machine_is_compatible("qi,lb60") &&
 393             gpiod_is_active_low(nand->busy_gpio))
 394                 gpiod_toggle_active_low(nand->busy_gpio);
 395
 396         nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
 397
 398         if (IS_ERR(nand->wp_gpio)) {
 399                 ret = PTR_ERR(nand->wp_gpio);
 400                 dev_err(dev, "failed to request WP GPIO: %d\n", ret);
 401                 return ret;
 402         }
 403
 404         chip = &nand->chip;
 405         mtd = nand_to_mtd(chip);
 406         mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
 407                                    cs->bank);
 408         if (!mtd->name)
 409                 return -ENOMEM;
 410         mtd->dev.parent = dev;
 411
 412         chip->options = NAND_NO_SUBPAGE_WRITE;
 413         chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
 414         chip->controller = &nfc->controller;
 415         nand_set_flash_node(chip, np);
 416
 417         chip->controller->ops = &ingenic_nand_controller_ops;
 418         ret = nand_scan(chip, 1);
 419         if (ret)
 420                 return ret;
 421
 422         ret = mtd_device_register(mtd, NULL, 0);
 423         if (ret) {
 424                 nand_cleanup(chip);
 425                 return ret;
 426         }
 427
 428         list_add_tail(&nand->chip_list, &nfc->chips);
 429
 430         return 0;
 431 }
 432
 433 static void ingenic_nand_cleanup_chips(struct ingenic_nfc *nfc)
 434 {
 435         struct ingenic_nand *ingenic_chip;
 436         struct nand_chip *chip;
 437         int ret;
 438
 439         while (!list_empty(&nfc->chips)) {
 440                 ingenic_chip = list_first_entry(&nfc->chips,
 441                                                 struct ingenic_nand, chip_list);
 442                 chip = &ingenic_chip->chip;
 443                 ret = mtd_device_unregister(nand_to_mtd(chip));
 444                 WARN_ON(ret);
 445                 nand_cleanup(chip);
 446                 list_del(&ingenic_chip->chip_list);
 447         }
 448 }
 449
 450 static int ingenic_nand_init_chips(struct ingenic_nfc *nfc,
 451                                    struct platform_device *pdev)
 452 {
 453         struct device *dev = &pdev->dev;
 454         struct device_node *np;
 455         int i = 0;
 456         int ret;
 457         int num_chips = of_get_child_count(dev->of_node);
 458
 459         if (num_chips > nfc->num_banks) {
 460                 dev_err(dev, "found %d chips but only %d banks\n",
 461                         num_chips, nfc->num_banks);
 462                 return -EINVAL;
 463         }
 464
 465         for_each_child_of_node(dev->of_node, np) {
 466                 ret = ingenic_nand_init_chip(pdev, nfc, np, i);
 467                 if (ret) {
 468                         ingenic_nand_cleanup_chips(nfc);
 469                         of_node_put(np);
 470                         return ret;
 471                 }
 472
 473                 i++;
 474         }
 475
 476         return 0;
 477 }
 478
 479 static int ingenic_nand_probe(struct platform_device *pdev)
 480 {
 481         struct device *dev = &pdev->dev;
 482         unsigned int num_banks;
 483         struct ingenic_nfc *nfc;
 484         int ret;
 485
 486         num_banks = jz4780_nemc_num_banks(dev);
 487         if (num_banks == 0) {
 488                 dev_err(dev, "no banks found\n");
 489                 return -ENODEV;
 490         }
 491
 492         nfc = devm_kzalloc(dev, struct_size(nfc, cs, num_banks), GFP_KERNEL);
 493         if (!nfc)
 494                 return -ENOMEM;
 495
 496         nfc->soc_info = device_get_match_data(dev);
 497         if (!nfc->soc_info)
 498                 return -EINVAL;
 499
 500         /*
 501          * Check for ECC HW before we call nand_scan_ident, to prevent us from
 502          * having to call it again if the ECC driver returns -EPROBE_DEFER.
 503          */
 504         nfc->ecc = of_ingenic_ecc_get(dev->of_node);
 505         if (IS_ERR(nfc->ecc))
 506                 return PTR_ERR(nfc->ecc);
 507
 508         nfc->dev = dev;
 509         nfc->num_banks = num_banks;
 510
 511         nand_controller_init(&nfc->controller);
 512         INIT_LIST_HEAD(&nfc->chips);
 513
 514         ret = ingenic_nand_init_chips(nfc, pdev);
 515         if (ret) {
 516                 if (nfc->ecc)
 517                         ingenic_ecc_release(nfc->ecc);
 518                 return ret;
 519         }
 520
 521         platform_set_drvdata(pdev, nfc);
 522         return 0;
 523 }
 524
 525 static int ingenic_nand_remove(struct platform_device *pdev)
 526 {
 527         struct ingenic_nfc *nfc = platform_get_drvdata(pdev);
 528
 529         if (nfc->ecc)
 530                 ingenic_ecc_release(nfc->ecc);
 531
 532         ingenic_nand_cleanup_chips(nfc);
 533
 534         return 0;
 535 }
 536
 537 static const struct jz_soc_info jz4740_soc_info = {
 538         .data_offset = 0x00000000,
 539         .cmd_offset = 0x00008000,
 540         .addr_offset = 0x00010000,
 541         .oob_first = true,
 542 };
 543
 544 static const struct jz_soc_info jz4725b_soc_info = {
 545         .data_offset = 0x00000000,
 546         .cmd_offset = 0x00008000,
 547         .addr_offset = 0x00010000,
 548         .oob_layout = &jz4725b_ooblayout_ops,
 549 };
 550
 551 static const struct jz_soc_info jz4780_soc_info = {
 552         .data_offset = 0x00000000,
 553         .cmd_offset = 0x00400000,
 554         .addr_offset = 0x00800000,
 555 };
 556
 557 static const struct of_device_id ingenic_nand_dt_match[] = {
 558         { .compatible = "ingenic,jz4740-nand", .data = &jz4740_soc_info },
 559         { .compatible = "ingenic,jz4725b-nand", .data = &jz4725b_soc_info },
 560         { .compatible = "ingenic,jz4780-nand", .data = &jz4780_soc_info },
 561         {},
 562 };
 563 MODULE_DEVICE_TABLE(of, ingenic_nand_dt_match);
 564
 565 static struct platform_driver ingenic_nand_driver = {
 566         .probe          = ingenic_nand_probe,
 567         .remove         = ingenic_nand_remove,
 568         .driver = {
 569                 .name   = DRV_NAME,
 570                 .of_match_table = ingenic_nand_dt_match,
 571         },
 572 };
 573 module_platform_driver(ingenic_nand_driver);
 574
 575 MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
 576 MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");
 577 MODULE_DESCRIPTION("Ingenic JZ47xx NAND driver");
 578 MODULE_LICENSE("GPL v2");