drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Freescale GPMI NAND Flash Driver
   4  *
   5  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   6  * Copyright 2008 Embedded Alley Solutions, Inc.
   7  */
   8 #ifndef __GPMI_NAND_GPMI_REGS_H
   9 #define __GPMI_NAND_GPMI_REGS_H
  10
  11 #define HW_GPMI_CTRL0                                   0x00000000
  12 #define HW_GPMI_CTRL0_SET                               0x00000004
  13 #define HW_GPMI_CTRL0_CLR                               0x00000008
  14 #define HW_GPMI_CTRL0_TOG                               0x0000000c
  15
  16 #define BP_GPMI_CTRL0_COMMAND_MODE                      24
  17 #define BM_GPMI_CTRL0_COMMAND_MODE      (3 << BP_GPMI_CTRL0_COMMAND_MODE)
  18 #define BF_GPMI_CTRL0_COMMAND_MODE(v)   \
  19         (((v) << BP_GPMI_CTRL0_COMMAND_MODE) & BM_GPMI_CTRL0_COMMAND_MODE)
  20 #define BV_GPMI_CTRL0_COMMAND_MODE__WRITE               0x0
  21 #define BV_GPMI_CTRL0_COMMAND_MODE__READ                0x1
  22 #define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE    0x2
  23 #define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY      0x3
  24
  25 #define BM_GPMI_CTRL0_WORD_LENGTH                       (1 << 23)
  26 #define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT               0x0
  27 #define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT                0x1
  28
  29 /*
  30  *  Difference in LOCK_CS between imx23 and imx28 :
  31  *  This bit may impact the _POWER_ consumption. So some chips
  32  *  do not set it.
  33  */
  34 #define MX23_BP_GPMI_CTRL0_LOCK_CS                      22
  35 #define MX28_BP_GPMI_CTRL0_LOCK_CS                      27
  36 #define LOCK_CS_ENABLE                                  0x1
  37 #define BF_GPMI_CTRL0_LOCK_CS(v, x)                     0x0
  38
  39 /* Difference in CS between imx23 and imx28 */
  40 #define BP_GPMI_CTRL0_CS                                20
  41 #define MX23_BM_GPMI_CTRL0_CS           (3 << BP_GPMI_CTRL0_CS)
  42 #define MX28_BM_GPMI_CTRL0_CS           (7 << BP_GPMI_CTRL0_CS)
  43 #define BF_GPMI_CTRL0_CS(v, x)          (((v) << BP_GPMI_CTRL0_CS) & \
  44                                                 (GPMI_IS_MX23((x)) \
  45                                                 ? MX23_BM_GPMI_CTRL0_CS \
  46                                                 : MX28_BM_GPMI_CTRL0_CS))
  47
  48 #define BP_GPMI_CTRL0_ADDRESS                           17
  49 #define BM_GPMI_CTRL0_ADDRESS           (3 << BP_GPMI_CTRL0_ADDRESS)
  50 #define BF_GPMI_CTRL0_ADDRESS(v)        \
  51                 (((v) << BP_GPMI_CTRL0_ADDRESS) & BM_GPMI_CTRL0_ADDRESS)
  52 #define BV_GPMI_CTRL0_ADDRESS__NAND_DATA                0x0
  53 #define BV_GPMI_CTRL0_ADDRESS__NAND_CLE                 0x1
  54 #define BV_GPMI_CTRL0_ADDRESS__NAND_ALE                 0x2
  55
  56 #define BM_GPMI_CTRL0_ADDRESS_INCREMENT                 (1 << 16)
  57 #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED       0x0
  58 #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED        0x1
  59
  60 #define BP_GPMI_CTRL0_XFER_COUNT                        0
  61 #define BM_GPMI_CTRL0_XFER_COUNT        (0xffff << BP_GPMI_CTRL0_XFER_COUNT)
  62 #define BF_GPMI_CTRL0_XFER_COUNT(v)     \
  63                 (((v) << BP_GPMI_CTRL0_XFER_COUNT) & BM_GPMI_CTRL0_XFER_COUNT)
  64
  65 #define HW_GPMI_COMPARE                                 0x00000010
  66
  67 #define HW_GPMI_ECCCTRL                                 0x00000020
  68 #define HW_GPMI_ECCCTRL_SET                             0x00000024
  69 #define HW_GPMI_ECCCTRL_CLR                             0x00000028
  70 #define HW_GPMI_ECCCTRL_TOG                             0x0000002c
  71
  72 #define BP_GPMI_ECCCTRL_ECC_CMD                         13
  73 #define BM_GPMI_ECCCTRL_ECC_CMD         (3 << BP_GPMI_ECCCTRL_ECC_CMD)
  74 #define BF_GPMI_ECCCTRL_ECC_CMD(v)      \
  75                 (((v) << BP_GPMI_ECCCTRL_ECC_CMD) & BM_GPMI_ECCCTRL_ECC_CMD)
  76 #define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE             0x0
  77 #define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE             0x1
  78
  79 #define BM_GPMI_ECCCTRL_ENABLE_ECC                      (1 << 12)
  80 #define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE              0x1
  81 #define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE             0x0
  82
  83 #define BP_GPMI_ECCCTRL_BUFFER_MASK                     0
  84 #define BM_GPMI_ECCCTRL_BUFFER_MASK     (0x1ff << BP_GPMI_ECCCTRL_BUFFER_MASK)
  85 #define BF_GPMI_ECCCTRL_BUFFER_MASK(v)  \
  86         (((v) << BP_GPMI_ECCCTRL_BUFFER_MASK) & BM_GPMI_ECCCTRL_BUFFER_MASK)
  87 #define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY        0x100
  88 #define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE           0x1FF
  89
  90 #define HW_GPMI_ECCCOUNT                                0x00000030
  91 #define HW_GPMI_PAYLOAD                                 0x00000040
  92 #define HW_GPMI_AUXILIARY                               0x00000050
  93 #define HW_GPMI_CTRL1                                   0x00000060
  94 #define HW_GPMI_CTRL1_SET                               0x00000064
  95 #define HW_GPMI_CTRL1_CLR                               0x00000068
  96 #define HW_GPMI_CTRL1_TOG                               0x0000006c
  97
  98 #define BP_GPMI_CTRL1_DECOUPLE_CS                       24
  99 #define BM_GPMI_CTRL1_DECOUPLE_CS       (1 << BP_GPMI_CTRL1_DECOUPLE_CS)
 100
 101 #define BP_GPMI_CTRL1_WRN_DLY_SEL                       22
 102 #define BM_GPMI_CTRL1_WRN_DLY_SEL       (0x3 << BP_GPMI_CTRL1_WRN_DLY_SEL)
 103 #define BF_GPMI_CTRL1_WRN_DLY_SEL(v)  \
 104         (((v) << BP_GPMI_CTRL1_WRN_DLY_SEL) & BM_GPMI_CTRL1_WRN_DLY_SEL)
 105 #define BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS              0x0
 106 #define BV_GPMI_CTRL1_WRN_DLY_SEL_6_TO_10NS             0x1
 107 #define BV_GPMI_CTRL1_WRN_DLY_SEL_7_TO_12NS             0x2
 108 #define BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY              0x3
 109
 110 #define BM_GPMI_CTRL1_BCH_MODE                          (1 << 18)
 111
 112 #define BP_GPMI_CTRL1_DLL_ENABLE                        17
 113 #define BM_GPMI_CTRL1_DLL_ENABLE        (1 << BP_GPMI_CTRL1_DLL_ENABLE)
 114
 115 #define BP_GPMI_CTRL1_HALF_PERIOD                       16
 116 #define BM_GPMI_CTRL1_HALF_PERIOD       (1 << BP_GPMI_CTRL1_HALF_PERIOD)
 117
 118 #define BP_GPMI_CTRL1_RDN_DELAY                         12
 119 #define BM_GPMI_CTRL1_RDN_DELAY         (0xf << BP_GPMI_CTRL1_RDN_DELAY)
 120 #define BF_GPMI_CTRL1_RDN_DELAY(v)      \
 121                 (((v) << BP_GPMI_CTRL1_RDN_DELAY) & BM_GPMI_CTRL1_RDN_DELAY)
 122
 123 #define BM_GPMI_CTRL1_DEV_RESET                         (1 << 3)
 124 #define BV_GPMI_CTRL1_DEV_RESET__ENABLED                0x0
 125 #define BV_GPMI_CTRL1_DEV_RESET__DISABLED               0x1
 126
 127 #define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY               (1 << 2)
 128 #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW    0x0
 129 #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH   0x1
 130
 131 #define BM_GPMI_CTRL1_CAMERA_MODE                       (1 << 1)
 132 #define BV_GPMI_CTRL1_GPMI_MODE__NAND                   0x0
 133 #define BV_GPMI_CTRL1_GPMI_MODE__ATA                    0x1
 134
 135 #define BM_GPMI_CTRL1_GPMI_MODE                         (1 << 0)
 136
 137 #define BM_GPMI_CTRL1_CLEAR_MASK (BM_GPMI_CTRL1_WRN_DLY_SEL | \
 138                                   BM_GPMI_CTRL1_DLL_ENABLE |  \
 139                                   BM_GPMI_CTRL1_RDN_DELAY |   \
 140                                   BM_GPMI_CTRL1_HALF_PERIOD)
 141
 142 #define HW_GPMI_TIMING0                                 0x00000070
 143
 144 #define BP_GPMI_TIMING0_ADDRESS_SETUP                   16
 145 #define BM_GPMI_TIMING0_ADDRESS_SETUP   (0xff << BP_GPMI_TIMING0_ADDRESS_SETUP)
 146 #define BF_GPMI_TIMING0_ADDRESS_SETUP(v)        \
 147         (((v) << BP_GPMI_TIMING0_ADDRESS_SETUP) & BM_GPMI_TIMING0_ADDRESS_SETUP)
 148
 149 #define BP_GPMI_TIMING0_DATA_HOLD                       8
 150 #define BM_GPMI_TIMING0_DATA_HOLD       (0xff << BP_GPMI_TIMING0_DATA_HOLD)
 151 #define BF_GPMI_TIMING0_DATA_HOLD(v)            \
 152         (((v) << BP_GPMI_TIMING0_DATA_HOLD) & BM_GPMI_TIMING0_DATA_HOLD)
 153
 154 #define BP_GPMI_TIMING0_DATA_SETUP                      0
 155 #define BM_GPMI_TIMING0_DATA_SETUP      (0xff << BP_GPMI_TIMING0_DATA_SETUP)
 156 #define BF_GPMI_TIMING0_DATA_SETUP(v)           \
 157         (((v) << BP_GPMI_TIMING0_DATA_SETUP) & BM_GPMI_TIMING0_DATA_SETUP)
 158
 159 #define HW_GPMI_TIMING1                                 0x00000080
 160 #define BP_GPMI_TIMING1_BUSY_TIMEOUT                    16
 161 #define BM_GPMI_TIMING1_BUSY_TIMEOUT    (0xffff << BP_GPMI_TIMING1_BUSY_TIMEOUT)
 162 #define BF_GPMI_TIMING1_BUSY_TIMEOUT(v)         \
 163         (((v) << BP_GPMI_TIMING1_BUSY_TIMEOUT) & BM_GPMI_TIMING1_BUSY_TIMEOUT)
 164
 165 #define HW_GPMI_TIMING2                                 0x00000090
 166 #define HW_GPMI_DATA                                    0x000000a0
 167
 168 /* MX28 uses this to detect READY. */
 169 #define HW_GPMI_STAT                                    0x000000b0
 170 #define MX28_BP_GPMI_STAT_READY_BUSY                    24
 171 #define MX28_BM_GPMI_STAT_READY_BUSY    (0xff << MX28_BP_GPMI_STAT_READY_BUSY)
 172 #define MX28_BF_GPMI_STAT_READY_BUSY(v)         \
 173         (((v) << MX28_BP_GPMI_STAT_READY_BUSY) & MX28_BM_GPMI_STAT_READY_BUSY)
 174
 175 /* MX23 uses this to detect READY. */
 176 #define HW_GPMI_DEBUG                                   0x000000c0
 177 #define MX23_BP_GPMI_DEBUG_READY0                       28
 178 #define MX23_BM_GPMI_DEBUG_READY0       (1 << MX23_BP_GPMI_DEBUG_READY0)
 179 #endif