1 // SPDX-License-Identifier: GPL-2.0
4 * Flexible Static Memory Controller (FSMC)
5 * Driver for NAND portions
7 * Copyright © 2010 ST Microelectronics
8 * Vipin Kumar <vipin.kumar@st.com>
11 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
12 * Copyright © 2007 STMicroelectronics Pvt. Ltd.
13 * Copyright © 2009 Alessandro Rubini
16 #include <linux/clk.h>
17 #include <linux/completion.h>
18 #include <linux/delay.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dma-direction.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/err.h>
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/resource.h>
26 #include <linux/sched.h>
27 #include <linux/types.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/rawnand.h>
30 #include <linux/mtd/nand_ecc.h>
31 #include <linux/platform_device.h>
33 #include <linux/mtd/partitions.h>
35 #include <linux/slab.h>
36 #include <linux/amba/bus.h>
37 #include <mtd/mtd-abi.h>
39 /* fsmc controller registers for NOR flash */
41 /* ctrl register definitions */
42 #define BANK_ENABLE BIT(0)
44 #define NOR_DEV (2 << 2)
45 #define WIDTH_16 BIT(4)
46 #define RSTPWRDWN BIT(6)
48 #define WRT_ENABLE BIT(12)
49 #define WAIT_ENB BIT(13)
52 /* ctrl_tim register definitions */
54 #define FSMC_NOR_BANK_SZ 0x8
55 #define FSMC_NOR_REG_SIZE 0x40
57 #define FSMC_NOR_REG(base, bank, reg) ((base) + \
58 (FSMC_NOR_BANK_SZ * (bank)) + \
61 /* fsmc controller registers for NAND flash */
63 /* pc register definitions */
64 #define FSMC_RESET BIT(0)
65 #define FSMC_WAITON BIT(1)
66 #define FSMC_ENABLE BIT(2)
67 #define FSMC_DEVTYPE_NAND BIT(3)
68 #define FSMC_DEVWID_16 BIT(4)
69 #define FSMC_ECCEN BIT(6)
70 #define FSMC_ECCPLEN_256 BIT(7)
71 #define FSMC_TCLR_SHIFT (9)
72 #define FSMC_TCLR_MASK (0xF)
73 #define FSMC_TAR_SHIFT (13)
74 #define FSMC_TAR_MASK (0xF)
76 /* sts register definitions */
77 #define FSMC_CODE_RDY BIT(15)
79 /* comm register definitions */
80 #define FSMC_TSET_SHIFT 0
81 #define FSMC_TSET_MASK 0xFF
82 #define FSMC_TWAIT_SHIFT 8
83 #define FSMC_TWAIT_MASK 0xFF
84 #define FSMC_THOLD_SHIFT 16
85 #define FSMC_THOLD_MASK 0xFF
86 #define FSMC_THIZ_SHIFT 24
87 #define FSMC_THIZ_MASK 0xFF
93 #define FSMC_NAND_BANK_SZ 0x20
95 #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
98 * According to SPEAr300 Reference Manual (RM0082)
99 * TOUDEL = 7ns (Output delay from the flip-flops to the board)
100 * TINDEL = 5ns (Input delay from the board to the flipflop)
105 struct fsmc_nand_timings {
120 * struct fsmc_nand_data - structure for FSMC NAND device state
122 * @base: Inherit from the nand_controller struct
123 * @pid: Part ID on the AMBA PrimeCell format
124 * @nand: Chip related info for a NAND flash.
126 * @bank: Bank number for probed device.
127 * @dev: Parent device
129 * @clk: Clock structure for FSMC.
131 * @read_dma_chan: DMA channel for read access
132 * @write_dma_chan: DMA channel for write access to NAND
133 * @dma_access_complete: Completion structure
135 * @dev_timings: NAND timings
137 * @data_pa: NAND Physical port for Data.
138 * @data_va: NAND port for Data.
139 * @cmd_va: NAND port for Command.
140 * @addr_va: NAND port for Address.
141 * @regs_va: Registers base address for a given bank.
143 struct fsmc_nand_data {
144 struct nand_controller base;
146 struct nand_chip nand;
150 enum access_mode mode;
153 /* DMA related objects */
154 struct dma_chan *read_dma_chan;
155 struct dma_chan *write_dma_chan;
156 struct completion dma_access_complete;
158 struct fsmc_nand_timings *dev_timings;
161 void __iomem *data_va;
162 void __iomem *cmd_va;
163 void __iomem *addr_va;
164 void __iomem *regs_va;
167 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
168 struct mtd_oob_region *oobregion)
170 struct nand_chip *chip = mtd_to_nand(mtd);
172 if (section >= chip->ecc.steps)
175 oobregion->offset = (section * 16) + 2;
176 oobregion->length = 3;
181 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
182 struct mtd_oob_region *oobregion)
184 struct nand_chip *chip = mtd_to_nand(mtd);
186 if (section >= chip->ecc.steps)
189 oobregion->offset = (section * 16) + 8;
191 if (section < chip->ecc.steps - 1)
192 oobregion->length = 8;
194 oobregion->length = mtd->oobsize - oobregion->offset;
199 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
200 .ecc = fsmc_ecc1_ooblayout_ecc,
201 .free = fsmc_ecc1_ooblayout_free,
205 * ECC placement definitions in oobfree type format.
206 * There are 13 bytes of ecc for every 512 byte block and it has to be read
207 * consecutively and immediately after the 512 byte data block for hardware to
208 * generate the error bit offsets in 512 byte data.
210 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
211 struct mtd_oob_region *oobregion)
213 struct nand_chip *chip = mtd_to_nand(mtd);
215 if (section >= chip->ecc.steps)
218 oobregion->length = chip->ecc.bytes;
220 if (!section && mtd->writesize <= 512)
221 oobregion->offset = 0;
223 oobregion->offset = (section * 16) + 2;
228 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
229 struct mtd_oob_region *oobregion)
231 struct nand_chip *chip = mtd_to_nand(mtd);
233 if (section >= chip->ecc.steps)
236 oobregion->offset = (section * 16) + 15;
238 if (section < chip->ecc.steps - 1)
239 oobregion->length = 3;
241 oobregion->length = mtd->oobsize - oobregion->offset;
246 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
247 .ecc = fsmc_ecc4_ooblayout_ecc,
248 .free = fsmc_ecc4_ooblayout_free,
251 static inline struct fsmc_nand_data *nand_to_fsmc(struct nand_chip *chip)
253 return container_of(chip, struct fsmc_nand_data, nand);
257 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
259 * This routine initializes timing parameters related to NAND memory access in
262 static void fsmc_nand_setup(struct fsmc_nand_data *host,
263 struct fsmc_nand_timings *tims)
265 u32 value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
266 u32 tclr, tar, thiz, thold, twait, tset;
268 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
269 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
270 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
271 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
272 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
273 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
275 if (host->nand.options & NAND_BUSWIDTH_16)
276 value |= FSMC_DEVWID_16;
278 writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC);
279 writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM);
280 writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB);
283 static int fsmc_calc_timings(struct fsmc_nand_data *host,
284 const struct nand_sdr_timings *sdrt,
285 struct fsmc_nand_timings *tims)
287 unsigned long hclk = clk_get_rate(host->clk);
288 unsigned long hclkn = NSEC_PER_SEC / hclk;
289 u32 thiz, thold, twait, tset, twait_min;
291 if (sdrt->tRC_min < 30000)
294 tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1;
295 if (tims->tar > FSMC_TAR_MASK)
296 tims->tar = FSMC_TAR_MASK;
297 tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1;
298 if (tims->tclr > FSMC_TCLR_MASK)
299 tims->tclr = FSMC_TCLR_MASK;
301 thiz = sdrt->tCS_min - sdrt->tWP_min;
302 tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn);
304 thold = sdrt->tDH_min;
305 if (thold < sdrt->tCH_min)
306 thold = sdrt->tCH_min;
307 if (thold < sdrt->tCLH_min)
308 thold = sdrt->tCLH_min;
309 if (thold < sdrt->tWH_min)
310 thold = sdrt->tWH_min;
311 if (thold < sdrt->tALH_min)
312 thold = sdrt->tALH_min;
313 if (thold < sdrt->tREH_min)
314 thold = sdrt->tREH_min;
315 tims->thold = DIV_ROUND_UP(thold / 1000, hclkn);
316 if (tims->thold == 0)
318 else if (tims->thold > FSMC_THOLD_MASK)
319 tims->thold = FSMC_THOLD_MASK;
321 tset = max(sdrt->tCS_min - sdrt->tWP_min,
322 sdrt->tCEA_max - sdrt->tREA_max);
323 tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
326 else if (tims->tset > FSMC_TSET_MASK)
327 tims->tset = FSMC_TSET_MASK;
330 * According to SPEAr300 Reference Manual (RM0082) which gives more
331 * information related to FSMSC timings than the SPEAr600 one (RM0305),
332 * twait >= tCEA - (tset * TCLK) + TOUTDEL + TINDEL
334 twait_min = sdrt->tCEA_max - ((tims->tset + 1) * hclkn * 1000)
336 twait = max3(sdrt->tRP_min, sdrt->tWP_min, twait_min);
338 tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
339 if (tims->twait == 0)
341 else if (tims->twait > FSMC_TWAIT_MASK)
342 tims->twait = FSMC_TWAIT_MASK;
347 static int fsmc_setup_interface(struct nand_chip *nand, int csline,
348 const struct nand_interface_config *conf)
350 struct fsmc_nand_data *host = nand_to_fsmc(nand);
351 struct fsmc_nand_timings tims;
352 const struct nand_sdr_timings *sdrt;
355 sdrt = nand_get_sdr_timings(conf);
357 return PTR_ERR(sdrt);
359 ret = fsmc_calc_timings(host, sdrt, &tims);
363 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
366 fsmc_nand_setup(host, &tims);
372 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
374 static void fsmc_enable_hwecc(struct nand_chip *chip, int mode)
376 struct fsmc_nand_data *host = nand_to_fsmc(chip);
378 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256,
379 host->regs_va + FSMC_PC);
380 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN,
381 host->regs_va + FSMC_PC);
382 writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN,
383 host->regs_va + FSMC_PC);
387 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
388 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
391 static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const u8 *data,
394 struct fsmc_nand_data *host = nand_to_fsmc(chip);
396 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
399 if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY)
403 } while (!time_after_eq(jiffies, deadline));
405 if (time_after_eq(jiffies, deadline)) {
406 dev_err(host->dev, "calculate ecc timed out\n");
410 ecc_tmp = readl_relaxed(host->regs_va + ECC1);
412 ecc[1] = ecc_tmp >> 8;
413 ecc[2] = ecc_tmp >> 16;
414 ecc[3] = ecc_tmp >> 24;
416 ecc_tmp = readl_relaxed(host->regs_va + ECC2);
418 ecc[5] = ecc_tmp >> 8;
419 ecc[6] = ecc_tmp >> 16;
420 ecc[7] = ecc_tmp >> 24;
422 ecc_tmp = readl_relaxed(host->regs_va + ECC3);
424 ecc[9] = ecc_tmp >> 8;
425 ecc[10] = ecc_tmp >> 16;
426 ecc[11] = ecc_tmp >> 24;
428 ecc_tmp = readl_relaxed(host->regs_va + STS);
429 ecc[12] = ecc_tmp >> 16;
435 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
436 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
439 static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data,
442 struct fsmc_nand_data *host = nand_to_fsmc(chip);
445 ecc_tmp = readl_relaxed(host->regs_va + ECC1);
447 ecc[1] = ecc_tmp >> 8;
448 ecc[2] = ecc_tmp >> 16;
453 /* Count the number of 0's in buff upto a max of max_bits */
454 static int count_written_bits(u8 *buff, int size, int max_bits)
456 int k, written_bits = 0;
458 for (k = 0; k < size; k++) {
459 written_bits += hweight8(~buff[k]);
460 if (written_bits > max_bits)
467 static void dma_complete(void *param)
469 struct fsmc_nand_data *host = param;
471 complete(&host->dma_access_complete);
474 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
475 enum dma_data_direction direction)
477 struct dma_chan *chan;
478 struct dma_device *dma_dev;
479 struct dma_async_tx_descriptor *tx;
480 dma_addr_t dma_dst, dma_src, dma_addr;
482 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
484 unsigned long time_left;
486 if (direction == DMA_TO_DEVICE)
487 chan = host->write_dma_chan;
488 else if (direction == DMA_FROM_DEVICE)
489 chan = host->read_dma_chan;
493 dma_dev = chan->device;
494 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
496 if (direction == DMA_TO_DEVICE) {
498 dma_dst = host->data_pa;
500 dma_src = host->data_pa;
504 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
507 dev_err(host->dev, "device_prep_dma_memcpy error\n");
512 tx->callback = dma_complete;
513 tx->callback_param = host;
514 cookie = tx->tx_submit(tx);
516 ret = dma_submit_error(cookie);
518 dev_err(host->dev, "dma_submit_error %d\n", cookie);
522 dma_async_issue_pending(chan);
525 wait_for_completion_timeout(&host->dma_access_complete,
526 msecs_to_jiffies(3000));
527 if (time_left == 0) {
528 dmaengine_terminate_all(chan);
529 dev_err(host->dev, "wait_for_completion_timeout\n");
537 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
543 * fsmc_write_buf - write buffer to chip
544 * @host: FSMC NAND controller
546 * @len: number of bytes to write
548 static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf,
553 if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
554 IS_ALIGNED(len, sizeof(u32))) {
558 for (i = 0; i < len; i++)
559 writel_relaxed(p[i], host->data_va);
561 for (i = 0; i < len; i++)
562 writeb_relaxed(buf[i], host->data_va);
567 * fsmc_read_buf - read chip data into buffer
568 * @host: FSMC NAND controller
569 * @buf: buffer to store date
570 * @len: number of bytes to read
572 static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len)
576 if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
577 IS_ALIGNED(len, sizeof(u32))) {
581 for (i = 0; i < len; i++)
582 p[i] = readl_relaxed(host->data_va);
584 for (i = 0; i < len; i++)
585 buf[i] = readb_relaxed(host->data_va);
590 * fsmc_read_buf_dma - read chip data into buffer
591 * @host: FSMC NAND controller
592 * @buf: buffer to store date
593 * @len: number of bytes to read
595 static void fsmc_read_buf_dma(struct fsmc_nand_data *host, u8 *buf,
598 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
602 * fsmc_write_buf_dma - write buffer to chip
603 * @host: FSMC NAND controller
605 * @len: number of bytes to write
607 static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf,
610 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
614 * fsmc_exec_op - hook called by the core to execute NAND operations
616 * This controller is simple enough and thus does not need to use the parser
617 * provided by the core, instead, handle every situation here.
619 static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
622 struct fsmc_nand_data *host = nand_to_fsmc(chip);
623 const struct nand_op_instr *instr = NULL;
631 pr_debug("Executing operation [%d instructions]:\n", op->ninstrs);
633 for (op_id = 0; op_id < op->ninstrs; op_id++) {
634 instr = &op->instrs[op_id];
636 nand_op_trace(" ", instr);
638 switch (instr->type) {
639 case NAND_OP_CMD_INSTR:
640 writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va);
643 case NAND_OP_ADDR_INSTR:
644 for (i = 0; i < instr->ctx.addr.naddrs; i++)
645 writeb_relaxed(instr->ctx.addr.addrs[i],
649 case NAND_OP_DATA_IN_INSTR:
650 if (host->mode == USE_DMA_ACCESS)
651 fsmc_read_buf_dma(host, instr->ctx.data.buf.in,
652 instr->ctx.data.len);
654 fsmc_read_buf(host, instr->ctx.data.buf.in,
655 instr->ctx.data.len);
658 case NAND_OP_DATA_OUT_INSTR:
659 if (host->mode == USE_DMA_ACCESS)
660 fsmc_write_buf_dma(host,
661 instr->ctx.data.buf.out,
662 instr->ctx.data.len);
664 fsmc_write_buf(host, instr->ctx.data.buf.out,
665 instr->ctx.data.len);
668 case NAND_OP_WAITRDY_INSTR:
669 ret = nand_soft_waitrdy(chip,
670 instr->ctx.waitrdy.timeout_ms);
675 ndelay(instr->delay_ns);
682 * fsmc_read_page_hwecc
683 * @chip: nand chip info structure
684 * @buf: buffer to store read data
685 * @oob_required: caller expects OOB data read to chip->oob_poi
686 * @page: page number to read
688 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
689 * performed in a strict sequence as follows:
690 * data(512 byte) -> ecc(13 byte)
691 * After this read, fsmc hardware generates and reports error data bits(up to a
694 static int fsmc_read_page_hwecc(struct nand_chip *chip, u8 *buf,
695 int oob_required, int page)
697 struct mtd_info *mtd = nand_to_mtd(chip);
698 int i, j, s, stat, eccsize = chip->ecc.size;
699 int eccbytes = chip->ecc.bytes;
700 int eccsteps = chip->ecc.steps;
702 u8 *ecc_calc = chip->ecc.calc_buf;
703 u8 *ecc_code = chip->ecc.code_buf;
704 int off, len, ret, group = 0;
706 * ecc_oob is intentionally taken as u16. In 16bit devices, we
707 * end up reading 14 bytes (7 words) from oob. The local array is
708 * to maintain word alignment
711 u8 *oob = (u8 *)&ecc_oob[0];
712 unsigned int max_bitflips = 0;
714 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
715 nand_read_page_op(chip, page, s * eccsize, NULL, 0);
716 chip->ecc.hwctl(chip, NAND_ECC_READ);
717 ret = nand_read_data_op(chip, p, eccsize, false, false);
721 for (j = 0; j < eccbytes;) {
722 struct mtd_oob_region oobregion;
724 ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
728 off = oobregion.offset;
729 len = oobregion.length;
732 * length is intentionally kept a higher multiple of 2
733 * to read at least 13 bytes even in case of 16 bit NAND
736 if (chip->options & NAND_BUSWIDTH_16)
737 len = roundup(len, 2);
739 nand_read_oob_op(chip, page, off, oob + j, len);
743 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
744 chip->ecc.calculate(chip, p, &ecc_calc[i]);
746 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
748 mtd->ecc_stats.failed++;
750 mtd->ecc_stats.corrected += stat;
751 max_bitflips = max_t(unsigned int, max_bitflips, stat);
759 * fsmc_bch8_correct_data
760 * @mtd: mtd info structure
761 * @dat: buffer of read data
762 * @read_ecc: ecc read from device spare area
763 * @calc_ecc: ecc calculated from read data
765 * calc_ecc is a 104 bit information containing maximum of 8 error
766 * offset information of 13 bits each in 512 bytes of read data.
768 static int fsmc_bch8_correct_data(struct nand_chip *chip, u8 *dat,
769 u8 *read_ecc, u8 *calc_ecc)
771 struct fsmc_nand_data *host = nand_to_fsmc(chip);
774 u32 ecc1, ecc2, ecc3, ecc4;
776 num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF;
778 /* no bit flipping */
779 if (likely(num_err == 0))
782 /* too many errors */
783 if (unlikely(num_err > 8)) {
785 * This is a temporary erase check. A newly erased page read
786 * would result in an ecc error because the oob data is also
787 * erased to FF and the calculated ecc for an FF data is not
789 * This is a workaround to skip performing correction in case
793 * For every page, each bit written as 0 is counted until these
794 * number of bits are greater than 8 (the maximum correction
795 * capability of FSMC for each 512 + 13 bytes)
798 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
799 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
801 if ((bits_ecc + bits_data) <= 8) {
803 memset(dat, 0xff, chip->ecc.size);
811 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
812 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
814 * calc_ecc is a 104 bit information containing maximum of 8 error
815 * offset information of 13 bits each. calc_ecc is copied into a
816 * u64 array and error offset indexes are populated in err_idx
819 ecc1 = readl_relaxed(host->regs_va + ECC1);
820 ecc2 = readl_relaxed(host->regs_va + ECC2);
821 ecc3 = readl_relaxed(host->regs_va + ECC3);
822 ecc4 = readl_relaxed(host->regs_va + STS);
824 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
825 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
826 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
827 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
828 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
829 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
830 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
831 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
837 if (err_idx[i] < chip->ecc.size * 8) {
838 int err = err_idx[i];
840 dat[err >> 3] ^= BIT(err & 7);
847 static bool filter(struct dma_chan *chan, void *slave)
849 chan->private = slave;
853 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
854 struct fsmc_nand_data *host,
855 struct nand_chip *nand)
857 struct device_node *np = pdev->dev.of_node;
863 if (!of_property_read_u32(np, "bank-width", &val)) {
865 nand->options |= NAND_BUSWIDTH_16;
866 } else if (val != 1) {
867 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
872 if (of_get_property(np, "nand-skip-bbtscan", NULL))
873 nand->options |= NAND_SKIP_BBTSCAN;
875 host->dev_timings = devm_kzalloc(&pdev->dev,
876 sizeof(*host->dev_timings),
878 if (!host->dev_timings)
881 ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
882 sizeof(*host->dev_timings));
884 host->dev_timings = NULL;
886 /* Set default NAND bank to 0 */
888 if (!of_property_read_u32(np, "bank", &val)) {
890 dev_err(&pdev->dev, "invalid bank %u\n", val);
898 static int fsmc_nand_attach_chip(struct nand_chip *nand)
900 struct mtd_info *mtd = nand_to_mtd(nand);
901 struct fsmc_nand_data *host = nand_to_fsmc(nand);
903 if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
904 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
907 nand->ecc.size = 512;
909 if (AMBA_REV_BITS(host->pid) >= 8) {
910 nand->ecc.read_page = fsmc_read_page_hwecc;
911 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
912 nand->ecc.correct = fsmc_bch8_correct_data;
913 nand->ecc.bytes = 13;
914 nand->ecc.strength = 8;
917 if (AMBA_REV_BITS(host->pid) >= 8) {
918 switch (mtd->oobsize) {
927 "No oob scheme defined for oobsize %d\n",
932 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
937 switch (nand->ecc.engine_type) {
938 case NAND_ECC_ENGINE_TYPE_ON_HOST:
939 dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
940 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
941 nand->ecc.correct = nand_correct_data;
942 nand->ecc.hwctl = fsmc_enable_hwecc;
944 nand->ecc.strength = 1;
945 nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
948 case NAND_ECC_ENGINE_TYPE_SOFT:
949 if (nand->ecc.algo == NAND_ECC_ALGO_BCH) {
951 "Using 4-bit SW BCH ECC scheme\n");
955 case NAND_ECC_ENGINE_TYPE_ON_DIE:
959 dev_err(host->dev, "Unsupported ECC mode!\n");
964 * Don't set layout for BCH4 SW ECC. This will be
965 * generated later in nand_bch_init() later.
967 if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
968 switch (mtd->oobsize) {
972 mtd_set_ooblayout(mtd,
973 &fsmc_ecc1_ooblayout_ops);
977 "No oob scheme defined for oobsize %d\n",
986 static const struct nand_controller_ops fsmc_nand_controller_ops = {
987 .attach_chip = fsmc_nand_attach_chip,
988 .exec_op = fsmc_exec_op,
989 .setup_interface = fsmc_setup_interface,
993 * fsmc_nand_disable() - Disables the NAND bank
994 * @host: The instance to disable
996 static void fsmc_nand_disable(struct fsmc_nand_data *host)
1000 val = readl(host->regs_va + FSMC_PC);
1001 val &= ~FSMC_ENABLE;
1002 writel(val, host->regs_va + FSMC_PC);
1006 * fsmc_nand_probe - Probe function
1007 * @pdev: platform device structure
1009 static int __init fsmc_nand_probe(struct platform_device *pdev)
1011 struct fsmc_nand_data *host;
1012 struct mtd_info *mtd;
1013 struct nand_chip *nand;
1014 struct resource *res;
1016 dma_cap_mask_t mask;
1021 /* Allocate memory for the device structure (and zero it) */
1022 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
1028 ret = fsmc_nand_probe_config_dt(pdev, host, nand);
1032 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
1033 host->data_va = devm_ioremap_resource(&pdev->dev, res);
1034 if (IS_ERR(host->data_va))
1035 return PTR_ERR(host->data_va);
1037 host->data_pa = (dma_addr_t)res->start;
1039 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
1040 host->addr_va = devm_ioremap_resource(&pdev->dev, res);
1041 if (IS_ERR(host->addr_va))
1042 return PTR_ERR(host->addr_va);
1044 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
1045 host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
1046 if (IS_ERR(host->cmd_va))
1047 return PTR_ERR(host->cmd_va);
1049 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
1050 base = devm_ioremap_resource(&pdev->dev, res);
1052 return PTR_ERR(base);
1054 host->regs_va = base + FSMC_NOR_REG_SIZE +
1055 (host->bank * FSMC_NAND_BANK_SZ);
1057 host->clk = devm_clk_get(&pdev->dev, NULL);
1058 if (IS_ERR(host->clk)) {
1059 dev_err(&pdev->dev, "failed to fetch block clock\n");
1060 return PTR_ERR(host->clk);
1063 ret = clk_prepare_enable(host->clk);
1068 * This device ID is actually a common AMBA ID as used on the
1069 * AMBA PrimeCell bus. However it is not a PrimeCell.
1071 for (pid = 0, i = 0; i < 4; i++)
1072 pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) &
1077 dev_info(&pdev->dev,
1078 "FSMC device partno %03x, manufacturer %02x, revision %02x, config %02x\n",
1079 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
1080 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
1082 host->dev = &pdev->dev;
1084 if (host->mode == USE_DMA_ACCESS)
1085 init_completion(&host->dma_access_complete);
1087 /* Link all private pointers */
1088 mtd = nand_to_mtd(&host->nand);
1089 nand_set_flash_node(nand, pdev->dev.of_node);
1091 mtd->dev.parent = &pdev->dev;
1093 nand->badblockbits = 7;
1095 if (host->mode == USE_DMA_ACCESS) {
1097 dma_cap_set(DMA_MEMCPY, mask);
1098 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
1099 if (!host->read_dma_chan) {
1100 dev_err(&pdev->dev, "Unable to get read dma channel\n");
1104 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
1105 if (!host->write_dma_chan) {
1106 dev_err(&pdev->dev, "Unable to get write dma channel\n");
1108 goto release_dma_read_chan;
1112 if (host->dev_timings) {
1113 fsmc_nand_setup(host, host->dev_timings);
1114 nand->options |= NAND_KEEP_TIMINGS;
1117 nand_controller_init(&host->base);
1118 host->base.ops = &fsmc_nand_controller_ops;
1119 nand->controller = &host->base;
1122 * Scan to find existence of the device
1124 ret = nand_scan(nand, 1);
1126 goto release_dma_write_chan;
1129 ret = mtd_device_register(mtd, NULL, 0);
1133 platform_set_drvdata(pdev, host);
1134 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1140 release_dma_write_chan:
1141 if (host->mode == USE_DMA_ACCESS)
1142 dma_release_channel(host->write_dma_chan);
1143 release_dma_read_chan:
1144 if (host->mode == USE_DMA_ACCESS)
1145 dma_release_channel(host->read_dma_chan);
1147 fsmc_nand_disable(host);
1148 clk_disable_unprepare(host->clk);
1156 static int fsmc_nand_remove(struct platform_device *pdev)
1158 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1161 struct nand_chip *chip = &host->nand;
1164 ret = mtd_device_unregister(nand_to_mtd(chip));
1167 fsmc_nand_disable(host);
1169 if (host->mode == USE_DMA_ACCESS) {
1170 dma_release_channel(host->write_dma_chan);
1171 dma_release_channel(host->read_dma_chan);
1173 clk_disable_unprepare(host->clk);
1179 #ifdef CONFIG_PM_SLEEP
1180 static int fsmc_nand_suspend(struct device *dev)
1182 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1185 clk_disable_unprepare(host->clk);
1190 static int fsmc_nand_resume(struct device *dev)
1192 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1195 clk_prepare_enable(host->clk);
1196 if (host->dev_timings)
1197 fsmc_nand_setup(host, host->dev_timings);
1198 nand_reset(&host->nand, 0);
1205 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1207 static const struct of_device_id fsmc_nand_id_table[] = {
1208 { .compatible = "st,spear600-fsmc-nand" },
1209 { .compatible = "stericsson,fsmc-nand" },
1212 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1214 static struct platform_driver fsmc_nand_driver = {
1215 .remove = fsmc_nand_remove,
1217 .name = "fsmc-nand",
1218 .of_match_table = fsmc_nand_id_table,
1219 .pm = &fsmc_nand_pm_ops,
1223 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1225 MODULE_LICENSE("GPL v2");
1226 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1227 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");