drivers/mtd/nand/raw/fsmc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ST Microelectronics
   4  * Flexible Static Memory Controller (FSMC)
   5  * Driver for NAND portions
   6  *
   7  * Copyright © 2010 ST Microelectronics
   8  * Vipin Kumar <vipin.kumar@st.com>
   9  * Ashish Priyadarshi
  10  *
  11  * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
  12  *  Copyright © 2007 STMicroelectronics Pvt. Ltd.
  13  *  Copyright © 2009 Alessandro Rubini
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/completion.h>
  18 #include <linux/delay.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/dma-direction.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/module.h>
  25 #include <linux/resource.h>
  26 #include <linux/sched.h>
  27 #include <linux/types.h>
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/rawnand.h>
  30 #include <linux/mtd/nand_ecc.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/of.h>
  33 #include <linux/mtd/partitions.h>
  34 #include <linux/io.h>
  35 #include <linux/slab.h>
  36 #include <linux/amba/bus.h>
  37 #include <mtd/mtd-abi.h>
  38
  39 /* fsmc controller registers for NOR flash */
  40 #define CTRL                    0x0
  41         /* ctrl register definitions */
  42         #define BANK_ENABLE             BIT(0)
  43         #define MUXED                   BIT(1)
  44         #define NOR_DEV                 (2 << 2)
  45         #define WIDTH_16                BIT(4)
  46         #define RSTPWRDWN               BIT(6)
  47         #define WPROT                   BIT(7)
  48         #define WRT_ENABLE              BIT(12)
  49         #define WAIT_ENB                BIT(13)
  50
  51 #define CTRL_TIM                0x4
  52         /* ctrl_tim register definitions */
  53
  54 #define FSMC_NOR_BANK_SZ        0x8
  55 #define FSMC_NOR_REG_SIZE       0x40
  56
  57 #define FSMC_NOR_REG(base, bank, reg)   ((base) +                       \
  58                                          (FSMC_NOR_BANK_SZ * (bank)) +  \
  59                                          (reg))
  60
  61 /* fsmc controller registers for NAND flash */
  62 #define FSMC_PC                 0x00
  63         /* pc register definitions */
  64         #define FSMC_RESET              BIT(0)
  65         #define FSMC_WAITON             BIT(1)
  66         #define FSMC_ENABLE             BIT(2)
  67         #define FSMC_DEVTYPE_NAND       BIT(3)
  68         #define FSMC_DEVWID_16          BIT(4)
  69         #define FSMC_ECCEN              BIT(6)
  70         #define FSMC_ECCPLEN_256        BIT(7)
  71         #define FSMC_TCLR_SHIFT         (9)
  72         #define FSMC_TCLR_MASK          (0xF)
  73         #define FSMC_TAR_SHIFT          (13)
  74         #define FSMC_TAR_MASK           (0xF)
  75 #define STS                     0x04
  76         /* sts register definitions */
  77         #define FSMC_CODE_RDY           BIT(15)
  78 #define COMM                    0x08
  79         /* comm register definitions */
  80         #define FSMC_TSET_SHIFT         0
  81         #define FSMC_TSET_MASK          0xFF
  82         #define FSMC_TWAIT_SHIFT        8
  83         #define FSMC_TWAIT_MASK         0xFF
  84         #define FSMC_THOLD_SHIFT        16
  85         #define FSMC_THOLD_MASK         0xFF
  86         #define FSMC_THIZ_SHIFT         24
  87         #define FSMC_THIZ_MASK          0xFF
  88 #define ATTRIB                  0x0C
  89 #define IOATA                   0x10
  90 #define ECC1                    0x14
  91 #define ECC2                    0x18
  92 #define ECC3                    0x1C
  93 #define FSMC_NAND_BANK_SZ       0x20
  94
  95 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
  96
  97 /*
  98  * According to SPEAr300 Reference Manual (RM0082)
  99  *  TOUDEL = 7ns (Output delay from the flip-flops to the board)
 100  *  TINDEL = 5ns (Input delay from the board to the flipflop)
 101  */
 102 #define TOUTDEL 7000
 103 #define TINDEL  5000
 104
 105 struct fsmc_nand_timings {
 106         u8 tclr;
 107         u8 tar;
 108         u8 thiz;
 109         u8 thold;
 110         u8 twait;
 111         u8 tset;
 112 };
 113
 114 enum access_mode {
 115         USE_DMA_ACCESS = 1,
 116         USE_WORD_ACCESS,
 117 };
 118
 119 /**
 120  * struct fsmc_nand_data - structure for FSMC NAND device state
 121  *
 122  * @base:               Inherit from the nand_controller struct
 123  * @pid:                Part ID on the AMBA PrimeCell format
 124  * @nand:               Chip related info for a NAND flash.
 125  *
 126  * @bank:               Bank number for probed device.
 127  * @dev:                Parent device
 128  * @mode:               Access mode
 129  * @clk:                Clock structure for FSMC.
 130  *
 131  * @read_dma_chan:      DMA channel for read access
 132  * @write_dma_chan:     DMA channel for write access to NAND
 133  * @dma_access_complete: Completion structure
 134  *
 135  * @dev_timings:        NAND timings
 136  *
 137  * @data_pa:            NAND Physical port for Data.
 138  * @data_va:            NAND port for Data.
 139  * @cmd_va:             NAND port for Command.
 140  * @addr_va:            NAND port for Address.
 141  * @regs_va:            Registers base address for a given bank.
 142  */
 143 struct fsmc_nand_data {
 144         struct nand_controller  base;
 145         u32                     pid;
 146         struct nand_chip        nand;
 147
 148         unsigned int            bank;
 149         struct device           *dev;
 150         enum access_mode        mode;
 151         struct clk              *clk;
 152
 153         /* DMA related objects */
 154         struct dma_chan         *read_dma_chan;
 155         struct dma_chan         *write_dma_chan;
 156         struct completion       dma_access_complete;
 157
 158         struct fsmc_nand_timings *dev_timings;
 159
 160         dma_addr_t              data_pa;
 161         void __iomem            *data_va;
 162         void __iomem            *cmd_va;
 163         void __iomem            *addr_va;
 164         void __iomem            *regs_va;
 165 };
 166
 167 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
 168                                    struct mtd_oob_region *oobregion)
 169 {
 170         struct nand_chip *chip = mtd_to_nand(mtd);
 171
 172         if (section >= chip->ecc.steps)
 173                 return -ERANGE;
 174
 175         oobregion->offset = (section * 16) + 2;
 176         oobregion->length = 3;
 177
 178         return 0;
 179 }
 180
 181 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
 182                                     struct mtd_oob_region *oobregion)
 183 {
 184         struct nand_chip *chip = mtd_to_nand(mtd);
 185
 186         if (section >= chip->ecc.steps)
 187                 return -ERANGE;
 188
 189         oobregion->offset = (section * 16) + 8;
 190
 191         if (section < chip->ecc.steps - 1)
 192                 oobregion->length = 8;
 193         else
 194                 oobregion->length = mtd->oobsize - oobregion->offset;
 195
 196         return 0;
 197 }
 198
 199 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
 200         .ecc = fsmc_ecc1_ooblayout_ecc,
 201         .free = fsmc_ecc1_ooblayout_free,
 202 };
 203
 204 /*
 205  * ECC placement definitions in oobfree type format.
 206  * There are 13 bytes of ecc for every 512 byte block and it has to be read
 207  * consecutively and immediately after the 512 byte data block for hardware to
 208  * generate the error bit offsets in 512 byte data.
 209  */
 210 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
 211                                    struct mtd_oob_region *oobregion)
 212 {
 213         struct nand_chip *chip = mtd_to_nand(mtd);
 214
 215         if (section >= chip->ecc.steps)
 216                 return -ERANGE;
 217
 218         oobregion->length = chip->ecc.bytes;
 219
 220         if (!section && mtd->writesize <= 512)
 221                 oobregion->offset = 0;
 222         else
 223                 oobregion->offset = (section * 16) + 2;
 224
 225         return 0;
 226 }
 227
 228 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
 229                                     struct mtd_oob_region *oobregion)
 230 {
 231         struct nand_chip *chip = mtd_to_nand(mtd);
 232
 233         if (section >= chip->ecc.steps)
 234                 return -ERANGE;
 235
 236         oobregion->offset = (section * 16) + 15;
 237
 238         if (section < chip->ecc.steps - 1)
 239                 oobregion->length = 3;
 240         else
 241                 oobregion->length = mtd->oobsize - oobregion->offset;
 242
 243         return 0;
 244 }
 245
 246 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
 247         .ecc = fsmc_ecc4_ooblayout_ecc,
 248         .free = fsmc_ecc4_ooblayout_free,
 249 };
 250
 251 static inline struct fsmc_nand_data *nand_to_fsmc(struct nand_chip *chip)
 252 {
 253         return container_of(chip, struct fsmc_nand_data, nand);
 254 }
 255
 256 /*
 257  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
 258  *
 259  * This routine initializes timing parameters related to NAND memory access in
 260  * FSMC registers
 261  */
 262 static void fsmc_nand_setup(struct fsmc_nand_data *host,
 263                             struct fsmc_nand_timings *tims)
 264 {
 265         u32 value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
 266         u32 tclr, tar, thiz, thold, twait, tset;
 267
 268         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
 269         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
 270         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
 271         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
 272         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
 273         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 274
 275         if (host->nand.options & NAND_BUSWIDTH_16)
 276                 value |= FSMC_DEVWID_16;
 277
 278         writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC);
 279         writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM);
 280         writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB);
 281 }
 282
 283 static int fsmc_calc_timings(struct fsmc_nand_data *host,
 284                              const struct nand_sdr_timings *sdrt,
 285                              struct fsmc_nand_timings *tims)
 286 {
 287         unsigned long hclk = clk_get_rate(host->clk);
 288         unsigned long hclkn = NSEC_PER_SEC / hclk;
 289         u32 thiz, thold, twait, tset, twait_min;
 290
 291         if (sdrt->tRC_min < 30000)
 292                 return -EOPNOTSUPP;
 293
 294         tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1;
 295         if (tims->tar > FSMC_TAR_MASK)
 296                 tims->tar = FSMC_TAR_MASK;
 297         tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1;
 298         if (tims->tclr > FSMC_TCLR_MASK)
 299                 tims->tclr = FSMC_TCLR_MASK;
 300
 301         thiz = sdrt->tCS_min - sdrt->tWP_min;
 302         tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn);
 303
 304         thold = sdrt->tDH_min;
 305         if (thold < sdrt->tCH_min)
 306                 thold = sdrt->tCH_min;
 307         if (thold < sdrt->tCLH_min)
 308                 thold = sdrt->tCLH_min;
 309         if (thold < sdrt->tWH_min)
 310                 thold = sdrt->tWH_min;
 311         if (thold < sdrt->tALH_min)
 312                 thold = sdrt->tALH_min;
 313         if (thold < sdrt->tREH_min)
 314                 thold = sdrt->tREH_min;
 315         tims->thold = DIV_ROUND_UP(thold / 1000, hclkn);
 316         if (tims->thold == 0)
 317                 tims->thold = 1;
 318         else if (tims->thold > FSMC_THOLD_MASK)
 319                 tims->thold = FSMC_THOLD_MASK;
 320
 321         tset = max(sdrt->tCS_min - sdrt->tWP_min,
 322                    sdrt->tCEA_max - sdrt->tREA_max);
 323         tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
 324         if (tims->tset == 0)
 325                 tims->tset = 1;
 326         else if (tims->tset > FSMC_TSET_MASK)
 327                 tims->tset = FSMC_TSET_MASK;
 328
 329         /*
 330          * According to SPEAr300 Reference Manual (RM0082) which gives more
 331          * information related to FSMSC timings than the SPEAr600 one (RM0305),
 332          *   twait >= tCEA - (tset * TCLK) + TOUTDEL + TINDEL
 333          */
 334         twait_min = sdrt->tCEA_max - ((tims->tset + 1) * hclkn * 1000)
 335                     + TOUTDEL + TINDEL;
 336         twait = max3(sdrt->tRP_min, sdrt->tWP_min, twait_min);
 337
 338         tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
 339         if (tims->twait == 0)
 340                 tims->twait = 1;
 341         else if (tims->twait > FSMC_TWAIT_MASK)
 342                 tims->twait = FSMC_TWAIT_MASK;
 343
 344         return 0;
 345 }
 346
 347 static int fsmc_setup_interface(struct nand_chip *nand, int csline,
 348                                 const struct nand_interface_config *conf)
 349 {
 350         struct fsmc_nand_data *host = nand_to_fsmc(nand);
 351         struct fsmc_nand_timings tims;
 352         const struct nand_sdr_timings *sdrt;
 353         int ret;
 354
 355         sdrt = nand_get_sdr_timings(conf);
 356         if (IS_ERR(sdrt))
 357                 return PTR_ERR(sdrt);
 358
 359         ret = fsmc_calc_timings(host, sdrt, &tims);
 360         if (ret)
 361                 return ret;
 362
 363         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
 364                 return 0;
 365
 366         fsmc_nand_setup(host, &tims);
 367
 368         return 0;
 369 }
 370
 371 /*
 372  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
 373  */
 374 static void fsmc_enable_hwecc(struct nand_chip *chip, int mode)
 375 {
 376         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 377
 378         writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256,
 379                        host->regs_va + FSMC_PC);
 380         writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN,
 381                        host->regs_va + FSMC_PC);
 382         writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN,
 383                        host->regs_va + FSMC_PC);
 384 }
 385
 386 /*
 387  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
 388  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
 389  * max of 8-bits)
 390  */
 391 static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const u8 *data,
 392                                 u8 *ecc)
 393 {
 394         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 395         u32 ecc_tmp;
 396         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 397
 398         do {
 399                 if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY)
 400                         break;
 401
 402                 cond_resched();
 403         } while (!time_after_eq(jiffies, deadline));
 404
 405         if (time_after_eq(jiffies, deadline)) {
 406                 dev_err(host->dev, "calculate ecc timed out\n");
 407                 return -ETIMEDOUT;
 408         }
 409
 410         ecc_tmp = readl_relaxed(host->regs_va + ECC1);
 411         ecc[0] = ecc_tmp;
 412         ecc[1] = ecc_tmp >> 8;
 413         ecc[2] = ecc_tmp >> 16;
 414         ecc[3] = ecc_tmp >> 24;
 415
 416         ecc_tmp = readl_relaxed(host->regs_va + ECC2);
 417         ecc[4] = ecc_tmp;
 418         ecc[5] = ecc_tmp >> 8;
 419         ecc[6] = ecc_tmp >> 16;
 420         ecc[7] = ecc_tmp >> 24;
 421
 422         ecc_tmp = readl_relaxed(host->regs_va + ECC3);
 423         ecc[8] = ecc_tmp;
 424         ecc[9] = ecc_tmp >> 8;
 425         ecc[10] = ecc_tmp >> 16;
 426         ecc[11] = ecc_tmp >> 24;
 427
 428         ecc_tmp = readl_relaxed(host->regs_va + STS);
 429         ecc[12] = ecc_tmp >> 16;
 430
 431         return 0;
 432 }
 433
 434 /*
 435  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
 436  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
 437  * max of 1-bit)
 438  */
 439 static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data,
 440                                 u8 *ecc)
 441 {
 442         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 443         u32 ecc_tmp;
 444
 445         ecc_tmp = readl_relaxed(host->regs_va + ECC1);
 446         ecc[0] = ecc_tmp;
 447         ecc[1] = ecc_tmp >> 8;
 448         ecc[2] = ecc_tmp >> 16;
 449
 450         return 0;
 451 }
 452
 453 /* Count the number of 0's in buff upto a max of max_bits */
 454 static int count_written_bits(u8 *buff, int size, int max_bits)
 455 {
 456         int k, written_bits = 0;
 457
 458         for (k = 0; k < size; k++) {
 459                 written_bits += hweight8(~buff[k]);
 460                 if (written_bits > max_bits)
 461                         break;
 462         }
 463
 464         return written_bits;
 465 }
 466
 467 static void dma_complete(void *param)
 468 {
 469         struct fsmc_nand_data *host = param;
 470
 471         complete(&host->dma_access_complete);
 472 }
 473
 474 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
 475                     enum dma_data_direction direction)
 476 {
 477         struct dma_chan *chan;
 478         struct dma_device *dma_dev;
 479         struct dma_async_tx_descriptor *tx;
 480         dma_addr_t dma_dst, dma_src, dma_addr;
 481         dma_cookie_t cookie;
 482         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 483         int ret;
 484         unsigned long time_left;
 485
 486         if (direction == DMA_TO_DEVICE)
 487                 chan = host->write_dma_chan;
 488         else if (direction == DMA_FROM_DEVICE)
 489                 chan = host->read_dma_chan;
 490         else
 491                 return -EINVAL;
 492
 493         dma_dev = chan->device;
 494         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
 495
 496         if (direction == DMA_TO_DEVICE) {
 497                 dma_src = dma_addr;
 498                 dma_dst = host->data_pa;
 499         } else {
 500                 dma_src = host->data_pa;
 501                 dma_dst = dma_addr;
 502         }
 503
 504         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
 505                         len, flags);
 506         if (!tx) {
 507                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
 508                 ret = -EIO;
 509                 goto unmap_dma;
 510         }
 511
 512         tx->callback = dma_complete;
 513         tx->callback_param = host;
 514         cookie = tx->tx_submit(tx);
 515
 516         ret = dma_submit_error(cookie);
 517         if (ret) {
 518                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
 519                 goto unmap_dma;
 520         }
 521
 522         dma_async_issue_pending(chan);
 523
 524         time_left =
 525         wait_for_completion_timeout(&host->dma_access_complete,
 526                                     msecs_to_jiffies(3000));
 527         if (time_left == 0) {
 528                 dmaengine_terminate_all(chan);
 529                 dev_err(host->dev, "wait_for_completion_timeout\n");
 530                 ret = -ETIMEDOUT;
 531                 goto unmap_dma;
 532         }
 533
 534         ret = 0;
 535
 536 unmap_dma:
 537         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
 538
 539         return ret;
 540 }
 541
 542 /*
 543  * fsmc_write_buf - write buffer to chip
 544  * @host:       FSMC NAND controller
 545  * @buf:        data buffer
 546  * @len:        number of bytes to write
 547  */
 548 static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf,
 549                            int len)
 550 {
 551         int i;
 552
 553         if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
 554             IS_ALIGNED(len, sizeof(u32))) {
 555                 u32 *p = (u32 *)buf;
 556
 557                 len = len >> 2;
 558                 for (i = 0; i < len; i++)
 559                         writel_relaxed(p[i], host->data_va);
 560         } else {
 561                 for (i = 0; i < len; i++)
 562                         writeb_relaxed(buf[i], host->data_va);
 563         }
 564 }
 565
 566 /*
 567  * fsmc_read_buf - read chip data into buffer
 568  * @host:       FSMC NAND controller
 569  * @buf:        buffer to store date
 570  * @len:        number of bytes to read
 571  */
 572 static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len)
 573 {
 574         int i;
 575
 576         if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
 577             IS_ALIGNED(len, sizeof(u32))) {
 578                 u32 *p = (u32 *)buf;
 579
 580                 len = len >> 2;
 581                 for (i = 0; i < len; i++)
 582                         p[i] = readl_relaxed(host->data_va);
 583         } else {
 584                 for (i = 0; i < len; i++)
 585                         buf[i] = readb_relaxed(host->data_va);
 586         }
 587 }
 588
 589 /*
 590  * fsmc_read_buf_dma - read chip data into buffer
 591  * @host:       FSMC NAND controller
 592  * @buf:        buffer to store date
 593  * @len:        number of bytes to read
 594  */
 595 static void fsmc_read_buf_dma(struct fsmc_nand_data *host, u8 *buf,
 596                               int len)
 597 {
 598         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
 599 }
 600
 601 /*
 602  * fsmc_write_buf_dma - write buffer to chip
 603  * @host:       FSMC NAND controller
 604  * @buf:        data buffer
 605  * @len:        number of bytes to write
 606  */
 607 static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf,
 608                                int len)
 609 {
 610         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
 611 }
 612
 613 /*
 614  * fsmc_exec_op - hook called by the core to execute NAND operations
 615  *
 616  * This controller is simple enough and thus does not need to use the parser
 617  * provided by the core, instead, handle every situation here.
 618  */
 619 static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
 620                         bool check_only)
 621 {
 622         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 623         const struct nand_op_instr *instr = NULL;
 624         int ret = 0;
 625         unsigned int op_id;
 626         int i;
 627
 628         if (check_only)
 629                 return 0;
 630
 631         pr_debug("Executing operation [%d instructions]:\n", op->ninstrs);
 632
 633         for (op_id = 0; op_id < op->ninstrs; op_id++) {
 634                 instr = &op->instrs[op_id];
 635
 636                 nand_op_trace("  ", instr);
 637
 638                 switch (instr->type) {
 639                 case NAND_OP_CMD_INSTR:
 640                         writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va);
 641                         break;
 642
 643                 case NAND_OP_ADDR_INSTR:
 644                         for (i = 0; i < instr->ctx.addr.naddrs; i++)
 645                                 writeb_relaxed(instr->ctx.addr.addrs[i],
 646                                                host->addr_va);
 647                         break;
 648
 649                 case NAND_OP_DATA_IN_INSTR:
 650                         if (host->mode == USE_DMA_ACCESS)
 651                                 fsmc_read_buf_dma(host, instr->ctx.data.buf.in,
 652                                                   instr->ctx.data.len);
 653                         else
 654                                 fsmc_read_buf(host, instr->ctx.data.buf.in,
 655                                               instr->ctx.data.len);
 656                         break;
 657
 658                 case NAND_OP_DATA_OUT_INSTR:
 659                         if (host->mode == USE_DMA_ACCESS)
 660                                 fsmc_write_buf_dma(host,
 661                                                    instr->ctx.data.buf.out,
 662                                                    instr->ctx.data.len);
 663                         else
 664                                 fsmc_write_buf(host, instr->ctx.data.buf.out,
 665                                                instr->ctx.data.len);
 666                         break;
 667
 668                 case NAND_OP_WAITRDY_INSTR:
 669                         ret = nand_soft_waitrdy(chip,
 670                                                 instr->ctx.waitrdy.timeout_ms);
 671                         break;
 672                 }
 673
 674                 if (instr->delay_ns)
 675                         ndelay(instr->delay_ns);
 676         }
 677
 678         return ret;
 679 }
 680
 681 /*
 682  * fsmc_read_page_hwecc
 683  * @chip:       nand chip info structure
 684  * @buf:        buffer to store read data
 685  * @oob_required:       caller expects OOB data read to chip->oob_poi
 686  * @page:       page number to read
 687  *
 688  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
 689  * performed in a strict sequence as follows:
 690  * data(512 byte) -> ecc(13 byte)
 691  * After this read, fsmc hardware generates and reports error data bits(up to a
 692  * max of 8 bits)
 693  */
 694 static int fsmc_read_page_hwecc(struct nand_chip *chip, u8 *buf,
 695                                 int oob_required, int page)
 696 {
 697         struct mtd_info *mtd = nand_to_mtd(chip);
 698         int i, j, s, stat, eccsize = chip->ecc.size;
 699         int eccbytes = chip->ecc.bytes;
 700         int eccsteps = chip->ecc.steps;
 701         u8 *p = buf;
 702         u8 *ecc_calc = chip->ecc.calc_buf;
 703         u8 *ecc_code = chip->ecc.code_buf;
 704         int off, len, ret, group = 0;
 705         /*
 706          * ecc_oob is intentionally taken as u16. In 16bit devices, we
 707          * end up reading 14 bytes (7 words) from oob. The local array is
 708          * to maintain word alignment
 709          */
 710         u16 ecc_oob[7];
 711         u8 *oob = (u8 *)&ecc_oob[0];
 712         unsigned int max_bitflips = 0;
 713
 714         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
 715                 nand_read_page_op(chip, page, s * eccsize, NULL, 0);
 716                 chip->ecc.hwctl(chip, NAND_ECC_READ);
 717                 ret = nand_read_data_op(chip, p, eccsize, false, false);
 718                 if (ret)
 719                         return ret;
 720
 721                 for (j = 0; j < eccbytes;) {
 722                         struct mtd_oob_region oobregion;
 723
 724                         ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
 725                         if (ret)
 726                                 return ret;
 727
 728                         off = oobregion.offset;
 729                         len = oobregion.length;
 730
 731                         /*
 732                          * length is intentionally kept a higher multiple of 2
 733                          * to read at least 13 bytes even in case of 16 bit NAND
 734                          * devices
 735                          */
 736                         if (chip->options & NAND_BUSWIDTH_16)
 737                                 len = roundup(len, 2);
 738
 739                         nand_read_oob_op(chip, page, off, oob + j, len);
 740                         j += len;
 741                 }
 742
 743                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 744                 chip->ecc.calculate(chip, p, &ecc_calc[i]);
 745
 746                 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
 747                 if (stat < 0) {
 748                         mtd->ecc_stats.failed++;
 749                 } else {
 750                         mtd->ecc_stats.corrected += stat;
 751                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 752                 }
 753         }
 754
 755         return max_bitflips;
 756 }
 757
 758 /*
 759  * fsmc_bch8_correct_data
 760  * @mtd:        mtd info structure
 761  * @dat:        buffer of read data
 762  * @read_ecc:   ecc read from device spare area
 763  * @calc_ecc:   ecc calculated from read data
 764  *
 765  * calc_ecc is a 104 bit information containing maximum of 8 error
 766  * offset information of 13 bits each in 512 bytes of read data.
 767  */
 768 static int fsmc_bch8_correct_data(struct nand_chip *chip, u8 *dat,
 769                                   u8 *read_ecc, u8 *calc_ecc)
 770 {
 771         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 772         u32 err_idx[8];
 773         u32 num_err, i;
 774         u32 ecc1, ecc2, ecc3, ecc4;
 775
 776         num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF;
 777
 778         /* no bit flipping */
 779         if (likely(num_err == 0))
 780                 return 0;
 781
 782         /* too many errors */
 783         if (unlikely(num_err > 8)) {
 784                 /*
 785                  * This is a temporary erase check. A newly erased page read
 786                  * would result in an ecc error because the oob data is also
 787                  * erased to FF and the calculated ecc for an FF data is not
 788                  * FF..FF.
 789                  * This is a workaround to skip performing correction in case
 790                  * data is FF..FF
 791                  *
 792                  * Logic:
 793                  * For every page, each bit written as 0 is counted until these
 794                  * number of bits are greater than 8 (the maximum correction
 795                  * capability of FSMC for each 512 + 13 bytes)
 796                  */
 797
 798                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
 799                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
 800
 801                 if ((bits_ecc + bits_data) <= 8) {
 802                         if (bits_data)
 803                                 memset(dat, 0xff, chip->ecc.size);
 804                         return bits_data;
 805                 }
 806
 807                 return -EBADMSG;
 808         }
 809
 810         /*
 811          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 812          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
 813          *
 814          * calc_ecc is a 104 bit information containing maximum of 8 error
 815          * offset information of 13 bits each. calc_ecc is copied into a
 816          * u64 array and error offset indexes are populated in err_idx
 817          * array
 818          */
 819         ecc1 = readl_relaxed(host->regs_va + ECC1);
 820         ecc2 = readl_relaxed(host->regs_va + ECC2);
 821         ecc3 = readl_relaxed(host->regs_va + ECC3);
 822         ecc4 = readl_relaxed(host->regs_va + STS);
 823
 824         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
 825         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
 826         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
 827         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
 828         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
 829         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
 830         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
 831         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 832
 833         i = 0;
 834         while (num_err--) {
 835                 err_idx[i] ^= 3;
 836
 837                 if (err_idx[i] < chip->ecc.size * 8) {
 838                         int err = err_idx[i];
 839
 840                         dat[err >> 3] ^= BIT(err & 7);
 841                         i++;
 842                 }
 843         }
 844         return i;
 845 }
 846
 847 static bool filter(struct dma_chan *chan, void *slave)
 848 {
 849         chan->private = slave;
 850         return true;
 851 }
 852
 853 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
 854                                      struct fsmc_nand_data *host,
 855                                      struct nand_chip *nand)
 856 {
 857         struct device_node *np = pdev->dev.of_node;
 858         u32 val;
 859         int ret;
 860
 861         nand->options = 0;
 862
 863         if (!of_property_read_u32(np, "bank-width", &val)) {
 864                 if (val == 2) {
 865                         nand->options |= NAND_BUSWIDTH_16;
 866                 } else if (val != 1) {
 867                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
 868                         return -EINVAL;
 869                 }
 870         }
 871
 872         if (of_get_property(np, "nand-skip-bbtscan", NULL))
 873                 nand->options |= NAND_SKIP_BBTSCAN;
 874
 875         host->dev_timings = devm_kzalloc(&pdev->dev,
 876                                          sizeof(*host->dev_timings),
 877                                          GFP_KERNEL);
 878         if (!host->dev_timings)
 879                 return -ENOMEM;
 880
 881         ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
 882                                         sizeof(*host->dev_timings));
 883         if (ret)
 884                 host->dev_timings = NULL;
 885
 886         /* Set default NAND bank to 0 */
 887         host->bank = 0;
 888         if (!of_property_read_u32(np, "bank", &val)) {
 889                 if (val > 3) {
 890                         dev_err(&pdev->dev, "invalid bank %u\n", val);
 891                         return -EINVAL;
 892                 }
 893                 host->bank = val;
 894         }
 895         return 0;
 896 }
 897
 898 static int fsmc_nand_attach_chip(struct nand_chip *nand)
 899 {
 900         struct mtd_info *mtd = nand_to_mtd(nand);
 901         struct fsmc_nand_data *host = nand_to_fsmc(nand);
 902
 903         if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
 904                 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
 905
 906         if (!nand->ecc.size)
 907                 nand->ecc.size = 512;
 908
 909         if (AMBA_REV_BITS(host->pid) >= 8) {
 910                 nand->ecc.read_page = fsmc_read_page_hwecc;
 911                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
 912                 nand->ecc.correct = fsmc_bch8_correct_data;
 913                 nand->ecc.bytes = 13;
 914                 nand->ecc.strength = 8;
 915         }
 916
 917         if (AMBA_REV_BITS(host->pid) >= 8) {
 918                 switch (mtd->oobsize) {
 919                 case 16:
 920                 case 64:
 921                 case 128:
 922                 case 224:
 923                 case 256:
 924                         break;
 925                 default:
 926                         dev_warn(host->dev,
 927                                  "No oob scheme defined for oobsize %d\n",
 928                                  mtd->oobsize);
 929                         return -EINVAL;
 930                 }
 931
 932                 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
 933
 934                 return 0;
 935         }
 936
 937         switch (nand->ecc.engine_type) {
 938         case NAND_ECC_ENGINE_TYPE_ON_HOST:
 939                 dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
 940                 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
 941                 nand->ecc.correct = nand_correct_data;
 942                 nand->ecc.hwctl = fsmc_enable_hwecc;
 943                 nand->ecc.bytes = 3;
 944                 nand->ecc.strength = 1;
 945                 nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
 946                 break;
 947
 948         case NAND_ECC_ENGINE_TYPE_SOFT:
 949                 if (nand->ecc.algo == NAND_ECC_ALGO_BCH) {
 950                         dev_info(host->dev,
 951                                  "Using 4-bit SW BCH ECC scheme\n");
 952                         break;
 953                 }
 954
 955         case NAND_ECC_ENGINE_TYPE_ON_DIE:
 956                 break;
 957
 958         default:
 959                 dev_err(host->dev, "Unsupported ECC mode!\n");
 960                 return -ENOTSUPP;
 961         }
 962
 963         /*
 964          * Don't set layout for BCH4 SW ECC. This will be
 965          * generated later in nand_bch_init() later.
 966          */
 967         if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
 968                 switch (mtd->oobsize) {
 969                 case 16:
 970                 case 64:
 971                 case 128:
 972                         mtd_set_ooblayout(mtd,
 973                                           &fsmc_ecc1_ooblayout_ops);
 974                         break;
 975                 default:
 976                         dev_warn(host->dev,
 977                                  "No oob scheme defined for oobsize %d\n",
 978                                  mtd->oobsize);
 979                         return -EINVAL;
 980                 }
 981         }
 982
 983         return 0;
 984 }
 985
 986 static const struct nand_controller_ops fsmc_nand_controller_ops = {
 987         .attach_chip = fsmc_nand_attach_chip,
 988         .exec_op = fsmc_exec_op,
 989         .setup_interface = fsmc_setup_interface,
 990 };
 991
 992 /**
 993  * fsmc_nand_disable() - Disables the NAND bank
 994  * @host: The instance to disable
 995  */
 996 static void fsmc_nand_disable(struct fsmc_nand_data *host)
 997 {
 998         u32 val;
 999
1000         val = readl(host->regs_va + FSMC_PC);
1001         val &= ~FSMC_ENABLE;
1002         writel(val, host->regs_va + FSMC_PC);
1003 }
1004
1005 /*
1006  * fsmc_nand_probe - Probe function
1007  * @pdev:       platform device structure
1008  */
1009 static int __init fsmc_nand_probe(struct platform_device *pdev)
1010 {
1011         struct fsmc_nand_data *host;
1012         struct mtd_info *mtd;
1013         struct nand_chip *nand;
1014         struct resource *res;
1015         void __iomem *base;
1016         dma_cap_mask_t mask;
1017         int ret = 0;
1018         u32 pid;
1019         int i;
1020
1021         /* Allocate memory for the device structure (and zero it) */
1022         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
1023         if (!host)
1024                 return -ENOMEM;
1025
1026         nand = &host->nand;
1027
1028         ret = fsmc_nand_probe_config_dt(pdev, host, nand);
1029         if (ret)
1030                 return ret;
1031
1032         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
1033         host->data_va = devm_ioremap_resource(&pdev->dev, res);
1034         if (IS_ERR(host->data_va))
1035                 return PTR_ERR(host->data_va);
1036
1037         host->data_pa = (dma_addr_t)res->start;
1038
1039         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
1040         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
1041         if (IS_ERR(host->addr_va))
1042                 return PTR_ERR(host->addr_va);
1043
1044         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
1045         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
1046         if (IS_ERR(host->cmd_va))
1047                 return PTR_ERR(host->cmd_va);
1048
1049         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
1050         base = devm_ioremap_resource(&pdev->dev, res);
1051         if (IS_ERR(base))
1052                 return PTR_ERR(base);
1053
1054         host->regs_va = base + FSMC_NOR_REG_SIZE +
1055                 (host->bank * FSMC_NAND_BANK_SZ);
1056
1057         host->clk = devm_clk_get(&pdev->dev, NULL);
1058         if (IS_ERR(host->clk)) {
1059                 dev_err(&pdev->dev, "failed to fetch block clock\n");
1060                 return PTR_ERR(host->clk);
1061         }
1062
1063         ret = clk_prepare_enable(host->clk);
1064         if (ret)
1065                 return ret;
1066
1067         /*
1068          * This device ID is actually a common AMBA ID as used on the
1069          * AMBA PrimeCell bus. However it is not a PrimeCell.
1070          */
1071         for (pid = 0, i = 0; i < 4; i++)
1072                 pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) &
1073                         255) << (i * 8);
1074
1075         host->pid = pid;
1076
1077         dev_info(&pdev->dev,
1078                  "FSMC device partno %03x, manufacturer %02x, revision %02x, config %02x\n",
1079                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
1080                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
1081
1082         host->dev = &pdev->dev;
1083
1084         if (host->mode == USE_DMA_ACCESS)
1085                 init_completion(&host->dma_access_complete);
1086
1087         /* Link all private pointers */
1088         mtd = nand_to_mtd(&host->nand);
1089         nand_set_flash_node(nand, pdev->dev.of_node);
1090
1091         mtd->dev.parent = &pdev->dev;
1092
1093         nand->badblockbits = 7;
1094
1095         if (host->mode == USE_DMA_ACCESS) {
1096                 dma_cap_zero(mask);
1097                 dma_cap_set(DMA_MEMCPY, mask);
1098                 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
1099                 if (!host->read_dma_chan) {
1100                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
1101                         ret = -ENODEV;
1102                         goto disable_clk;
1103                 }
1104                 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
1105                 if (!host->write_dma_chan) {
1106                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
1107                         ret = -ENODEV;
1108                         goto release_dma_read_chan;
1109                 }
1110         }
1111
1112         if (host->dev_timings) {
1113                 fsmc_nand_setup(host, host->dev_timings);
1114                 nand->options |= NAND_KEEP_TIMINGS;
1115         }
1116
1117         nand_controller_init(&host->base);
1118         host->base.ops = &fsmc_nand_controller_ops;
1119         nand->controller = &host->base;
1120
1121         /*
1122          * Scan to find existence of the device
1123          */
1124         ret = nand_scan(nand, 1);
1125         if (ret)
1126                 goto release_dma_write_chan;
1127
1128         mtd->name = "nand";
1129         ret = mtd_device_register(mtd, NULL, 0);
1130         if (ret)
1131                 goto cleanup_nand;
1132
1133         platform_set_drvdata(pdev, host);
1134         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1135
1136         return 0;
1137
1138 cleanup_nand:
1139         nand_cleanup(nand);
1140 release_dma_write_chan:
1141         if (host->mode == USE_DMA_ACCESS)
1142                 dma_release_channel(host->write_dma_chan);
1143 release_dma_read_chan:
1144         if (host->mode == USE_DMA_ACCESS)
1145                 dma_release_channel(host->read_dma_chan);
1146 disable_clk:
1147         fsmc_nand_disable(host);
1148         clk_disable_unprepare(host->clk);
1149
1150         return ret;
1151 }
1152
1153 /*
1154  * Clean up routine
1155  */
1156 static int fsmc_nand_remove(struct platform_device *pdev)
1157 {
1158         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1159
1160         if (host) {
1161                 struct nand_chip *chip = &host->nand;
1162                 int ret;
1163
1164                 ret = mtd_device_unregister(nand_to_mtd(chip));
1165                 WARN_ON(ret);
1166                 nand_cleanup(chip);
1167                 fsmc_nand_disable(host);
1168
1169                 if (host->mode == USE_DMA_ACCESS) {
1170                         dma_release_channel(host->write_dma_chan);
1171                         dma_release_channel(host->read_dma_chan);
1172                 }
1173                 clk_disable_unprepare(host->clk);
1174         }
1175
1176         return 0;
1177 }
1178
1179 #ifdef CONFIG_PM_SLEEP
1180 static int fsmc_nand_suspend(struct device *dev)
1181 {
1182         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1183
1184         if (host)
1185                 clk_disable_unprepare(host->clk);
1186
1187         return 0;
1188 }
1189
1190 static int fsmc_nand_resume(struct device *dev)
1191 {
1192         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1193         int ret;
1194
1195         if (host) {
1196                 ret = clk_prepare_enable(host->clk);
1197                 if (ret) {
1198                         dev_err(dev, "failed to enable clk\n");
1199                         return ret;
1200                 }
1201                 if (host->dev_timings)
1202                         fsmc_nand_setup(host, host->dev_timings);
1203                 nand_reset(&host->nand, 0);
1204         }
1205
1206         return 0;
1207 }
1208 #endif
1209
1210 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1211
1212 static const struct of_device_id fsmc_nand_id_table[] = {
1213         { .compatible = "st,spear600-fsmc-nand" },
1214         { .compatible = "stericsson,fsmc-nand" },
1215         {}
1216 };
1217 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1218
1219 static struct platform_driver fsmc_nand_driver = {
1220         .remove = fsmc_nand_remove,
1221         .driver = {
1222                 .name = "fsmc-nand",
1223                 .of_match_table = fsmc_nand_id_table,
1224                 .pm = &fsmc_nand_pm_ops,
1225         },
1226 };
1227
1228 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1229
1230 MODULE_LICENSE("GPL v2");
1231 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1232 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");