1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale UPM NAND driver.
5 * Copyright © 2007-2008 MontaVista Software, Inc.
7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <linux/mtd/rawnand.h>
14 #include <linux/mtd/nand_ecc.h>
15 #include <linux/mtd/partitions.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/of_platform.h>
19 #include <linux/slab.h>
20 #include <asm/fsl_lbc.h>
23 struct nand_controller base;
25 struct nand_chip chip;
27 uint8_t upm_addr_offset;
28 uint8_t upm_cmd_offset;
29 void __iomem *io_base;
30 struct gpio_desc *rnb_gpio[NAND_MAX_CHIPS];
31 uint32_t mchip_offsets[NAND_MAX_CHIPS];
33 uint32_t mchip_number;
36 static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
38 return container_of(mtd_to_nand(mtdinfo), struct fsl_upm_nand,
42 static int fun_chip_init(struct fsl_upm_nand *fun,
43 const struct device_node *upm_np,
44 const struct resource *io_res)
46 struct mtd_info *mtd = nand_to_mtd(&fun->chip);
48 struct device_node *flash_np;
50 fun->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
51 fun->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
52 fun->chip.controller = &fun->base;
53 mtd->dev.parent = fun->dev;
55 flash_np = of_get_next_child(upm_np, NULL);
59 nand_set_flash_node(&fun->chip, flash_np);
60 mtd->name = devm_kasprintf(fun->dev, GFP_KERNEL, "0x%llx.%pOFn",
68 ret = nand_scan(&fun->chip, fun->mchip_count);
72 ret = mtd_device_register(mtd, NULL, 0);
74 of_node_put(flash_np);
78 static int func_exec_instr(struct nand_chip *chip,
79 const struct nand_op_instr *instr)
81 struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
82 u32 mar, reg_offs = fun->mchip_offsets[fun->mchip_number];
87 switch (instr->type) {
88 case NAND_OP_CMD_INSTR:
89 fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
90 mar = (instr->ctx.cmd.opcode << (32 - fun->upm.width)) |
92 fsl_upm_run_pattern(&fun->upm, fun->io_base + reg_offs, mar);
93 fsl_upm_end_pattern(&fun->upm);
96 case NAND_OP_ADDR_INSTR:
97 fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
98 for (i = 0; i < instr->ctx.addr.naddrs; i++) {
99 mar = (instr->ctx.addr.addrs[i] << (32 - fun->upm.width)) |
101 fsl_upm_run_pattern(&fun->upm, fun->io_base + reg_offs, mar);
103 fsl_upm_end_pattern(&fun->upm);
106 case NAND_OP_DATA_IN_INSTR:
107 in = instr->ctx.data.buf.in;
108 for (i = 0; i < instr->ctx.data.len; i++)
109 in[i] = in_8(fun->io_base + reg_offs);
112 case NAND_OP_DATA_OUT_INSTR:
113 out = instr->ctx.data.buf.out;
114 for (i = 0; i < instr->ctx.data.len; i++)
115 out_8(fun->io_base + reg_offs, out[i]);
118 case NAND_OP_WAITRDY_INSTR:
119 if (!fun->rnb_gpio[fun->mchip_number])
120 return nand_soft_waitrdy(chip, instr->ctx.waitrdy.timeout_ms);
122 return nand_gpio_waitrdy(chip, fun->rnb_gpio[fun->mchip_number],
123 instr->ctx.waitrdy.timeout_ms);
132 static int fun_exec_op(struct nand_chip *chip, const struct nand_operation *op,
135 struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
139 if (op->cs > NAND_MAX_CHIPS)
145 fun->mchip_number = op->cs;
147 for (i = 0; i < op->ninstrs; i++) {
148 ret = func_exec_instr(chip, &op->instrs[i]);
152 if (op->instrs[i].delay_ns)
153 ndelay(op->instrs[i].delay_ns);
159 static const struct nand_controller_ops fun_ops = {
160 .exec_op = fun_exec_op,
163 static int fun_probe(struct platform_device *ofdev)
165 struct fsl_upm_nand *fun;
166 struct resource *io_res;
172 fun = devm_kzalloc(&ofdev->dev, sizeof(*fun), GFP_KERNEL);
176 io_res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
177 fun->io_base = devm_ioremap_resource(&ofdev->dev, io_res);
178 if (IS_ERR(fun->io_base))
179 return PTR_ERR(fun->io_base);
181 ret = fsl_upm_find(io_res->start, &fun->upm);
183 dev_err(&ofdev->dev, "can't find UPM\n");
187 prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
189 if (!prop || size != sizeof(uint32_t)) {
190 dev_err(&ofdev->dev, "can't get UPM address offset\n");
193 fun->upm_addr_offset = *prop;
195 prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
196 if (!prop || size != sizeof(uint32_t)) {
197 dev_err(&ofdev->dev, "can't get UPM command offset\n");
200 fun->upm_cmd_offset = *prop;
202 prop = of_get_property(ofdev->dev.of_node,
203 "fsl,upm-addr-line-cs-offsets", &size);
204 if (prop && (size / sizeof(uint32_t)) > 0) {
205 fun->mchip_count = size / sizeof(uint32_t);
206 if (fun->mchip_count >= NAND_MAX_CHIPS) {
207 dev_err(&ofdev->dev, "too much multiple chips\n");
210 for (i = 0; i < fun->mchip_count; i++)
211 fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
213 fun->mchip_count = 1;
216 for (i = 0; i < fun->mchip_count; i++) {
217 fun->rnb_gpio[i] = devm_gpiod_get_index_optional(&ofdev->dev,
220 if (IS_ERR(fun->rnb_gpio[i])) {
221 dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
222 return PTR_ERR(fun->rnb_gpio[i]);
226 nand_controller_init(&fun->base);
227 fun->base.ops = &fun_ops;
228 fun->dev = &ofdev->dev;
230 ret = fun_chip_init(fun, ofdev->dev.of_node, io_res);
234 dev_set_drvdata(&ofdev->dev, fun);
239 static int fun_remove(struct platform_device *ofdev)
241 struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
242 struct nand_chip *chip = &fun->chip;
243 struct mtd_info *mtd = nand_to_mtd(chip);
246 ret = mtd_device_unregister(mtd);
253 static const struct of_device_id of_fun_match[] = {
254 { .compatible = "fsl,upm-nand" },
257 MODULE_DEVICE_TABLE(of, of_fun_match);
259 static struct platform_driver of_fun_driver = {
261 .name = "fsl,upm-nand",
262 .of_match_table = of_fun_match,
265 .remove = fun_remove,
268 module_platform_driver(of_fun_driver);
270 MODULE_LICENSE("GPL");
271 MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
272 MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
273 "LocalBus User-Programmable Machine");