2 * Freescale Integrated Flash Controller NAND driver
4 * Copyright 2011-2012 Freescale Semiconductor, Inc
6 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/of_address.h>
27 #include <linux/slab.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/rawnand.h>
30 #include <linux/mtd/partitions.h>
31 #include <linux/mtd/nand_ecc.h>
32 #include <linux/fsl_ifc.h>
33 #include <linux/iopoll.h>
35 #define ERR_BYTE 0xFF /* Value returned for read
36 bytes when read failed */
37 #define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait
38 for IFC NAND Machine */
42 /* mtd information per set */
44 struct nand_chip chip;
45 struct fsl_ifc_ctrl *ctrl;
48 int bank; /* Chip select bank number */
49 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
50 u8 __iomem *vbase; /* Chip select base virtual address */
53 /* overview of the fsl ifc controller */
54 struct fsl_ifc_nand_ctrl {
55 struct nand_controller controller;
56 struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
58 void __iomem *addr; /* Address of assigned IFC buffer */
59 unsigned int page; /* Last page written to / read from */
60 unsigned int read_bytes;/* Number of bytes read during command */
61 unsigned int column; /* Saved column from SEQIN */
62 unsigned int index; /* Pointer to next byte to 'read' */
63 unsigned int oob; /* Non zero if operating on OOB data */
64 unsigned int eccread; /* Non zero for a full-page ECC read */
65 unsigned int counter; /* counter for the initializations */
66 unsigned int max_bitflips; /* Saved during READ0 cmd */
69 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
72 * Generic flash bbt descriptors
74 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
75 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
77 static struct nand_bbt_descr bbt_main_descr = {
78 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
79 NAND_BBT_2BIT | NAND_BBT_VERSION,
80 .offs = 2, /* 0 on 8-bit small page */
84 .pattern = bbt_pattern,
87 static struct nand_bbt_descr bbt_mirror_descr = {
88 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
89 NAND_BBT_2BIT | NAND_BBT_VERSION,
90 .offs = 2, /* 0 on 8-bit small page */
94 .pattern = mirror_pattern,
97 static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section,
98 struct mtd_oob_region *oobregion)
100 struct nand_chip *chip = mtd_to_nand(mtd);
105 oobregion->offset = 8;
106 oobregion->length = chip->ecc.total;
111 static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section,
112 struct mtd_oob_region *oobregion)
114 struct nand_chip *chip = mtd_to_nand(mtd);
119 if (mtd->writesize == 512 &&
120 !(chip->options & NAND_BUSWIDTH_16)) {
122 oobregion->offset = 0;
123 oobregion->length = 5;
125 oobregion->offset = 6;
126 oobregion->length = 2;
133 oobregion->offset = 2;
134 oobregion->length = 6;
136 oobregion->offset = chip->ecc.total + 8;
137 oobregion->length = mtd->oobsize - oobregion->offset;
143 static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = {
144 .ecc = fsl_ifc_ooblayout_ecc,
145 .free = fsl_ifc_ooblayout_free,
149 * Set up the IFC hardware block and page address fields, and the ifc nand
150 * structure addr field to point to the correct IFC buffer in memory
152 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
154 struct nand_chip *chip = mtd_to_nand(mtd);
155 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
156 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
157 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
160 ifc_nand_ctrl->page = page_addr;
161 /* Program ROW0/COL0 */
162 ifc_out32(page_addr, &ifc->ifc_nand.row0);
163 ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
165 buf_num = page_addr & priv->bufnum_mask;
167 ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
168 ifc_nand_ctrl->index = column;
170 /* for OOB data point to the second half of the buffer */
172 ifc_nand_ctrl->index += mtd->writesize;
175 /* returns nonzero if entire page is blank */
176 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
177 u32 eccstat, unsigned int bufnum)
179 return (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
183 * execute IFC NAND command and wait for it to complete
185 static void fsl_ifc_run_command(struct mtd_info *mtd)
187 struct nand_chip *chip = mtd_to_nand(mtd);
188 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
189 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
190 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
191 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
195 /* set the chip select for NAND Transaction */
196 ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
197 &ifc->ifc_nand.nand_csel);
200 "%s: fir0=%08x fcr0=%08x\n",
202 ifc_in32(&ifc->ifc_nand.nand_fir0),
203 ifc_in32(&ifc->ifc_nand.nand_fcr0));
207 /* start read/write seq */
208 ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
210 /* wait for command complete flag or timeout */
211 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
212 msecs_to_jiffies(IFC_TIMEOUT_MSECS));
214 /* ctrl->nand_stat will be updated from IRQ context */
215 if (!ctrl->nand_stat)
216 dev_err(priv->dev, "Controller is not responding\n");
217 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
218 dev_err(priv->dev, "NAND Flash Timeout Error\n");
219 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
220 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
222 nctrl->max_bitflips = 0;
224 if (nctrl->eccread) {
226 int bufnum = nctrl->page & priv->bufnum_mask;
227 int sector_start = bufnum * chip->ecc.steps;
228 int sector_end = sector_start + chip->ecc.steps - 1;
229 __be32 __iomem *eccstat_regs;
231 eccstat_regs = ifc->ifc_nand.nand_eccstat;
232 eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
234 for (i = sector_start; i <= sector_end; i++) {
235 if (i != sector_start && !(i % 4))
236 eccstat = ifc_in32(&eccstat_regs[i / 4]);
238 errors = check_read_ecc(mtd, ctrl, eccstat, i);
242 * Uncorrectable error.
243 * We'll check for blank pages later.
245 * We disable ECCER reporting due to...
246 * erratum IFC-A002770 -- so report it now if we
247 * see an uncorrectable error in ECCSTAT.
249 ctrl->nand_stat |= IFC_NAND_EVTER_STAT_ECCER;
253 mtd->ecc_stats.corrected += errors;
254 nctrl->max_bitflips = max_t(unsigned int,
263 static void fsl_ifc_do_read(struct nand_chip *chip,
265 struct mtd_info *mtd)
267 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
268 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
269 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
271 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
272 if (mtd->writesize > 512) {
273 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
274 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
275 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
276 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
277 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
278 &ifc->ifc_nand.nand_fir0);
279 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
281 ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
282 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
283 &ifc->ifc_nand.nand_fcr0);
285 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
286 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
287 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
288 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
289 &ifc->ifc_nand.nand_fir0);
290 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
293 ifc_out32(NAND_CMD_READOOB <<
294 IFC_NAND_FCR0_CMD0_SHIFT,
295 &ifc->ifc_nand.nand_fcr0);
297 ifc_out32(NAND_CMD_READ0 <<
298 IFC_NAND_FCR0_CMD0_SHIFT,
299 &ifc->ifc_nand.nand_fcr0);
303 /* cmdfunc send commands to the IFC NAND Machine */
304 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
305 int column, int page_addr) {
306 struct nand_chip *chip = mtd_to_nand(mtd);
307 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
308 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
309 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
311 /* clear the read buffer */
312 ifc_nand_ctrl->read_bytes = 0;
313 if (command != NAND_CMD_PAGEPROG)
314 ifc_nand_ctrl->index = 0;
317 /* READ0 read the entire buffer to use hardware ECC. */
319 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
320 set_addr(mtd, 0, page_addr, 0);
322 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
323 ifc_nand_ctrl->index += column;
325 if (chip->ecc.mode == NAND_ECC_HW)
326 ifc_nand_ctrl->eccread = 1;
328 fsl_ifc_do_read(chip, 0, mtd);
329 fsl_ifc_run_command(mtd);
332 /* READOOB reads only the OOB because no ECC is performed. */
333 case NAND_CMD_READOOB:
334 ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
335 set_addr(mtd, column, page_addr, 1);
337 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
339 fsl_ifc_do_read(chip, 1, mtd);
340 fsl_ifc_run_command(mtd);
344 case NAND_CMD_READID:
345 case NAND_CMD_PARAM: {
347 * For READID, read 8 bytes that are currently used.
348 * For PARAM, read all 3 copies of 256-bytes pages.
351 int timing = IFC_FIR_OP_RB;
352 if (command == NAND_CMD_PARAM) {
353 timing = IFC_FIR_OP_RBCD;
357 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
358 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
359 (timing << IFC_NAND_FIR0_OP2_SHIFT),
360 &ifc->ifc_nand.nand_fir0);
361 ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
362 &ifc->ifc_nand.nand_fcr0);
363 ifc_out32(column, &ifc->ifc_nand.row3);
365 ifc_out32(len, &ifc->ifc_nand.nand_fbcr);
366 ifc_nand_ctrl->read_bytes = len;
368 set_addr(mtd, 0, 0, 0);
369 fsl_ifc_run_command(mtd);
373 /* ERASE1 stores the block and page address */
374 case NAND_CMD_ERASE1:
375 set_addr(mtd, 0, page_addr, 0);
378 /* ERASE2 uses the block and page address from ERASE1 */
379 case NAND_CMD_ERASE2:
380 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
381 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
382 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
383 &ifc->ifc_nand.nand_fir0);
385 ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
386 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
387 &ifc->ifc_nand.nand_fcr0);
389 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
390 ifc_nand_ctrl->read_bytes = 0;
391 fsl_ifc_run_command(mtd);
394 /* SEQIN sets up the addr buffer and all registers except the length */
395 case NAND_CMD_SEQIN: {
397 ifc_nand_ctrl->column = column;
398 ifc_nand_ctrl->oob = 0;
400 if (mtd->writesize > 512) {
402 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
403 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
404 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
407 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
408 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
409 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
410 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
411 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
412 &ifc->ifc_nand.nand_fir0);
414 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
415 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) |
416 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
417 &ifc->ifc_nand.nand_fir1);
419 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
420 IFC_NAND_FCR0_CMD1_SHIFT) |
422 IFC_NAND_FCR0_CMD2_SHIFT) |
424 IFC_NAND_FCR0_CMD3_SHIFT));
427 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
428 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
429 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
430 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
431 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
432 &ifc->ifc_nand.nand_fir0);
434 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
435 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
436 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) |
437 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
438 &ifc->ifc_nand.nand_fir1);
440 if (column >= mtd->writesize)
442 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
445 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
448 if (column >= mtd->writesize) {
449 /* OOB area --> READOOB */
450 column -= mtd->writesize;
451 ifc_nand_ctrl->oob = 1;
453 ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
454 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
458 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
459 case NAND_CMD_PAGEPROG: {
460 if (ifc_nand_ctrl->oob) {
461 ifc_out32(ifc_nand_ctrl->index -
462 ifc_nand_ctrl->column,
463 &ifc->ifc_nand.nand_fbcr);
465 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
468 fsl_ifc_run_command(mtd);
472 case NAND_CMD_STATUS: {
475 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
476 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
477 &ifc->ifc_nand.nand_fir0);
478 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
479 &ifc->ifc_nand.nand_fcr0);
480 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
481 set_addr(mtd, 0, 0, 0);
482 ifc_nand_ctrl->read_bytes = 1;
484 fsl_ifc_run_command(mtd);
487 * The chip always seems to report that it is
488 * write-protected, even when it is not.
490 addr = ifc_nand_ctrl->addr;
491 if (chip->options & NAND_BUSWIDTH_16)
492 ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr);
494 ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr);
499 ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
500 &ifc->ifc_nand.nand_fir0);
501 ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
502 &ifc->ifc_nand.nand_fcr0);
503 fsl_ifc_run_command(mtd);
507 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
512 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
514 /* The hardware does not seem to support multiple
520 * Write buf to the IFC NAND Controller Data Buffer
522 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
524 struct nand_chip *chip = mtd_to_nand(mtd);
525 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
526 unsigned int bufsize = mtd->writesize + mtd->oobsize;
529 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
533 if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
535 "%s: beyond end of buffer (%d requested, %u available)\n",
536 __func__, len, bufsize - ifc_nand_ctrl->index);
537 len = bufsize - ifc_nand_ctrl->index;
540 memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
541 ifc_nand_ctrl->index += len;
545 * Read a byte from either the IFC hardware buffer
546 * read function for 8-bit buswidth
548 static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
550 struct nand_chip *chip = mtd_to_nand(mtd);
551 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
555 * If there are still bytes in the IFC buffer, then use the
558 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
559 offset = ifc_nand_ctrl->index++;
560 return ifc_in8(ifc_nand_ctrl->addr + offset);
563 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
568 * Read two bytes from the IFC hardware buffer
569 * read function for 16-bit buswith
571 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
573 struct nand_chip *chip = mtd_to_nand(mtd);
574 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
578 * If there are still bytes in the IFC buffer, then use the
581 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
582 data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
583 ifc_nand_ctrl->index += 2;
584 return (uint8_t) data;
587 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
592 * Read from the IFC Controller Data Buffer
594 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
596 struct nand_chip *chip = mtd_to_nand(mtd);
597 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
601 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
605 avail = min((unsigned int)len,
606 ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
607 memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
608 ifc_nand_ctrl->index += avail;
612 "%s: beyond end of buffer (%d requested, %d available)\n",
613 __func__, len, avail);
617 * This function is called after Program and Erase Operations to
618 * check for success or failure.
620 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
622 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
623 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
624 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
628 /* Use READ_STATUS command, but wait for the device to be ready */
629 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
630 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
631 &ifc->ifc_nand.nand_fir0);
632 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
633 &ifc->ifc_nand.nand_fcr0);
634 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
635 set_addr(mtd, 0, 0, 0);
636 ifc_nand_ctrl->read_bytes = 1;
638 fsl_ifc_run_command(mtd);
640 nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
641 status = nand_fsr >> 24;
643 * The chip always seems to report that it is
644 * write-protected, even when it is not.
646 return status | NAND_STATUS_WP;
650 * The controller does not check for bitflips in erased pages,
651 * therefore software must check instead.
653 static int check_erased_page(struct nand_chip *chip, u8 *buf)
655 struct mtd_info *mtd = nand_to_mtd(chip);
656 u8 *ecc = chip->oob_poi;
657 const int ecc_size = chip->ecc.bytes;
658 const int pkt_size = chip->ecc.size;
659 int i, res, bitflips = 0;
660 struct mtd_oob_region oobregion = { };
662 mtd_ooblayout_ecc(mtd, 0, &oobregion);
663 ecc += oobregion.offset;
665 for (i = 0; i < chip->ecc.steps; ++i) {
666 res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
670 mtd->ecc_stats.failed++;
672 mtd->ecc_stats.corrected += res;
674 bitflips = max(res, bitflips);
682 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
683 uint8_t *buf, int oob_required, int page)
685 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
686 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
687 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
689 nand_read_page_op(chip, page, 0, buf, mtd->writesize);
691 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
693 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) {
695 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
697 return check_erased_page(chip, buf);
700 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
701 mtd->ecc_stats.failed++;
703 return nctrl->max_bitflips;
706 /* ECC will be calculated automatically, and errors will be detected in
709 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
710 const uint8_t *buf, int oob_required, int page)
712 nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
713 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
715 return nand_prog_page_end_op(chip);
718 static int fsl_ifc_attach_chip(struct nand_chip *chip)
720 struct mtd_info *mtd = nand_to_mtd(chip);
721 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
723 dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
725 dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
727 dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
729 dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
731 dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
733 dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
735 dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
737 dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
738 chip->phys_erase_shift);
739 dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
741 dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
743 dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
745 dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
747 dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__,
749 dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
750 dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
751 dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
753 dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
755 dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
761 static const struct nand_controller_ops fsl_ifc_controller_ops = {
762 .attach_chip = fsl_ifc_attach_chip,
765 static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
767 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
768 struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
769 struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
770 uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
771 uint32_t cs = priv->bank;
773 if (ctrl->version < FSL_IFC_VERSION_1_1_0)
776 if (ctrl->version > FSL_IFC_VERSION_1_1_0) {
780 /* Trigger auto initialization */
781 ncfgr = ifc_in32(&ifc_runtime->ifc_nand.ncfgr);
782 ifc_out32(ncfgr | IFC_NAND_NCFGR_SRAM_INIT_EN, &ifc_runtime->ifc_nand.ncfgr);
784 /* Wait until done */
785 ret = readx_poll_timeout(ifc_in32, &ifc_runtime->ifc_nand.ncfgr,
786 status, !(status & IFC_NAND_NCFGR_SRAM_INIT_EN),
787 10, IFC_TIMEOUT_MSECS * 1000);
789 dev_err(priv->dev, "Failed to initialize SRAM!\n");
794 /* Save CSOR and CSOR_ext */
795 csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
796 csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
798 /* chage PageSize 8K and SpareSize 1K*/
799 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
800 ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor);
801 ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext);
804 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
805 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
806 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
807 &ifc_runtime->ifc_nand.nand_fir0);
808 ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
809 &ifc_runtime->ifc_nand.nand_fcr0);
810 ifc_out32(0x0, &ifc_runtime->ifc_nand.row3);
812 ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr);
814 /* Program ROW0/COL0 */
815 ifc_out32(0x0, &ifc_runtime->ifc_nand.row0);
816 ifc_out32(0x0, &ifc_runtime->ifc_nand.col0);
818 /* set the chip select for NAND Transaction */
819 ifc_out32(cs << IFC_NAND_CSEL_SHIFT,
820 &ifc_runtime->ifc_nand.nand_csel);
823 ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT,
824 &ifc_runtime->ifc_nand.nandseq_strt);
826 /* wait for command complete flag or timeout */
827 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
828 msecs_to_jiffies(IFC_TIMEOUT_MSECS));
830 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) {
831 pr_err("fsl-ifc: Failed to Initialise SRAM\n");
835 /* Restore CSOR and CSOR_ext */
836 ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
837 ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
842 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
844 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
845 struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
846 struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
847 struct nand_chip *chip = &priv->chip;
848 struct mtd_info *mtd = nand_to_mtd(&priv->chip);
852 /* Fill in fsl_ifc_mtd structure */
853 mtd->dev.parent = priv->dev;
854 nand_set_flash_node(chip, priv->dev->of_node);
856 /* fill in nand_chip structure */
857 /* set up function call table */
858 if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
860 chip->read_byte = fsl_ifc_read_byte16;
862 chip->read_byte = fsl_ifc_read_byte;
864 chip->write_buf = fsl_ifc_write_buf;
865 chip->read_buf = fsl_ifc_read_buf;
866 chip->select_chip = fsl_ifc_select_chip;
867 chip->cmdfunc = fsl_ifc_cmdfunc;
868 chip->waitfunc = fsl_ifc_wait;
869 chip->set_features = nand_get_set_features_notsupp;
870 chip->get_features = nand_get_set_features_notsupp;
872 chip->bbt_td = &bbt_main_descr;
873 chip->bbt_md = &bbt_mirror_descr;
875 ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
877 /* set up nand options */
878 chip->bbt_options = NAND_BBT_USE_FLASH;
879 chip->options = NAND_NO_SUBPAGE_WRITE;
881 if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
882 & CSPR_PORT_SIZE_16) {
883 chip->read_byte = fsl_ifc_read_byte16;
884 chip->options |= NAND_BUSWIDTH_16;
886 chip->read_byte = fsl_ifc_read_byte;
889 chip->controller = &ifc_nand_ctrl->controller;
890 nand_set_controller_data(chip, priv);
892 chip->ecc.read_page = fsl_ifc_read_page;
893 chip->ecc.write_page = fsl_ifc_write_page;
895 csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
897 switch (csor & CSOR_NAND_PGS_MASK) {
898 case CSOR_NAND_PGS_512:
899 if (!(chip->options & NAND_BUSWIDTH_16)) {
900 /* Avoid conflict with bad block marker */
901 bbt_main_descr.offs = 0;
902 bbt_mirror_descr.offs = 0;
905 priv->bufnum_mask = 15;
908 case CSOR_NAND_PGS_2K:
909 priv->bufnum_mask = 3;
912 case CSOR_NAND_PGS_4K:
913 priv->bufnum_mask = 1;
916 case CSOR_NAND_PGS_8K:
917 priv->bufnum_mask = 0;
921 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
925 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
926 if (csor & CSOR_NAND_ECC_DEC_EN) {
927 chip->ecc.mode = NAND_ECC_HW;
928 mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
930 /* Hardware generates ECC per 512 Bytes */
931 chip->ecc.size = 512;
932 if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
934 chip->ecc.strength = 4;
936 chip->ecc.bytes = 16;
937 chip->ecc.strength = 8;
940 chip->ecc.mode = NAND_ECC_SOFT;
941 chip->ecc.algo = NAND_ECC_HAMMING;
944 ret = fsl_ifc_sram_init(priv);
949 * As IFC version 2.0.0 has 16KB of internal SRAM as compared to older
950 * versions which had 8KB. Hence bufnum mask needs to be updated.
952 if (ctrl->version >= FSL_IFC_VERSION_2_0_0)
953 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
958 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
960 struct mtd_info *mtd = nand_to_mtd(&priv->chip);
965 iounmap(priv->vbase);
967 ifc_nand_ctrl->chips[priv->bank] = NULL;
972 static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank,
975 u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);
977 if (!(cspr & CSPR_V))
979 if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
982 return (cspr & CSPR_BA) == convert_ifc_address(addr);
985 static DEFINE_MUTEX(fsl_ifc_nand_mutex);
987 static int fsl_ifc_nand_probe(struct platform_device *dev)
989 struct fsl_ifc_runtime __iomem *ifc;
990 struct fsl_ifc_mtd *priv;
992 static const char *part_probe_types[]
993 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
996 struct device_node *node = dev->dev.of_node;
997 struct mtd_info *mtd;
999 if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs)
1001 ifc = fsl_ifc_ctrl_dev->rregs;
1003 /* get, allocate and map the memory resource */
1004 ret = of_address_to_resource(node, 0, &res);
1006 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
1010 /* find which chip select it is connected to */
1011 for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
1012 if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))
1016 if (bank >= fsl_ifc_ctrl_dev->banks) {
1017 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
1022 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1026 mutex_lock(&fsl_ifc_nand_mutex);
1027 if (!fsl_ifc_ctrl_dev->nand) {
1028 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
1029 if (!ifc_nand_ctrl) {
1030 mutex_unlock(&fsl_ifc_nand_mutex);
1034 ifc_nand_ctrl->read_bytes = 0;
1035 ifc_nand_ctrl->index = 0;
1036 ifc_nand_ctrl->addr = NULL;
1037 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
1039 nand_controller_init(&ifc_nand_ctrl->controller);
1041 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
1043 mutex_unlock(&fsl_ifc_nand_mutex);
1045 ifc_nand_ctrl->chips[bank] = priv;
1047 priv->ctrl = fsl_ifc_ctrl_dev;
1048 priv->dev = &dev->dev;
1050 priv->vbase = ioremap(res.start, resource_size(&res));
1052 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1057 dev_set_drvdata(priv->dev, priv);
1059 ifc_out32(IFC_NAND_EVTER_EN_OPC_EN |
1060 IFC_NAND_EVTER_EN_FTOER_EN |
1061 IFC_NAND_EVTER_EN_WPER_EN,
1062 &ifc->ifc_nand.nand_evter_en);
1064 /* enable NAND Machine Interrupts */
1065 ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN |
1066 IFC_NAND_EVTER_INTR_FTOERIR_EN |
1067 IFC_NAND_EVTER_INTR_WPERIR_EN,
1068 &ifc->ifc_nand.nand_evter_intr_en);
1070 mtd = nand_to_mtd(&priv->chip);
1071 mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1077 ret = fsl_ifc_chip_init(priv);
1081 priv->chip.controller->ops = &fsl_ifc_controller_ops;
1082 ret = nand_scan(&priv->chip, 1);
1086 /* First look for RedBoot table or partitions on the command
1087 * line, these take precedence over device tree information */
1088 ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
1092 dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1093 (unsigned long long)res.start, priv->bank);
1098 nand_cleanup(&priv->chip);
1100 fsl_ifc_chip_remove(priv);
1105 static int fsl_ifc_nand_remove(struct platform_device *dev)
1107 struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1109 nand_release(&priv->chip);
1110 fsl_ifc_chip_remove(priv);
1112 mutex_lock(&fsl_ifc_nand_mutex);
1113 ifc_nand_ctrl->counter--;
1114 if (!ifc_nand_ctrl->counter) {
1115 fsl_ifc_ctrl_dev->nand = NULL;
1116 kfree(ifc_nand_ctrl);
1118 mutex_unlock(&fsl_ifc_nand_mutex);
1123 static const struct of_device_id fsl_ifc_nand_match[] = {
1125 .compatible = "fsl,ifc-nand",
1129 MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match);
1131 static struct platform_driver fsl_ifc_nand_driver = {
1133 .name = "fsl,ifc-nand",
1134 .of_match_table = fsl_ifc_nand_match,
1136 .probe = fsl_ifc_nand_probe,
1137 .remove = fsl_ifc_nand_remove,
1140 module_platform_driver(fsl_ifc_nand_driver);
1142 MODULE_LICENSE("GPL");
1143 MODULE_AUTHOR("Freescale");
1144 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");