1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
5 * The data sheet for this device can be found at:
6 * http://wiki.laptop.org/go/Datasheets
8 * Copyright © 2006 Red Hat, Inc.
9 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
14 #include <linux/device.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/rawnand.h>
18 #include <linux/mtd/partitions.h>
19 #include <linux/rslib.h>
20 #include <linux/pci.h>
21 #include <linux/delay.h>
22 #include <linux/interrupt.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
28 #define CAFE_NAND_CTRL1 0x00
29 #define CAFE_NAND_CTRL2 0x04
30 #define CAFE_NAND_CTRL3 0x08
31 #define CAFE_NAND_STATUS 0x0c
32 #define CAFE_NAND_IRQ 0x10
33 #define CAFE_NAND_IRQ_MASK 0x14
34 #define CAFE_NAND_DATA_LEN 0x18
35 #define CAFE_NAND_ADDR1 0x1c
36 #define CAFE_NAND_ADDR2 0x20
37 #define CAFE_NAND_TIMING1 0x24
38 #define CAFE_NAND_TIMING2 0x28
39 #define CAFE_NAND_TIMING3 0x2c
40 #define CAFE_NAND_NONMEM 0x30
41 #define CAFE_NAND_ECC_RESULT 0x3C
42 #define CAFE_NAND_DMA_CTRL 0x40
43 #define CAFE_NAND_DMA_ADDR0 0x44
44 #define CAFE_NAND_DMA_ADDR1 0x48
45 #define CAFE_NAND_ECC_SYN01 0x50
46 #define CAFE_NAND_ECC_SYN23 0x54
47 #define CAFE_NAND_ECC_SYN45 0x58
48 #define CAFE_NAND_ECC_SYN67 0x5c
49 #define CAFE_NAND_READ_DATA 0x1000
50 #define CAFE_NAND_WRITE_DATA 0x2000
52 #define CAFE_GLOBAL_CTRL 0x3004
53 #define CAFE_GLOBAL_IRQ 0x3008
54 #define CAFE_GLOBAL_IRQ_MASK 0x300c
55 #define CAFE_NAND_RESET 0x3034
57 /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
58 #define CTRL1_CHIPSELECT (1<<19)
61 struct nand_chip nand;
64 struct rs_control *rs;
73 unsigned char *dmabuf;
76 static int usedma = 1;
77 module_param(usedma, int, 0644);
79 static int skipbbt = 0;
80 module_param(skipbbt, int, 0644);
83 module_param(debug, int, 0644);
85 static int regdebug = 0;
86 module_param(regdebug, int, 0644);
88 static int checkecc = 1;
89 module_param(checkecc, int, 0644);
91 static unsigned int numtimings;
93 module_param_array(timing, int, &numtimings, 0644);
95 static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
97 /* Hrm. Why isn't this already conditional on something in the struct device? */
98 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
100 /* Make it easier to switch to PIO if we need to */
101 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
102 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
104 static int cafe_device_ready(struct nand_chip *chip)
106 struct cafe_priv *cafe = nand_get_controller_data(chip);
107 int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000);
108 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
110 cafe_writel(cafe, irqs, NAND_IRQ);
112 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
113 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
114 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
120 static void cafe_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
122 struct cafe_priv *cafe = nand_get_controller_data(chip);
125 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
127 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
129 cafe->datalen += len;
131 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
135 static void cafe_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
137 struct cafe_priv *cafe = nand_get_controller_data(chip);
140 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
142 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
144 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
146 cafe->datalen += len;
149 static uint8_t cafe_read_byte(struct nand_chip *chip)
151 struct cafe_priv *cafe = nand_get_controller_data(chip);
154 cafe_read_buf(chip, &d, 1);
155 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
160 static void cafe_nand_cmdfunc(struct nand_chip *chip, unsigned command,
161 int column, int page_addr)
163 struct mtd_info *mtd = nand_to_mtd(chip);
164 struct cafe_priv *cafe = nand_get_controller_data(chip);
167 uint32_t doneint = 0x80000000;
169 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
170 command, column, page_addr);
172 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
173 /* Second half of a command we already calculated */
174 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
176 cafe->ctl2 &= ~(1<<30);
177 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
178 cafe->ctl1, cafe->nr_data);
181 /* Reset ECC engine */
182 cafe_writel(cafe, 0, NAND_CTRL2);
184 /* Emulate NAND_CMD_READOOB on large-page chips */
185 if (mtd->writesize > 512 &&
186 command == NAND_CMD_READOOB) {
187 column += mtd->writesize;
188 command = NAND_CMD_READ0;
191 /* FIXME: Do we need to send read command before sending data
192 for small-page chips, to position the buffer correctly? */
195 cafe_writel(cafe, column, NAND_ADDR1);
199 } else if (page_addr != -1) {
200 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
203 cafe_writel(cafe, page_addr, NAND_ADDR2);
205 if (mtd->size > mtd->writesize << 16)
209 cafe->data_pos = cafe->datalen = 0;
211 /* Set command valid bit, mask in the chip select bit */
212 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
214 /* Set RD or WR bits as appropriate */
215 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
216 ctl1 |= (1<<26); /* rd */
217 /* Always 5 bytes, for now */
219 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
221 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
222 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
223 ctl1 |= 1<<26; /* rd */
224 /* For now, assume just read to end of page */
225 cafe->datalen = mtd->writesize + mtd->oobsize - column;
226 } else if (command == NAND_CMD_SEQIN)
227 ctl1 |= 1<<25; /* wr */
229 /* Set number of address bytes */
231 ctl1 |= ((adrbytes-1)|8) << 27;
233 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
234 /* Ignore the first command of a pair; the hardware
235 deals with them both at once, later */
237 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
238 cafe->ctl1, cafe->datalen);
241 /* RNDOUT and READ0 commands need a following byte */
242 if (command == NAND_CMD_RNDOUT)
243 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
244 else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
245 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
248 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
249 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
251 /* NB: The datasheet lies -- we really should be subtracting 1 here */
252 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
253 cafe_writel(cafe, 0x90000000, NAND_IRQ);
254 if (cafe->usedma && (ctl1 & (3<<25))) {
255 uint32_t dmactl = 0xc0000000 + cafe->datalen;
256 /* If WR or RD bits set, set up DMA */
257 if (ctl1 & (1<<26)) {
260 /* ... so it's done when the DMA is done, not just
262 doneint = 0x10000000;
264 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
268 if (unlikely(regdebug)) {
270 printk("About to write command %08x to register 0\n", ctl1);
271 for (i=4; i< 0x5c; i+=4)
272 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
275 cafe_writel(cafe, ctl1, NAND_CTRL1);
276 /* Apply this short delay always to ensure that we do wait tWB in
277 * any case on any machine. */
284 for (c = 500000; c != 0; c--) {
285 irqs = cafe_readl(cafe, NAND_IRQ);
290 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
293 cafe_writel(cafe, doneint, NAND_IRQ);
294 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
295 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
298 WARN_ON(cafe->ctl2 & (1<<30));
302 case NAND_CMD_CACHEDPROG:
303 case NAND_CMD_PAGEPROG:
304 case NAND_CMD_ERASE1:
305 case NAND_CMD_ERASE2:
308 case NAND_CMD_STATUS:
309 case NAND_CMD_RNDOUT:
310 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
313 nand_wait_ready(chip);
314 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
317 static void cafe_select_chip(struct nand_chip *chip, int chipnr)
319 struct cafe_priv *cafe = nand_get_controller_data(chip);
321 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
323 /* Mask the appropriate bit into the stored value of ctl1
324 which will be used by cafe_nand_cmdfunc() */
326 cafe->ctl1 |= CTRL1_CHIPSELECT;
328 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
331 static irqreturn_t cafe_nand_interrupt(int irq, void *id)
333 struct mtd_info *mtd = id;
334 struct nand_chip *chip = mtd_to_nand(mtd);
335 struct cafe_priv *cafe = nand_get_controller_data(chip);
336 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
337 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
341 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
345 static int cafe_nand_write_oob(struct nand_chip *chip, int page)
347 struct mtd_info *mtd = nand_to_mtd(chip);
349 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
353 /* Don't use -- use nand_read_oob_std for now */
354 static int cafe_nand_read_oob(struct nand_chip *chip, int page)
356 struct mtd_info *mtd = nand_to_mtd(chip);
358 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
361 * cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read
362 * @mtd: mtd info structure
363 * @chip: nand chip info structure
364 * @buf: buffer to store read data
365 * @oob_required: caller expects OOB data read to chip->oob_poi
367 * The hw generator calculates the error syndrome automatically. Therefore
368 * we need a special oob layout and handling.
370 static int cafe_nand_read_page(struct nand_chip *chip, uint8_t *buf,
371 int oob_required, int page)
373 struct mtd_info *mtd = nand_to_mtd(chip);
374 struct cafe_priv *cafe = nand_get_controller_data(chip);
375 unsigned int max_bitflips = 0;
377 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
378 cafe_readl(cafe, NAND_ECC_RESULT),
379 cafe_readl(cafe, NAND_ECC_SYN01));
381 nand_read_page_op(chip, page, 0, buf, mtd->writesize);
382 chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
384 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
385 unsigned short syn[8], pat[4];
387 u8 *oob = chip->oob_poi;
390 for (i=0; i<8; i+=2) {
391 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
393 syn[i] = cafe->rs->codec->index_of[tmp & 0xfff];
394 syn[i+1] = cafe->rs->codec->index_of[(tmp >> 16) & 0xfff];
397 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
400 for (i = 0; i < n; i++) {
403 /* The 12-bit symbols are mapped to bytes here */
409 /* high four bits do not correspond to data */
414 } else if (p == 1365) {
415 buf[2047] ^= pat[i] >> 4;
416 oob[0] ^= pat[i] << 4;
417 } else if (p > 1365) {
419 oob[3*p/2 - 2048] ^= pat[i] >> 4;
420 oob[3*p/2 - 2047] ^= pat[i] << 4;
422 oob[3*p/2 - 2049] ^= pat[i] >> 8;
423 oob[3*p/2 - 2048] ^= pat[i];
425 } else if ((p & 1) == 1) {
426 buf[3*p/2] ^= pat[i] >> 4;
427 buf[3*p/2 + 1] ^= pat[i] << 4;
429 buf[3*p/2 - 1] ^= pat[i] >> 8;
430 buf[3*p/2] ^= pat[i];
435 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
436 cafe_readl(cafe, NAND_ADDR2) * 2048);
437 for (i = 0; i < 0x5c; i += 4)
438 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
439 mtd->ecc_stats.failed++;
441 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
442 mtd->ecc_stats.corrected += n;
443 max_bitflips = max_t(unsigned int, max_bitflips, n);
450 static int cafe_ooblayout_ecc(struct mtd_info *mtd, int section,
451 struct mtd_oob_region *oobregion)
453 struct nand_chip *chip = mtd_to_nand(mtd);
458 oobregion->offset = 0;
459 oobregion->length = chip->ecc.total;
464 static int cafe_ooblayout_free(struct mtd_info *mtd, int section,
465 struct mtd_oob_region *oobregion)
467 struct nand_chip *chip = mtd_to_nand(mtd);
472 oobregion->offset = chip->ecc.total;
473 oobregion->length = mtd->oobsize - chip->ecc.total;
478 static const struct mtd_ooblayout_ops cafe_ooblayout_ops = {
479 .ecc = cafe_ooblayout_ecc,
480 .free = cafe_ooblayout_free,
483 /* Ick. The BBT code really ought to be able to work this bit out
484 for itself from the above, at least for the 2KiB case */
485 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
486 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
488 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
489 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
492 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
493 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
494 | NAND_BBT_2BIT | NAND_BBT_VERSION,
499 .pattern = cafe_bbt_pattern_2048
502 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
503 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
504 | NAND_BBT_2BIT | NAND_BBT_VERSION,
509 .pattern = cafe_mirror_pattern_2048
512 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
513 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
514 | NAND_BBT_2BIT | NAND_BBT_VERSION,
519 .pattern = cafe_bbt_pattern_512
522 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
523 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
524 | NAND_BBT_2BIT | NAND_BBT_VERSION,
529 .pattern = cafe_mirror_pattern_512
533 static int cafe_nand_write_page_lowlevel(struct nand_chip *chip,
534 const uint8_t *buf, int oob_required,
537 struct mtd_info *mtd = nand_to_mtd(chip);
538 struct cafe_priv *cafe = nand_get_controller_data(chip);
540 nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
541 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
543 /* Set up ECC autogeneration */
544 cafe->ctl2 |= (1<<30);
546 return nand_prog_page_end_op(chip);
549 /* F_2[X]/(X**6+X+1) */
550 static unsigned short gf64_mul(u8 a, u8 b)
556 for (i = 0; i < 6; i++) {
568 /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */
569 static u16 gf4096_mul(u16 a, u16 b)
571 u8 ah, al, bh, bl, ch, cl;
578 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
579 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
581 return (ch << 6) ^ cl;
584 static int cafe_mul(int x)
588 return gf4096_mul(x, 0xe01);
591 static int cafe_nand_attach_chip(struct nand_chip *chip)
593 struct mtd_info *mtd = nand_to_mtd(chip);
594 struct cafe_priv *cafe = nand_get_controller_data(chip);
597 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112,
598 &cafe->dmaaddr, GFP_KERNEL);
602 /* Set up DMA address */
603 cafe_writel(cafe, lower_32_bits(cafe->dmaaddr), NAND_DMA_ADDR0);
604 cafe_writel(cafe, upper_32_bits(cafe->dmaaddr), NAND_DMA_ADDR1);
606 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
607 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
609 /* Restore the DMA flag */
610 cafe->usedma = usedma;
612 cafe->ctl2 = BIT(27); /* Reed-Solomon ECC */
613 if (mtd->writesize == 2048)
614 cafe->ctl2 |= BIT(29); /* 2KiB page size */
616 /* Set up ECC according to the type of chip we found */
617 mtd_set_ooblayout(mtd, &cafe_ooblayout_ops);
618 if (mtd->writesize == 2048) {
619 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
620 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
621 } else if (mtd->writesize == 512) {
622 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
623 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
625 dev_warn(&cafe->pdev->dev,
626 "Unexpected NAND flash writesize %d. Aborting\n",
632 cafe->nand.ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
633 cafe->nand.ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
634 cafe->nand.ecc.size = mtd->writesize;
635 cafe->nand.ecc.bytes = 14;
636 cafe->nand.ecc.strength = 4;
637 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
638 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
639 cafe->nand.ecc.read_page = cafe_nand_read_page;
640 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
645 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
650 static void cafe_nand_detach_chip(struct nand_chip *chip)
652 struct cafe_priv *cafe = nand_get_controller_data(chip);
654 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
657 static const struct nand_controller_ops cafe_nand_controller_ops = {
658 .attach_chip = cafe_nand_attach_chip,
659 .detach_chip = cafe_nand_detach_chip,
662 static int cafe_nand_probe(struct pci_dev *pdev,
663 const struct pci_device_id *ent)
665 struct mtd_info *mtd;
666 struct cafe_priv *cafe;
670 /* Very old versions shared the same PCI ident for all three
671 functions on the chip. Verify the class too... */
672 if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
675 err = pci_enable_device(pdev);
679 pci_set_master(pdev);
681 cafe = kzalloc(sizeof(*cafe), GFP_KERNEL);
685 mtd = nand_to_mtd(&cafe->nand);
686 mtd->dev.parent = &pdev->dev;
687 nand_set_controller_data(&cafe->nand, cafe);
690 cafe->mmio = pci_iomap(pdev, 0, 0);
692 dev_warn(&pdev->dev, "failed to iomap\n");
697 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
703 cafe->nand.legacy.cmdfunc = cafe_nand_cmdfunc;
704 cafe->nand.legacy.dev_ready = cafe_device_ready;
705 cafe->nand.legacy.read_byte = cafe_read_byte;
706 cafe->nand.legacy.read_buf = cafe_read_buf;
707 cafe->nand.legacy.write_buf = cafe_write_buf;
708 cafe->nand.legacy.select_chip = cafe_select_chip;
709 cafe->nand.legacy.set_features = nand_get_set_features_notsupp;
710 cafe->nand.legacy.get_features = nand_get_set_features_notsupp;
712 cafe->nand.legacy.chip_delay = 0;
714 /* Enable the following for a flash based bad block table */
715 cafe->nand.bbt_options = NAND_BBT_USE_FLASH;
718 cafe->nand.options |= NAND_SKIP_BBTSCAN | NAND_NO_BBM_QUIRK;
720 if (numtimings && numtimings != 3) {
721 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
724 if (numtimings == 3) {
725 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
726 timing[0], timing[1], timing[2]);
728 timing[0] = cafe_readl(cafe, NAND_TIMING1);
729 timing[1] = cafe_readl(cafe, NAND_TIMING2);
730 timing[2] = cafe_readl(cafe, NAND_TIMING3);
732 if (timing[0] | timing[1] | timing[2]) {
733 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
734 timing[0], timing[1], timing[2]);
736 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
737 timing[0] = timing[1] = timing[2] = 0xffffffff;
741 /* Start off by resetting the NAND controller completely */
742 cafe_writel(cafe, 1, NAND_RESET);
743 cafe_writel(cafe, 0, NAND_RESET);
745 cafe_writel(cafe, timing[0], NAND_TIMING1);
746 cafe_writel(cafe, timing[1], NAND_TIMING2);
747 cafe_writel(cafe, timing[2], NAND_TIMING3);
749 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
750 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
753 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
757 /* Disable master reset, enable NAND clock */
758 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
761 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
762 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
763 cafe_writel(cafe, 0, NAND_DMA_CTRL);
765 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
766 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
768 /* Enable NAND IRQ in global IRQ mask register */
769 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
770 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
771 cafe_readl(cafe, GLOBAL_CTRL),
772 cafe_readl(cafe, GLOBAL_IRQ_MASK));
774 /* Do not use the DMA during the NAND identification */
777 /* Scan to find existence of the device */
778 cafe->nand.legacy.dummy_controller.ops = &cafe_nand_controller_ops;
779 err = nand_scan(&cafe->nand, 2);
783 pci_set_drvdata(pdev, mtd);
785 mtd->name = "cafe_nand";
786 err = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
788 goto out_cleanup_nand;
793 nand_cleanup(&cafe->nand);
795 /* Disable NAND IRQ in global IRQ mask register */
796 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
797 free_irq(pdev->irq, mtd);
801 pci_iounmap(pdev, cafe->mmio);
808 static void cafe_nand_remove(struct pci_dev *pdev)
810 struct mtd_info *mtd = pci_get_drvdata(pdev);
811 struct nand_chip *chip = mtd_to_nand(mtd);
812 struct cafe_priv *cafe = nand_get_controller_data(chip);
815 /* Disable NAND IRQ in global IRQ mask register */
816 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
817 free_irq(pdev->irq, mtd);
818 ret = mtd_device_unregister(mtd);
822 pci_iounmap(pdev, cafe->mmio);
823 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
827 static const struct pci_device_id cafe_nand_tbl[] = {
828 { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND,
829 PCI_ANY_ID, PCI_ANY_ID },
833 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
835 static int cafe_nand_resume(struct pci_dev *pdev)
838 struct mtd_info *mtd = pci_get_drvdata(pdev);
839 struct nand_chip *chip = mtd_to_nand(mtd);
840 struct cafe_priv *cafe = nand_get_controller_data(chip);
842 /* Start off by resetting the NAND controller completely */
843 cafe_writel(cafe, 1, NAND_RESET);
844 cafe_writel(cafe, 0, NAND_RESET);
845 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
847 /* Restore timing configuration */
848 cafe_writel(cafe, timing[0], NAND_TIMING1);
849 cafe_writel(cafe, timing[1], NAND_TIMING2);
850 cafe_writel(cafe, timing[2], NAND_TIMING3);
852 /* Disable master reset, enable NAND clock */
853 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
856 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
857 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
858 cafe_writel(cafe, 0, NAND_DMA_CTRL);
859 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
860 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
862 /* Set up DMA address */
863 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
864 if (sizeof(cafe->dmaaddr) > 4)
865 /* Shift in two parts to shut the compiler up */
866 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
868 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
870 /* Enable NAND IRQ in global IRQ mask register */
871 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
875 static struct pci_driver cafe_nand_pci_driver = {
877 .id_table = cafe_nand_tbl,
878 .probe = cafe_nand_probe,
879 .remove = cafe_nand_remove,
880 .resume = cafe_nand_resume,
883 module_pci_driver(cafe_nand_pci_driver);
885 MODULE_LICENSE("GPL");
886 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
887 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");