drivers/mtd/nand/raw/atmel/nand-controller.c

   1 /*
   2  * Copyright 2017 ATMEL
   3  * Copyright 2017 Free Electrons
   4  *
   5  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
   6  *
   7  * Derived from the atmel_nand.c driver which contained the following
   8  * copyrights:
   9  *
  10  *   Copyright 2003 Rick Bronson
  11  *
  12  *   Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
  13  *      Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
  14  *
  15  *   Derived from drivers/mtd/spia.c (removed in v3.8)
  16  *      Copyright 2000 Steven J. Hill (sjhill@cotw.com)
  17  *
  18  *
  19  *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  20  *      Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
  21  *
  22  *   Derived from Das U-Boot source code
  23  *      (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  24  *      Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  25  *
  26  *   Add Programmable Multibit ECC support for various AT91 SoC
  27  *      Copyright 2012 ATMEL, Hong Xu
  28  *
  29  *   Add Nand Flash Controller support for SAMA5 SoC
  30  *      Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
  31  *
  32  * This program is free software; you can redistribute it and/or modify
  33  * it under the terms of the GNU General Public License version 2 as
  34  * published by the Free Software Foundation.
  35  *
  36  * A few words about the naming convention in this file. This convention
  37  * applies to structure and function names.
  38  *
  39  * Prefixes:
  40  *
  41  * - atmel_nand_: all generic structures/functions
  42  * - atmel_smc_nand_: all structures/functions specific to the SMC interface
  43  *                    (at91sam9 and avr32 SoCs)
  44  * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
  45  *                     (sama5 SoCs and later)
  46  * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
  47  *               that is available in the HSMC block
  48  * - <soc>_nand_: all SoC specific structures/functions
  49  */
  50
  51 #include <linux/clk.h>
  52 #include <linux/dma-mapping.h>
  53 #include <linux/dmaengine.h>
  54 #include <linux/genalloc.h>
  55 #include <linux/gpio/consumer.h>
  56 #include <linux/interrupt.h>
  57 #include <linux/mfd/syscon.h>
  58 #include <linux/mfd/syscon/atmel-matrix.h>
  59 #include <linux/mfd/syscon/atmel-smc.h>
  60 #include <linux/module.h>
  61 #include <linux/mtd/rawnand.h>
  62 #include <linux/of_address.h>
  63 #include <linux/of_irq.h>
  64 #include <linux/of_platform.h>
  65 #include <linux/iopoll.h>
  66 #include <linux/platform_device.h>
  67 #include <linux/regmap.h>
  68
  69 #include "pmecc.h"
  70
  71 #define ATMEL_HSMC_NFC_CFG                      0x0
  72 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)         (((x) / 4) << 24)
  73 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK       GENMASK(30, 24)
  74 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul)        (((cyc) << 16) | ((mul) << 20))
  75 #define ATMEL_HSMC_NFC_CFG_DTO_MAX              GENMASK(22, 16)
  76 #define ATMEL_HSMC_NFC_CFG_RBEDGE               BIT(13)
  77 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE         BIT(12)
  78 #define ATMEL_HSMC_NFC_CFG_RSPARE               BIT(9)
  79 #define ATMEL_HSMC_NFC_CFG_WSPARE               BIT(8)
  80 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK        GENMASK(2, 0)
  81 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x)          (fls((x) / 512) - 1)
  82
  83 #define ATMEL_HSMC_NFC_CTRL                     0x4
  84 #define ATMEL_HSMC_NFC_CTRL_EN                  BIT(0)
  85 #define ATMEL_HSMC_NFC_CTRL_DIS                 BIT(1)
  86
  87 #define ATMEL_HSMC_NFC_SR                       0x8
  88 #define ATMEL_HSMC_NFC_IER                      0xc
  89 #define ATMEL_HSMC_NFC_IDR                      0x10
  90 #define ATMEL_HSMC_NFC_IMR                      0x14
  91 #define ATMEL_HSMC_NFC_SR_ENABLED               BIT(1)
  92 #define ATMEL_HSMC_NFC_SR_RB_RISE               BIT(4)
  93 #define ATMEL_HSMC_NFC_SR_RB_FALL               BIT(5)
  94 #define ATMEL_HSMC_NFC_SR_BUSY                  BIT(8)
  95 #define ATMEL_HSMC_NFC_SR_WR                    BIT(11)
  96 #define ATMEL_HSMC_NFC_SR_CSID                  GENMASK(14, 12)
  97 #define ATMEL_HSMC_NFC_SR_XFRDONE               BIT(16)
  98 #define ATMEL_HSMC_NFC_SR_CMDDONE               BIT(17)
  99 #define ATMEL_HSMC_NFC_SR_DTOE                  BIT(20)
 100 #define ATMEL_HSMC_NFC_SR_UNDEF                 BIT(21)
 101 #define ATMEL_HSMC_NFC_SR_AWB                   BIT(22)
 102 #define ATMEL_HSMC_NFC_SR_NFCASE                BIT(23)
 103 #define ATMEL_HSMC_NFC_SR_ERRORS                (ATMEL_HSMC_NFC_SR_DTOE | \
 104                                                  ATMEL_HSMC_NFC_SR_UNDEF | \
 105                                                  ATMEL_HSMC_NFC_SR_AWB | \
 106                                                  ATMEL_HSMC_NFC_SR_NFCASE)
 107 #define ATMEL_HSMC_NFC_SR_RBEDGE(x)             BIT((x) + 24)
 108
 109 #define ATMEL_HSMC_NFC_ADDR                     0x18
 110 #define ATMEL_HSMC_NFC_BANK                     0x1c
 111
 112 #define ATMEL_NFC_MAX_RB_ID                     7
 113
 114 #define ATMEL_NFC_SRAM_SIZE                     0x2400
 115
 116 #define ATMEL_NFC_CMD(pos, cmd)                 ((cmd) << (((pos) * 8) + 2))
 117 #define ATMEL_NFC_VCMD2                         BIT(18)
 118 #define ATMEL_NFC_ACYCLE(naddrs)                ((naddrs) << 19)
 119 #define ATMEL_NFC_CSID(cs)                      ((cs) << 22)
 120 #define ATMEL_NFC_DATAEN                        BIT(25)
 121 #define ATMEL_NFC_NFCWR                         BIT(26)
 122
 123 #define ATMEL_NFC_MAX_ADDR_CYCLES               5
 124
 125 #define ATMEL_NAND_ALE_OFFSET                   BIT(21)
 126 #define ATMEL_NAND_CLE_OFFSET                   BIT(22)
 127
 128 #define DEFAULT_TIMEOUT_MS                      1000
 129 #define MIN_DMA_LEN                             128
 130
 131 static bool atmel_nand_avoid_dma __read_mostly;
 132
 133 MODULE_PARM_DESC(avoiddma, "Avoid using DMA");
 134 module_param_named(avoiddma, atmel_nand_avoid_dma, bool, 0400);
 135
 136 enum atmel_nand_rb_type {
 137         ATMEL_NAND_NO_RB,
 138         ATMEL_NAND_NATIVE_RB,
 139         ATMEL_NAND_GPIO_RB,
 140 };
 141
 142 struct atmel_nand_rb {
 143         enum atmel_nand_rb_type type;
 144         union {
 145                 struct gpio_desc *gpio;
 146                 int id;
 147         };
 148 };
 149
 150 struct atmel_nand_cs {
 151         int id;
 152         struct atmel_nand_rb rb;
 153         struct gpio_desc *csgpio;
 154         struct {
 155                 void __iomem *virt;
 156                 dma_addr_t dma;
 157         } io;
 158
 159         struct atmel_smc_cs_conf smcconf;
 160 };
 161
 162 struct atmel_nand {
 163         struct list_head node;
 164         struct device *dev;
 165         struct nand_chip base;
 166         struct atmel_nand_cs *activecs;
 167         struct atmel_pmecc_user *pmecc;
 168         struct gpio_desc *cdgpio;
 169         int numcs;
 170         struct atmel_nand_cs cs[];
 171 };
 172
 173 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
 174 {
 175         return container_of(chip, struct atmel_nand, base);
 176 }
 177
 178 enum atmel_nfc_data_xfer {
 179         ATMEL_NFC_NO_DATA,
 180         ATMEL_NFC_READ_DATA,
 181         ATMEL_NFC_WRITE_DATA,
 182 };
 183
 184 struct atmel_nfc_op {
 185         u8 cs;
 186         u8 ncmds;
 187         u8 cmds[2];
 188         u8 naddrs;
 189         u8 addrs[5];
 190         enum atmel_nfc_data_xfer data;
 191         u32 wait;
 192         u32 errors;
 193 };
 194
 195 struct atmel_nand_controller;
 196 struct atmel_nand_controller_caps;
 197
 198 struct atmel_nand_controller_ops {
 199         int (*probe)(struct platform_device *pdev,
 200                      const struct atmel_nand_controller_caps *caps);
 201         int (*remove)(struct atmel_nand_controller *nc);
 202         void (*nand_init)(struct atmel_nand_controller *nc,
 203                           struct atmel_nand *nand);
 204         int (*ecc_init)(struct nand_chip *chip);
 205         int (*setup_data_interface)(struct atmel_nand *nand, int csline,
 206                                     const struct nand_data_interface *conf);
 207 };
 208
 209 struct atmel_nand_controller_caps {
 210         bool has_dma;
 211         bool legacy_of_bindings;
 212         u32 ale_offs;
 213         u32 cle_offs;
 214         const struct atmel_nand_controller_ops *ops;
 215 };
 216
 217 struct atmel_nand_controller {
 218         struct nand_controller base;
 219         const struct atmel_nand_controller_caps *caps;
 220         struct device *dev;
 221         struct regmap *smc;
 222         struct dma_chan *dmac;
 223         struct atmel_pmecc *pmecc;
 224         struct list_head chips;
 225         struct clk *mck;
 226 };
 227
 228 static inline struct atmel_nand_controller *
 229 to_nand_controller(struct nand_controller *ctl)
 230 {
 231         return container_of(ctl, struct atmel_nand_controller, base);
 232 }
 233
 234 struct atmel_smc_nand_controller {
 235         struct atmel_nand_controller base;
 236         struct regmap *matrix;
 237         unsigned int ebi_csa_offs;
 238 };
 239
 240 static inline struct atmel_smc_nand_controller *
 241 to_smc_nand_controller(struct nand_controller *ctl)
 242 {
 243         return container_of(to_nand_controller(ctl),
 244                             struct atmel_smc_nand_controller, base);
 245 }
 246
 247 struct atmel_hsmc_nand_controller {
 248         struct atmel_nand_controller base;
 249         struct {
 250                 struct gen_pool *pool;
 251                 void __iomem *virt;
 252                 dma_addr_t dma;
 253         } sram;
 254         const struct atmel_hsmc_reg_layout *hsmc_layout;
 255         struct regmap *io;
 256         struct atmel_nfc_op op;
 257         struct completion complete;
 258         int irq;
 259
 260         /* Only used when instantiating from legacy DT bindings. */
 261         struct clk *clk;
 262 };
 263
 264 static inline struct atmel_hsmc_nand_controller *
 265 to_hsmc_nand_controller(struct nand_controller *ctl)
 266 {
 267         return container_of(to_nand_controller(ctl),
 268                             struct atmel_hsmc_nand_controller, base);
 269 }
 270
 271 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
 272 {
 273         op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
 274         op->wait ^= status & op->wait;
 275
 276         return !op->wait || op->errors;
 277 }
 278
 279 static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
 280 {
 281         struct atmel_hsmc_nand_controller *nc = data;
 282         u32 sr, rcvd;
 283         bool done;
 284
 285         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
 286
 287         rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
 288         done = atmel_nfc_op_done(&nc->op, sr);
 289
 290         if (rcvd)
 291                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
 292
 293         if (done)
 294                 complete(&nc->complete);
 295
 296         return rcvd ? IRQ_HANDLED : IRQ_NONE;
 297 }
 298
 299 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
 300                           unsigned int timeout_ms)
 301 {
 302         int ret;
 303
 304         if (!timeout_ms)
 305                 timeout_ms = DEFAULT_TIMEOUT_MS;
 306
 307         if (poll) {
 308                 u32 status;
 309
 310                 ret = regmap_read_poll_timeout(nc->base.smc,
 311                                                ATMEL_HSMC_NFC_SR, status,
 312                                                atmel_nfc_op_done(&nc->op,
 313                                                                  status),
 314                                                0, timeout_ms * 1000);
 315         } else {
 316                 init_completion(&nc->complete);
 317                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
 318                              nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
 319                 ret = wait_for_completion_timeout(&nc->complete,
 320                                                 msecs_to_jiffies(timeout_ms));
 321                 if (!ret)
 322                         ret = -ETIMEDOUT;
 323                 else
 324                         ret = 0;
 325
 326                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
 327         }
 328
 329         if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
 330                 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
 331                 ret = -ETIMEDOUT;
 332         }
 333
 334         if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
 335                 dev_err(nc->base.dev, "Access to an undefined area\n");
 336                 ret = -EIO;
 337         }
 338
 339         if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
 340                 dev_err(nc->base.dev, "Access while busy\n");
 341                 ret = -EIO;
 342         }
 343
 344         if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
 345                 dev_err(nc->base.dev, "Wrong access size\n");
 346                 ret = -EIO;
 347         }
 348
 349         return ret;
 350 }
 351
 352 static void atmel_nand_dma_transfer_finished(void *data)
 353 {
 354         struct completion *finished = data;
 355
 356         complete(finished);
 357 }
 358
 359 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
 360                                    void *buf, dma_addr_t dev_dma, size_t len,
 361                                    enum dma_data_direction dir)
 362 {
 363         DECLARE_COMPLETION_ONSTACK(finished);
 364         dma_addr_t src_dma, dst_dma, buf_dma;
 365         struct dma_async_tx_descriptor *tx;
 366         dma_cookie_t cookie;
 367
 368         buf_dma = dma_map_single(nc->dev, buf, len, dir);
 369         if (dma_mapping_error(nc->dev, dev_dma)) {
 370                 dev_err(nc->dev,
 371                         "Failed to prepare a buffer for DMA access\n");
 372                 goto err;
 373         }
 374
 375         if (dir == DMA_FROM_DEVICE) {
 376                 src_dma = dev_dma;
 377                 dst_dma = buf_dma;
 378         } else {
 379                 src_dma = buf_dma;
 380                 dst_dma = dev_dma;
 381         }
 382
 383         tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
 384                                        DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
 385         if (!tx) {
 386                 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
 387                 goto err_unmap;
 388         }
 389
 390         tx->callback = atmel_nand_dma_transfer_finished;
 391         tx->callback_param = &finished;
 392
 393         cookie = dmaengine_submit(tx);
 394         if (dma_submit_error(cookie)) {
 395                 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
 396                 goto err_unmap;
 397         }
 398
 399         dma_async_issue_pending(nc->dmac);
 400         wait_for_completion(&finished);
 401
 402         return 0;
 403
 404 err_unmap:
 405         dma_unmap_single(nc->dev, buf_dma, len, dir);
 406
 407 err:
 408         dev_dbg(nc->dev, "Fall back to CPU I/O\n");
 409
 410         return -EIO;
 411 }
 412
 413 static u8 atmel_nand_read_byte(struct mtd_info *mtd)
 414 {
 415         struct nand_chip *chip = mtd_to_nand(mtd);
 416         struct atmel_nand *nand = to_atmel_nand(chip);
 417
 418         return ioread8(nand->activecs->io.virt);
 419 }
 420
 421 static u16 atmel_nand_read_word(struct mtd_info *mtd)
 422 {
 423         struct nand_chip *chip = mtd_to_nand(mtd);
 424         struct atmel_nand *nand = to_atmel_nand(chip);
 425
 426         return ioread16(nand->activecs->io.virt);
 427 }
 428
 429 static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
 430 {
 431         struct nand_chip *chip = mtd_to_nand(mtd);
 432         struct atmel_nand *nand = to_atmel_nand(chip);
 433
 434         if (chip->options & NAND_BUSWIDTH_16)
 435                 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
 436         else
 437                 iowrite8(byte, nand->activecs->io.virt);
 438 }
 439
 440 static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 441 {
 442         struct nand_chip *chip = mtd_to_nand(mtd);
 443         struct atmel_nand *nand = to_atmel_nand(chip);
 444         struct atmel_nand_controller *nc;
 445
 446         nc = to_nand_controller(chip->controller);
 447
 448         /*
 449          * If the controller supports DMA, the buffer address is DMA-able and
 450          * len is long enough to make DMA transfers profitable, let's trigger
 451          * a DMA transfer. If it fails, fallback to PIO mode.
 452          */
 453         if (nc->dmac && virt_addr_valid(buf) &&
 454             len >= MIN_DMA_LEN &&
 455             !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
 456                                      DMA_FROM_DEVICE))
 457                 return;
 458
 459         if (chip->options & NAND_BUSWIDTH_16)
 460                 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
 461         else
 462                 ioread8_rep(nand->activecs->io.virt, buf, len);
 463 }
 464
 465 static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 466 {
 467         struct nand_chip *chip = mtd_to_nand(mtd);
 468         struct atmel_nand *nand = to_atmel_nand(chip);
 469         struct atmel_nand_controller *nc;
 470
 471         nc = to_nand_controller(chip->controller);
 472
 473         /*
 474          * If the controller supports DMA, the buffer address is DMA-able and
 475          * len is long enough to make DMA transfers profitable, let's trigger
 476          * a DMA transfer. If it fails, fallback to PIO mode.
 477          */
 478         if (nc->dmac && virt_addr_valid(buf) &&
 479             len >= MIN_DMA_LEN &&
 480             !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
 481                                      len, DMA_TO_DEVICE))
 482                 return;
 483
 484         if (chip->options & NAND_BUSWIDTH_16)
 485                 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
 486         else
 487                 iowrite8_rep(nand->activecs->io.virt, buf, len);
 488 }
 489
 490 static int atmel_nand_dev_ready(struct mtd_info *mtd)
 491 {
 492         struct nand_chip *chip = mtd_to_nand(mtd);
 493         struct atmel_nand *nand = to_atmel_nand(chip);
 494
 495         return gpiod_get_value(nand->activecs->rb.gpio);
 496 }
 497
 498 static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
 499 {
 500         struct nand_chip *chip = mtd_to_nand(mtd);
 501         struct atmel_nand *nand = to_atmel_nand(chip);
 502
 503         if (cs < 0 || cs >= nand->numcs) {
 504                 nand->activecs = NULL;
 505                 chip->dev_ready = NULL;
 506                 return;
 507         }
 508
 509         nand->activecs = &nand->cs[cs];
 510
 511         if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
 512                 chip->dev_ready = atmel_nand_dev_ready;
 513 }
 514
 515 static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
 516 {
 517         struct nand_chip *chip = mtd_to_nand(mtd);
 518         struct atmel_nand *nand = to_atmel_nand(chip);
 519         struct atmel_hsmc_nand_controller *nc;
 520         u32 status;
 521
 522         nc = to_hsmc_nand_controller(chip->controller);
 523
 524         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
 525
 526         return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
 527 }
 528
 529 static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
 530 {
 531         struct nand_chip *chip = mtd_to_nand(mtd);
 532         struct atmel_nand *nand = to_atmel_nand(chip);
 533         struct atmel_hsmc_nand_controller *nc;
 534
 535         nc = to_hsmc_nand_controller(chip->controller);
 536
 537         atmel_nand_select_chip(mtd, cs);
 538
 539         if (!nand->activecs) {
 540                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 541                              ATMEL_HSMC_NFC_CTRL_DIS);
 542                 return;
 543         }
 544
 545         if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
 546                 chip->dev_ready = atmel_hsmc_nand_dev_ready;
 547
 548         regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
 549                            ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
 550                            ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
 551                            ATMEL_HSMC_NFC_CFG_RSPARE |
 552                            ATMEL_HSMC_NFC_CFG_WSPARE,
 553                            ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
 554                            ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
 555                            ATMEL_HSMC_NFC_CFG_RSPARE);
 556         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 557                      ATMEL_HSMC_NFC_CTRL_EN);
 558 }
 559
 560 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
 561 {
 562         u8 *addrs = nc->op.addrs;
 563         unsigned int op = 0;
 564         u32 addr, val;
 565         int i, ret;
 566
 567         nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
 568
 569         for (i = 0; i < nc->op.ncmds; i++)
 570                 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
 571
 572         if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 573                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
 574
 575         op |= ATMEL_NFC_CSID(nc->op.cs) |
 576               ATMEL_NFC_ACYCLE(nc->op.naddrs);
 577
 578         if (nc->op.ncmds > 1)
 579                 op |= ATMEL_NFC_VCMD2;
 580
 581         addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
 582                (addrs[3] << 24);
 583
 584         if (nc->op.data != ATMEL_NFC_NO_DATA) {
 585                 op |= ATMEL_NFC_DATAEN;
 586                 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
 587
 588                 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
 589                         op |= ATMEL_NFC_NFCWR;
 590         }
 591
 592         /* Clear all flags. */
 593         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
 594
 595         /* Send the command. */
 596         regmap_write(nc->io, op, addr);
 597
 598         ret = atmel_nfc_wait(nc, poll, 0);
 599         if (ret)
 600                 dev_err(nc->base.dev,
 601                         "Failed to send NAND command (err = %d)!",
 602                         ret);
 603
 604         /* Reset the op state. */
 605         memset(&nc->op, 0, sizeof(nc->op));
 606
 607         return ret;
 608 }
 609
 610 static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
 611                                      unsigned int ctrl)
 612 {
 613         struct nand_chip *chip = mtd_to_nand(mtd);
 614         struct atmel_nand *nand = to_atmel_nand(chip);
 615         struct atmel_hsmc_nand_controller *nc;
 616
 617         nc = to_hsmc_nand_controller(chip->controller);
 618
 619         if (ctrl & NAND_ALE) {
 620                 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 621                         return;
 622
 623                 nc->op.addrs[nc->op.naddrs++] = dat;
 624         } else if (ctrl & NAND_CLE) {
 625                 if (nc->op.ncmds > 1)
 626                         return;
 627
 628                 nc->op.cmds[nc->op.ncmds++] = dat;
 629         }
 630
 631         if (dat == NAND_CMD_NONE) {
 632                 nc->op.cs = nand->activecs->id;
 633                 atmel_nfc_exec_op(nc, true);
 634         }
 635 }
 636
 637 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 638                                 unsigned int ctrl)
 639 {
 640         struct nand_chip *chip = mtd_to_nand(mtd);
 641         struct atmel_nand *nand = to_atmel_nand(chip);
 642         struct atmel_nand_controller *nc;
 643
 644         nc = to_nand_controller(chip->controller);
 645
 646         if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) {
 647                 if (ctrl & NAND_NCE)
 648                         gpiod_set_value(nand->activecs->csgpio, 0);
 649                 else
 650                         gpiod_set_value(nand->activecs->csgpio, 1);
 651         }
 652
 653         if (ctrl & NAND_ALE)
 654                 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
 655         else if (ctrl & NAND_CLE)
 656                 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
 657 }
 658
 659 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
 660                                    bool oob_required)
 661 {
 662         struct mtd_info *mtd = nand_to_mtd(chip);
 663         struct atmel_hsmc_nand_controller *nc;
 664         int ret = -EIO;
 665
 666         nc = to_hsmc_nand_controller(chip->controller);
 667
 668         if (nc->base.dmac)
 669                 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
 670                                               nc->sram.dma, mtd->writesize,
 671                                               DMA_TO_DEVICE);
 672
 673         /* Falling back to CPU copy. */
 674         if (ret)
 675                 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
 676
 677         if (oob_required)
 678                 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
 679                             mtd->oobsize);
 680 }
 681
 682 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
 683                                      bool oob_required)
 684 {
 685         struct mtd_info *mtd = nand_to_mtd(chip);
 686         struct atmel_hsmc_nand_controller *nc;
 687         int ret = -EIO;
 688
 689         nc = to_hsmc_nand_controller(chip->controller);
 690
 691         if (nc->base.dmac)
 692                 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
 693                                               mtd->writesize, DMA_FROM_DEVICE);
 694
 695         /* Falling back to CPU copy. */
 696         if (ret)
 697                 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
 698
 699         if (oob_required)
 700                 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
 701                               mtd->oobsize);
 702 }
 703
 704 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
 705 {
 706         struct mtd_info *mtd = nand_to_mtd(chip);
 707         struct atmel_hsmc_nand_controller *nc;
 708
 709         nc = to_hsmc_nand_controller(chip->controller);
 710
 711         if (column >= 0) {
 712                 nc->op.addrs[nc->op.naddrs++] = column;
 713
 714                 /*
 715                  * 2 address cycles for the column offset on large page NANDs.
 716                  */
 717                 if (mtd->writesize > 512)
 718                         nc->op.addrs[nc->op.naddrs++] = column >> 8;
 719         }
 720
 721         if (page >= 0) {
 722                 nc->op.addrs[nc->op.naddrs++] = page;
 723                 nc->op.addrs[nc->op.naddrs++] = page >> 8;
 724
 725                 if (chip->options & NAND_ROW_ADDR_3)
 726                         nc->op.addrs[nc->op.naddrs++] = page >> 16;
 727         }
 728 }
 729
 730 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
 731 {
 732         struct atmel_nand *nand = to_atmel_nand(chip);
 733         struct atmel_nand_controller *nc;
 734         int ret;
 735
 736         nc = to_nand_controller(chip->controller);
 737
 738         if (raw)
 739                 return 0;
 740
 741         ret = atmel_pmecc_enable(nand->pmecc, op);
 742         if (ret)
 743                 dev_err(nc->dev,
 744                         "Failed to enable ECC engine (err = %d)\n", ret);
 745
 746         return ret;
 747 }
 748
 749 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
 750 {
 751         struct atmel_nand *nand = to_atmel_nand(chip);
 752
 753         if (!raw)
 754                 atmel_pmecc_disable(nand->pmecc);
 755 }
 756
 757 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
 758 {
 759         struct atmel_nand *nand = to_atmel_nand(chip);
 760         struct mtd_info *mtd = nand_to_mtd(chip);
 761         struct atmel_nand_controller *nc;
 762         struct mtd_oob_region oobregion;
 763         void *eccbuf;
 764         int ret, i;
 765
 766         nc = to_nand_controller(chip->controller);
 767
 768         if (raw)
 769                 return 0;
 770
 771         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 772         if (ret) {
 773                 dev_err(nc->dev,
 774                         "Failed to transfer NAND page data (err = %d)\n",
 775                         ret);
 776                 return ret;
 777         }
 778
 779         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 780         eccbuf = chip->oob_poi + oobregion.offset;
 781
 782         for (i = 0; i < chip->ecc.steps; i++) {
 783                 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
 784                                                    eccbuf);
 785                 eccbuf += chip->ecc.bytes;
 786         }
 787
 788         return 0;
 789 }
 790
 791 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
 792                                          bool raw)
 793 {
 794         struct atmel_nand *nand = to_atmel_nand(chip);
 795         struct mtd_info *mtd = nand_to_mtd(chip);
 796         struct atmel_nand_controller *nc;
 797         struct mtd_oob_region oobregion;
 798         int ret, i, max_bitflips = 0;
 799         void *databuf, *eccbuf;
 800
 801         nc = to_nand_controller(chip->controller);
 802
 803         if (raw)
 804                 return 0;
 805
 806         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 807         if (ret) {
 808                 dev_err(nc->dev,
 809                         "Failed to read NAND page data (err = %d)\n",
 810                         ret);
 811                 return ret;
 812         }
 813
 814         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 815         eccbuf = chip->oob_poi + oobregion.offset;
 816         databuf = buf;
 817
 818         for (i = 0; i < chip->ecc.steps; i++) {
 819                 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
 820                                                  eccbuf);
 821                 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
 822                         ret = nand_check_erased_ecc_chunk(databuf,
 823                                                           chip->ecc.size,
 824                                                           eccbuf,
 825                                                           chip->ecc.bytes,
 826                                                           NULL, 0,
 827                                                           chip->ecc.strength);
 828
 829                 if (ret >= 0) {
 830                         mtd->ecc_stats.corrected += ret;
 831                         max_bitflips = max(ret, max_bitflips);
 832                 } else {
 833                         mtd->ecc_stats.failed++;
 834                 }
 835
 836                 databuf += chip->ecc.size;
 837                 eccbuf += chip->ecc.bytes;
 838         }
 839
 840         return max_bitflips;
 841 }
 842
 843 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
 844                                      bool oob_required, int page, bool raw)
 845 {
 846         struct mtd_info *mtd = nand_to_mtd(chip);
 847         struct atmel_nand *nand = to_atmel_nand(chip);
 848         int ret;
 849
 850         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
 851
 852         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 853         if (ret)
 854                 return ret;
 855
 856         atmel_nand_write_buf(mtd, buf, mtd->writesize);
 857
 858         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 859         if (ret) {
 860                 atmel_pmecc_disable(nand->pmecc);
 861                 return ret;
 862         }
 863
 864         atmel_nand_pmecc_disable(chip, raw);
 865
 866         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 867
 868         return nand_prog_page_end_op(chip);
 869 }
 870
 871 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 872                                        struct nand_chip *chip, const u8 *buf,
 873                                        int oob_required, int page)
 874 {
 875         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
 876 }
 877
 878 static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
 879                                            struct nand_chip *chip,
 880                                            const u8 *buf, int oob_required,
 881                                            int page)
 882 {
 883         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
 884 }
 885
 886 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 887                                     bool oob_required, int page, bool raw)
 888 {
 889         struct mtd_info *mtd = nand_to_mtd(chip);
 890         int ret;
 891
 892         nand_read_page_op(chip, page, 0, NULL, 0);
 893
 894         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
 895         if (ret)
 896                 return ret;
 897
 898         atmel_nand_read_buf(mtd, buf, mtd->writesize);
 899         atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 900
 901         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
 902
 903         atmel_nand_pmecc_disable(chip, raw);
 904
 905         return ret;
 906 }
 907
 908 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 909                                       struct nand_chip *chip, u8 *buf,
 910                                       int oob_required, int page)
 911 {
 912         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
 913 }
 914
 915 static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
 916                                           struct nand_chip *chip, u8 *buf,
 917                                           int oob_required, int page)
 918 {
 919         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
 920 }
 921
 922 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
 923                                           const u8 *buf, bool oob_required,
 924                                           int page, bool raw)
 925 {
 926         struct mtd_info *mtd = nand_to_mtd(chip);
 927         struct atmel_nand *nand = to_atmel_nand(chip);
 928         struct atmel_hsmc_nand_controller *nc;
 929         int ret, status;
 930
 931         nc = to_hsmc_nand_controller(chip->controller);
 932
 933         atmel_nfc_copy_to_sram(chip, buf, false);
 934
 935         nc->op.cmds[0] = NAND_CMD_SEQIN;
 936         nc->op.ncmds = 1;
 937         atmel_nfc_set_op_addr(chip, page, 0x0);
 938         nc->op.cs = nand->activecs->id;
 939         nc->op.data = ATMEL_NFC_WRITE_DATA;
 940
 941         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 942         if (ret)
 943                 return ret;
 944
 945         ret = atmel_nfc_exec_op(nc, false);
 946         if (ret) {
 947                 atmel_nand_pmecc_disable(chip, raw);
 948                 dev_err(nc->base.dev,
 949                         "Failed to transfer NAND page data (err = %d)\n",
 950                         ret);
 951                 return ret;
 952         }
 953
 954         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 955
 956         atmel_nand_pmecc_disable(chip, raw);
 957
 958         if (ret)
 959                 return ret;
 960
 961         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 962
 963         nc->op.cmds[0] = NAND_CMD_PAGEPROG;
 964         nc->op.ncmds = 1;
 965         nc->op.cs = nand->activecs->id;
 966         ret = atmel_nfc_exec_op(nc, false);
 967         if (ret)
 968                 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
 969                         ret);
 970
 971         status = chip->waitfunc(mtd, chip);
 972         if (status & NAND_STATUS_FAIL)
 973                 return -EIO;
 974
 975         return ret;
 976 }
 977
 978 static int atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd,
 979                                             struct nand_chip *chip,
 980                                             const u8 *buf, int oob_required,
 981                                             int page)
 982 {
 983         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 984                                               false);
 985 }
 986
 987 static int atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd,
 988                                                 struct nand_chip *chip,
 989                                                 const u8 *buf,
 990                                                 int oob_required, int page)
 991 {
 992         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 993                                               true);
 994 }
 995
 996 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 997                                          bool oob_required, int page,
 998                                          bool raw)
 999 {
1000         struct mtd_info *mtd = nand_to_mtd(chip);
1001         struct atmel_nand *nand = to_atmel_nand(chip);
1002         struct atmel_hsmc_nand_controller *nc;
1003         int ret;
1004
1005         nc = to_hsmc_nand_controller(chip->controller);
1006
1007         /*
1008          * Optimized read page accessors only work when the NAND R/B pin is
1009          * connected to a native SoC R/B pin. If that's not the case, fallback
1010          * to the non-optimized one.
1011          */
1012         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
1013                 nand_read_page_op(chip, page, 0, NULL, 0);
1014
1015                 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
1016                                                 raw);
1017         }
1018
1019         nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1020
1021         if (mtd->writesize > 512)
1022                 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1023
1024         atmel_nfc_set_op_addr(chip, page, 0x0);
1025         nc->op.cs = nand->activecs->id;
1026         nc->op.data = ATMEL_NFC_READ_DATA;
1027
1028         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1029         if (ret)
1030                 return ret;
1031
1032         ret = atmel_nfc_exec_op(nc, false);
1033         if (ret) {
1034                 atmel_nand_pmecc_disable(chip, raw);
1035                 dev_err(nc->base.dev,
1036                         "Failed to load NAND page data (err = %d)\n",
1037                         ret);
1038                 return ret;
1039         }
1040
1041         atmel_nfc_copy_from_sram(chip, buf, true);
1042
1043         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1044
1045         atmel_nand_pmecc_disable(chip, raw);
1046
1047         return ret;
1048 }
1049
1050 static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
1051                                            struct nand_chip *chip, u8 *buf,
1052                                            int oob_required, int page)
1053 {
1054         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1055                                              false);
1056 }
1057
1058 static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
1059                                                struct nand_chip *chip,
1060                                                u8 *buf, int oob_required,
1061                                                int page)
1062 {
1063         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1064                                              true);
1065 }
1066
1067 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1068 {
1069         struct mtd_info *mtd = nand_to_mtd(chip);
1070         struct atmel_nand *nand = to_atmel_nand(chip);
1071         struct atmel_nand_controller *nc;
1072         struct atmel_pmecc_user_req req;
1073
1074         nc = to_nand_controller(chip->controller);
1075
1076         if (!nc->pmecc) {
1077                 dev_err(nc->dev, "HW ECC not supported\n");
1078                 return -ENOTSUPP;
1079         }
1080
1081         if (nc->caps->legacy_of_bindings) {
1082                 u32 val;
1083
1084                 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1085                                           &val))
1086                         chip->ecc.strength = val;
1087
1088                 if (!of_property_read_u32(nc->dev->of_node,
1089                                           "atmel,pmecc-sector-size",
1090                                           &val))
1091                         chip->ecc.size = val;
1092         }
1093
1094         if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1095                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1096         else if (chip->ecc.strength)
1097                 req.ecc.strength = chip->ecc.strength;
1098         else if (chip->ecc_strength_ds)
1099                 req.ecc.strength = chip->ecc_strength_ds;
1100         else
1101                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1102
1103         if (chip->ecc.size)
1104                 req.ecc.sectorsize = chip->ecc.size;
1105         else if (chip->ecc_step_ds)
1106                 req.ecc.sectorsize = chip->ecc_step_ds;
1107         else
1108                 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1109
1110         req.pagesize = mtd->writesize;
1111         req.oobsize = mtd->oobsize;
1112
1113         if (mtd->writesize <= 512) {
1114                 req.ecc.bytes = 4;
1115                 req.ecc.ooboffset = 0;
1116         } else {
1117                 req.ecc.bytes = mtd->oobsize - 2;
1118                 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1119         }
1120
1121         nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1122         if (IS_ERR(nand->pmecc))
1123                 return PTR_ERR(nand->pmecc);
1124
1125         chip->ecc.algo = NAND_ECC_BCH;
1126         chip->ecc.size = req.ecc.sectorsize;
1127         chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1128         chip->ecc.strength = req.ecc.strength;
1129
1130         chip->options |= NAND_NO_SUBPAGE_WRITE;
1131
1132         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1133
1134         return 0;
1135 }
1136
1137 static int atmel_nand_ecc_init(struct nand_chip *chip)
1138 {
1139         struct atmel_nand_controller *nc;
1140         int ret;
1141
1142         nc = to_nand_controller(chip->controller);
1143
1144         switch (chip->ecc.mode) {
1145         case NAND_ECC_NONE:
1146         case NAND_ECC_SOFT:
1147                 /*
1148                  * Nothing to do, the core will initialize everything for us.
1149                  */
1150                 break;
1151
1152         case NAND_ECC_HW:
1153                 ret = atmel_nand_pmecc_init(chip);
1154                 if (ret)
1155                         return ret;
1156
1157                 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1158                 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1159                 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1160                 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1161                 break;
1162
1163         default:
1164                 /* Other modes are not supported. */
1165                 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1166                         chip->ecc.mode);
1167                 return -ENOTSUPP;
1168         }
1169
1170         return 0;
1171 }
1172
1173 static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
1174 {
1175         int ret;
1176
1177         ret = atmel_nand_ecc_init(chip);
1178         if (ret)
1179                 return ret;
1180
1181         if (chip->ecc.mode != NAND_ECC_HW)
1182                 return 0;
1183
1184         /* Adjust the ECC operations for the HSMC IP. */
1185         chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1186         chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1187         chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1188         chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1189
1190         return 0;
1191 }
1192
1193 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1194                                         const struct nand_data_interface *conf,
1195                                         struct atmel_smc_cs_conf *smcconf)
1196 {
1197         u32 ncycles, totalcycles, timeps, mckperiodps;
1198         struct atmel_nand_controller *nc;
1199         int ret;
1200
1201         nc = to_nand_controller(nand->base.controller);
1202
1203         /* DDR interface not supported. */
1204         if (conf->type != NAND_SDR_IFACE)
1205                 return -ENOTSUPP;
1206
1207         /*
1208          * tRC < 30ns implies EDO mode. This controller does not support this
1209          * mode.
1210          */
1211         if (conf->timings.sdr.tRC_min < 30000)
1212                 return -ENOTSUPP;
1213
1214         atmel_smc_cs_conf_init(smcconf);
1215
1216         mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1217         mckperiodps *= 1000;
1218
1219         /*
1220          * Set write pulse timing. This one is easy to extract:
1221          *
1222          * NWE_PULSE = tWP
1223          */
1224         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1225         totalcycles = ncycles;
1226         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1227                                           ncycles);
1228         if (ret)
1229                 return ret;
1230
1231         /*
1232          * The write setup timing depends on the operation done on the NAND.
1233          * All operations goes through the same data bus, but the operation
1234          * type depends on the address we are writing to (ALE/CLE address
1235          * lines).
1236          * Since we have no way to differentiate the different operations at
1237          * the SMC level, we must consider the worst case (the biggest setup
1238          * time among all operation types):
1239          *
1240          * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1241          */
1242         timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1243                       conf->timings.sdr.tALS_min);
1244         timeps = max(timeps, conf->timings.sdr.tDS_min);
1245         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1246         ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1247         totalcycles += ncycles;
1248         ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1249                                           ncycles);
1250         if (ret)
1251                 return ret;
1252
1253         /*
1254          * As for the write setup timing, the write hold timing depends on the
1255          * operation done on the NAND:
1256          *
1257          * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1258          */
1259         timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1260                       conf->timings.sdr.tALH_min);
1261         timeps = max3(timeps, conf->timings.sdr.tDH_min,
1262                       conf->timings.sdr.tWH_min);
1263         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1264         totalcycles += ncycles;
1265
1266         /*
1267          * The write cycle timing is directly matching tWC, but is also
1268          * dependent on the other timings on the setup and hold timings we
1269          * calculated earlier, which gives:
1270          *
1271          * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1272          */
1273         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1274         ncycles = max(totalcycles, ncycles);
1275         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1276                                           ncycles);
1277         if (ret)
1278                 return ret;
1279
1280         /*
1281          * We don't want the CS line to be toggled between each byte/word
1282          * transfer to the NAND. The only way to guarantee that is to have the
1283          * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1284          *
1285          * NCS_WR_PULSE = NWE_CYCLE
1286          */
1287         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1288                                           ncycles);
1289         if (ret)
1290                 return ret;
1291
1292         /*
1293          * As for the write setup timing, the read hold timing depends on the
1294          * operation done on the NAND:
1295          *
1296          * NRD_HOLD = max(tREH, tRHOH)
1297          */
1298         timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1299         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1300         totalcycles = ncycles;
1301
1302         /*
1303          * TDF = tRHZ - NRD_HOLD
1304          */
1305         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1306         ncycles -= totalcycles;
1307
1308         /*
1309          * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1310          * we might end up with a config that does not fit in the TDF field.
1311          * Just take the max value in this case and hope that the NAND is more
1312          * tolerant than advertised.
1313          */
1314         if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1315                 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1316         else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1317                 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1318
1319         smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1320                          ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1321
1322         /*
1323          * Read pulse timing directly matches tRP:
1324          *
1325          * NRD_PULSE = tRP
1326          */
1327         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1328         totalcycles += ncycles;
1329         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1330                                           ncycles);
1331         if (ret)
1332                 return ret;
1333
1334         /*
1335          * The write cycle timing is directly matching tWC, but is also
1336          * dependent on the setup and hold timings we calculated earlier,
1337          * which gives:
1338          *
1339          * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1340          *
1341          * NRD_SETUP is always 0.
1342          */
1343         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1344         ncycles = max(totalcycles, ncycles);
1345         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1346                                           ncycles);
1347         if (ret)
1348                 return ret;
1349
1350         /*
1351          * We don't want the CS line to be toggled between each byte/word
1352          * transfer from the NAND. The only way to guarantee that is to have
1353          * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1354          *
1355          * NCS_RD_PULSE = NRD_CYCLE
1356          */
1357         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1358                                           ncycles);
1359         if (ret)
1360                 return ret;
1361
1362         /* Txxx timings are directly matching tXXX ones. */
1363         ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1364         ret = atmel_smc_cs_conf_set_timing(smcconf,
1365                                            ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1366                                            ncycles);
1367         if (ret)
1368                 return ret;
1369
1370         ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1371         ret = atmel_smc_cs_conf_set_timing(smcconf,
1372                                            ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1373                                            ncycles);
1374         /*
1375          * Version 4 of the ONFI spec mandates that tADL be at least 400
1376          * nanoseconds, but, depending on the master clock rate, 400 ns may not
1377          * fit in the tADL field of the SMC reg. We need to relax the check and
1378          * accept the -ERANGE return code.
1379          *
1380          * Note that previous versions of the ONFI spec had a lower tADL_min
1381          * (100 or 200 ns). It's not clear why this timing constraint got
1382          * increased but it seems most NANDs are fine with values lower than
1383          * 400ns, so we should be safe.
1384          */
1385         if (ret && ret != -ERANGE)
1386                 return ret;
1387
1388         ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1389         ret = atmel_smc_cs_conf_set_timing(smcconf,
1390                                            ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1391                                            ncycles);
1392         if (ret)
1393                 return ret;
1394
1395         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1396         ret = atmel_smc_cs_conf_set_timing(smcconf,
1397                                            ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1398                                            ncycles);
1399         if (ret)
1400                 return ret;
1401
1402         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1403         ret = atmel_smc_cs_conf_set_timing(smcconf,
1404                                            ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1405                                            ncycles);
1406         if (ret)
1407                 return ret;
1408
1409         /* Attach the CS line to the NFC logic. */
1410         smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1411
1412         /* Set the appropriate data bus width. */
1413         if (nand->base.options & NAND_BUSWIDTH_16)
1414                 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1415
1416         /* Operate in NRD/NWE READ/WRITEMODE. */
1417         smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1418                          ATMEL_SMC_MODE_WRITEMODE_NWE;
1419
1420         return 0;
1421 }
1422
1423 static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
1424                                         int csline,
1425                                         const struct nand_data_interface *conf)
1426 {
1427         struct atmel_nand_controller *nc;
1428         struct atmel_smc_cs_conf smcconf;
1429         struct atmel_nand_cs *cs;
1430         int ret;
1431
1432         nc = to_nand_controller(nand->base.controller);
1433
1434         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1435         if (ret)
1436                 return ret;
1437
1438         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1439                 return 0;
1440
1441         cs = &nand->cs[csline];
1442         cs->smcconf = smcconf;
1443         atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1444
1445         return 0;
1446 }
1447
1448 static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
1449                                         int csline,
1450                                         const struct nand_data_interface *conf)
1451 {
1452         struct atmel_hsmc_nand_controller *nc;
1453         struct atmel_smc_cs_conf smcconf;
1454         struct atmel_nand_cs *cs;
1455         int ret;
1456
1457         nc = to_hsmc_nand_controller(nand->base.controller);
1458
1459         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1460         if (ret)
1461                 return ret;
1462
1463         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1464                 return 0;
1465
1466         cs = &nand->cs[csline];
1467         cs->smcconf = smcconf;
1468
1469         if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1470                 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1471
1472         atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1473                                  &cs->smcconf);
1474
1475         return 0;
1476 }
1477
1478 static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
1479                                         const struct nand_data_interface *conf)
1480 {
1481         struct nand_chip *chip = mtd_to_nand(mtd);
1482         struct atmel_nand *nand = to_atmel_nand(chip);
1483         struct atmel_nand_controller *nc;
1484
1485         nc = to_nand_controller(nand->base.controller);
1486
1487         if (csline >= nand->numcs ||
1488             (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1489                 return -EINVAL;
1490
1491         return nc->caps->ops->setup_data_interface(nand, csline, conf);
1492 }
1493
1494 static void atmel_nand_init(struct atmel_nand_controller *nc,
1495                             struct atmel_nand *nand)
1496 {
1497         struct nand_chip *chip = &nand->base;
1498         struct mtd_info *mtd = nand_to_mtd(chip);
1499
1500         mtd->dev.parent = nc->dev;
1501         nand->base.controller = &nc->base;
1502
1503         chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1504         chip->read_byte = atmel_nand_read_byte;
1505         chip->read_word = atmel_nand_read_word;
1506         chip->write_byte = atmel_nand_write_byte;
1507         chip->read_buf = atmel_nand_read_buf;
1508         chip->write_buf = atmel_nand_write_buf;
1509         chip->select_chip = atmel_nand_select_chip;
1510
1511         if (nc->mck && nc->caps->ops->setup_data_interface)
1512                 chip->setup_data_interface = atmel_nand_setup_data_interface;
1513
1514         /* Some NANDs require a longer delay than the default one (20us). */
1515         chip->chip_delay = 40;
1516
1517         /*
1518          * Use a bounce buffer when the buffer passed by the MTD user is not
1519          * suitable for DMA.
1520          */
1521         if (nc->dmac)
1522                 chip->options |= NAND_USE_BOUNCE_BUFFER;
1523
1524         /* Default to HW ECC if pmecc is available. */
1525         if (nc->pmecc)
1526                 chip->ecc.mode = NAND_ECC_HW;
1527 }
1528
1529 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1530                                 struct atmel_nand *nand)
1531 {
1532         struct nand_chip *chip = &nand->base;
1533         struct atmel_smc_nand_controller *smc_nc;
1534         int i;
1535
1536         atmel_nand_init(nc, nand);
1537
1538         smc_nc = to_smc_nand_controller(chip->controller);
1539         if (!smc_nc->matrix)
1540                 return;
1541
1542         /* Attach the CS to the NAND Flash logic. */
1543         for (i = 0; i < nand->numcs; i++)
1544                 regmap_update_bits(smc_nc->matrix, smc_nc->ebi_csa_offs,
1545                                    BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1546 }
1547
1548 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1549                                  struct atmel_nand *nand)
1550 {
1551         struct nand_chip *chip = &nand->base;
1552
1553         atmel_nand_init(nc, nand);
1554
1555         /* Overload some methods for the HSMC controller. */
1556         chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1557         chip->select_chip = atmel_hsmc_nand_select_chip;
1558 }
1559
1560 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
1561 {
1562         struct nand_chip *chip = &nand->base;
1563         struct mtd_info *mtd = nand_to_mtd(chip);
1564         int ret;
1565
1566         ret = mtd_device_unregister(mtd);
1567         if (ret)
1568                 return ret;
1569
1570         nand_cleanup(chip);
1571         list_del(&nand->node);
1572
1573         return 0;
1574 }
1575
1576 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1577                                             struct device_node *np,
1578                                             int reg_cells)
1579 {
1580         struct atmel_nand *nand;
1581         struct gpio_desc *gpio;
1582         int numcs, ret, i;
1583
1584         numcs = of_property_count_elems_of_size(np, "reg",
1585                                                 reg_cells * sizeof(u32));
1586         if (numcs < 1) {
1587                 dev_err(nc->dev, "Missing or invalid reg property\n");
1588                 return ERR_PTR(-EINVAL);
1589         }
1590
1591         nand = devm_kzalloc(nc->dev,
1592                             sizeof(*nand) + (numcs * sizeof(*nand->cs)),
1593                             GFP_KERNEL);
1594         if (!nand) {
1595                 dev_err(nc->dev, "Failed to allocate NAND object\n");
1596                 return ERR_PTR(-ENOMEM);
1597         }
1598
1599         nand->numcs = numcs;
1600
1601         gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "det", 0,
1602                                                       &np->fwnode, GPIOD_IN,
1603                                                       "nand-det");
1604         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1605                 dev_err(nc->dev,
1606                         "Failed to get detect gpio (err = %ld)\n",
1607                         PTR_ERR(gpio));
1608                 return ERR_CAST(gpio);
1609         }
1610
1611         if (!IS_ERR(gpio))
1612                 nand->cdgpio = gpio;
1613
1614         for (i = 0; i < numcs; i++) {
1615                 struct resource res;
1616                 u32 val;
1617
1618                 ret = of_address_to_resource(np, 0, &res);
1619                 if (ret) {
1620                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1621                                 ret);
1622                         return ERR_PTR(ret);
1623                 }
1624
1625                 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1626                                                  &val);
1627                 if (ret) {
1628                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1629                                 ret);
1630                         return ERR_PTR(ret);
1631                 }
1632
1633                 nand->cs[i].id = val;
1634
1635                 nand->cs[i].io.dma = res.start;
1636                 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1637                 if (IS_ERR(nand->cs[i].io.virt))
1638                         return ERR_CAST(nand->cs[i].io.virt);
1639
1640                 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1641                         if (val > ATMEL_NFC_MAX_RB_ID)
1642                                 return ERR_PTR(-EINVAL);
1643
1644                         nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1645                         nand->cs[i].rb.id = val;
1646                 } else {
1647                         gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev,
1648                                                         "rb", i, &np->fwnode,
1649                                                         GPIOD_IN, "nand-rb");
1650                         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1651                                 dev_err(nc->dev,
1652                                         "Failed to get R/B gpio (err = %ld)\n",
1653                                         PTR_ERR(gpio));
1654                                 return ERR_CAST(gpio);
1655                         }
1656
1657                         if (!IS_ERR(gpio)) {
1658                                 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1659                                 nand->cs[i].rb.gpio = gpio;
1660                         }
1661                 }
1662
1663                 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "cs",
1664                                                               i, &np->fwnode,
1665                                                               GPIOD_OUT_HIGH,
1666                                                               "nand-cs");
1667                 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1668                         dev_err(nc->dev,
1669                                 "Failed to get CS gpio (err = %ld)\n",
1670                                 PTR_ERR(gpio));
1671                         return ERR_CAST(gpio);
1672                 }
1673
1674                 if (!IS_ERR(gpio))
1675                         nand->cs[i].csgpio = gpio;
1676         }
1677
1678         nand_set_flash_node(&nand->base, np);
1679
1680         return nand;
1681 }
1682
1683 static int
1684 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1685                                struct atmel_nand *nand)
1686 {
1687         struct nand_chip *chip = &nand->base;
1688         struct mtd_info *mtd = nand_to_mtd(chip);
1689         int ret;
1690
1691         /* No card inserted, skip this NAND. */
1692         if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1693                 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1694                 return 0;
1695         }
1696
1697         nc->caps->ops->nand_init(nc, nand);
1698
1699         ret = nand_scan(chip, nand->numcs);
1700         if (ret) {
1701                 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1702                 return ret;
1703         }
1704
1705         ret = mtd_device_register(mtd, NULL, 0);
1706         if (ret) {
1707                 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1708                 nand_cleanup(chip);
1709                 return ret;
1710         }
1711
1712         list_add_tail(&nand->node, &nc->chips);
1713
1714         return 0;
1715 }
1716
1717 static int
1718 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1719 {
1720         struct atmel_nand *nand, *tmp;
1721         int ret;
1722
1723         list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1724                 ret = atmel_nand_controller_remove_nand(nand);
1725                 if (ret)
1726                         return ret;
1727         }
1728
1729         return 0;
1730 }
1731
1732 static int
1733 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1734 {
1735         struct device *dev = nc->dev;
1736         struct platform_device *pdev = to_platform_device(dev);
1737         struct atmel_nand *nand;
1738         struct gpio_desc *gpio;
1739         struct resource *res;
1740
1741         /*
1742          * Legacy bindings only allow connecting a single NAND with a unique CS
1743          * line to the controller.
1744          */
1745         nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1746                             GFP_KERNEL);
1747         if (!nand)
1748                 return -ENOMEM;
1749
1750         nand->numcs = 1;
1751
1752         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1753         nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1754         if (IS_ERR(nand->cs[0].io.virt))
1755                 return PTR_ERR(nand->cs[0].io.virt);
1756
1757         nand->cs[0].io.dma = res->start;
1758
1759         /*
1760          * The old driver was hardcoding the CS id to 3 for all sama5
1761          * controllers. Since this id is only meaningful for the sama5
1762          * controller we can safely assign this id to 3 no matter the
1763          * controller.
1764          * If one wants to connect a NAND to a different CS line, he will
1765          * have to use the new bindings.
1766          */
1767         nand->cs[0].id = 3;
1768
1769         /* R/B GPIO. */
1770         gpio = devm_gpiod_get_index_optional(dev, NULL, 0,  GPIOD_IN);
1771         if (IS_ERR(gpio)) {
1772                 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1773                         PTR_ERR(gpio));
1774                 return PTR_ERR(gpio);
1775         }
1776
1777         if (gpio) {
1778                 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1779                 nand->cs[0].rb.gpio = gpio;
1780         }
1781
1782         /* CS GPIO. */
1783         gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1784         if (IS_ERR(gpio)) {
1785                 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1786                         PTR_ERR(gpio));
1787                 return PTR_ERR(gpio);
1788         }
1789
1790         nand->cs[0].csgpio = gpio;
1791
1792         /* Card detect GPIO. */
1793         gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1794         if (IS_ERR(gpio)) {
1795                 dev_err(dev,
1796                         "Failed to get detect gpio (err = %ld)\n",
1797                         PTR_ERR(gpio));
1798                 return PTR_ERR(gpio);
1799         }
1800
1801         nand->cdgpio = gpio;
1802
1803         nand_set_flash_node(&nand->base, nc->dev->of_node);
1804
1805         return atmel_nand_controller_add_nand(nc, nand);
1806 }
1807
1808 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1809 {
1810         struct device_node *np, *nand_np;
1811         struct device *dev = nc->dev;
1812         int ret, reg_cells;
1813         u32 val;
1814
1815         /* We do not retrieve the SMC syscon when parsing old DTs. */
1816         if (nc->caps->legacy_of_bindings)
1817                 return atmel_nand_controller_legacy_add_nands(nc);
1818
1819         np = dev->of_node;
1820
1821         ret = of_property_read_u32(np, "#address-cells", &val);
1822         if (ret) {
1823                 dev_err(dev, "missing #address-cells property\n");
1824                 return ret;
1825         }
1826
1827         reg_cells = val;
1828
1829         ret = of_property_read_u32(np, "#size-cells", &val);
1830         if (ret) {
1831                 dev_err(dev, "missing #size-cells property\n");
1832                 return ret;
1833         }
1834
1835         reg_cells += val;
1836
1837         for_each_child_of_node(np, nand_np) {
1838                 struct atmel_nand *nand;
1839
1840                 nand = atmel_nand_create(nc, nand_np, reg_cells);
1841                 if (IS_ERR(nand)) {
1842                         ret = PTR_ERR(nand);
1843                         goto err;
1844                 }
1845
1846                 ret = atmel_nand_controller_add_nand(nc, nand);
1847                 if (ret)
1848                         goto err;
1849         }
1850
1851         return 0;
1852
1853 err:
1854         atmel_nand_controller_remove_nands(nc);
1855
1856         return ret;
1857 }
1858
1859 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1860 {
1861         if (nc->dmac)
1862                 dma_release_channel(nc->dmac);
1863
1864         clk_put(nc->mck);
1865 }
1866
1867 static const struct of_device_id atmel_matrix_of_ids[] = {
1868         {
1869                 .compatible = "atmel,at91sam9260-matrix",
1870                 .data = (void *)AT91SAM9260_MATRIX_EBICSA,
1871         },
1872         {
1873                 .compatible = "atmel,at91sam9261-matrix",
1874                 .data = (void *)AT91SAM9261_MATRIX_EBICSA,
1875         },
1876         {
1877                 .compatible = "atmel,at91sam9263-matrix",
1878                 .data = (void *)AT91SAM9263_MATRIX_EBI0CSA,
1879         },
1880         {
1881                 .compatible = "atmel,at91sam9rl-matrix",
1882                 .data = (void *)AT91SAM9RL_MATRIX_EBICSA,
1883         },
1884         {
1885                 .compatible = "atmel,at91sam9g45-matrix",
1886                 .data = (void *)AT91SAM9G45_MATRIX_EBICSA,
1887         },
1888         {
1889                 .compatible = "atmel,at91sam9n12-matrix",
1890                 .data = (void *)AT91SAM9N12_MATRIX_EBICSA,
1891         },
1892         {
1893                 .compatible = "atmel,at91sam9x5-matrix",
1894                 .data = (void *)AT91SAM9X5_MATRIX_EBICSA,
1895         },
1896         { /* sentinel */ },
1897 };
1898
1899 static int atmel_nand_attach_chip(struct nand_chip *chip)
1900 {
1901         struct atmel_nand_controller *nc = to_nand_controller(chip->controller);
1902         struct atmel_nand *nand = to_atmel_nand(chip);
1903         struct mtd_info *mtd = nand_to_mtd(chip);
1904         int ret;
1905
1906         ret = nc->caps->ops->ecc_init(chip);
1907         if (ret)
1908                 return ret;
1909
1910         if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1911                 /*
1912                  * We keep the MTD name unchanged to avoid breaking platforms
1913                  * where the MTD cmdline parser is used and the bootloader
1914                  * has not been updated to use the new naming scheme.
1915                  */
1916                 mtd->name = "atmel_nand";
1917         } else if (!mtd->name) {
1918                 /*
1919                  * If the new bindings are used and the bootloader has not been
1920                  * updated to pass a new mtdparts parameter on the cmdline, you
1921                  * should define the following property in your nand node:
1922                  *
1923                  *      label = "atmel_nand";
1924                  *
1925                  * This way, mtd->name will be set by the core when
1926                  * nand_set_flash_node() is called.
1927                  */
1928                 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
1929                                            "%s:nand.%d", dev_name(nc->dev),
1930                                            nand->cs[0].id);
1931                 if (!mtd->name) {
1932                         dev_err(nc->dev, "Failed to allocate mtd->name\n");
1933                         return -ENOMEM;
1934                 }
1935         }
1936
1937         return 0;
1938 }
1939
1940 static const struct nand_controller_ops atmel_nand_controller_ops = {
1941         .attach_chip = atmel_nand_attach_chip,
1942 };
1943
1944 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
1945                                 struct platform_device *pdev,
1946                                 const struct atmel_nand_controller_caps *caps)
1947 {
1948         struct device *dev = &pdev->dev;
1949         struct device_node *np = dev->of_node;
1950         int ret;
1951
1952         nand_controller_init(&nc->base);
1953         nc->base.ops = &atmel_nand_controller_ops;
1954         INIT_LIST_HEAD(&nc->chips);
1955         nc->dev = dev;
1956         nc->caps = caps;
1957
1958         platform_set_drvdata(pdev, nc);
1959
1960         nc->pmecc = devm_atmel_pmecc_get(dev);
1961         if (IS_ERR(nc->pmecc)) {
1962                 ret = PTR_ERR(nc->pmecc);
1963                 if (ret != -EPROBE_DEFER)
1964                         dev_err(dev, "Could not get PMECC object (err = %d)\n",
1965                                 ret);
1966                 return ret;
1967         }
1968
1969         if (nc->caps->has_dma && !atmel_nand_avoid_dma) {
1970                 dma_cap_mask_t mask;
1971
1972                 dma_cap_zero(mask);
1973                 dma_cap_set(DMA_MEMCPY, mask);
1974
1975                 nc->dmac = dma_request_channel(mask, NULL, NULL);
1976                 if (!nc->dmac)
1977                         dev_err(nc->dev, "Failed to request DMA channel\n");
1978         }
1979
1980         /* We do not retrieve the SMC syscon when parsing old DTs. */
1981         if (nc->caps->legacy_of_bindings)
1982                 return 0;
1983
1984         nc->mck = of_clk_get(dev->parent->of_node, 0);
1985         if (IS_ERR(nc->mck)) {
1986                 dev_err(dev, "Failed to retrieve MCK clk\n");
1987                 ret = PTR_ERR(nc->mck);
1988                 goto out_release_dma;
1989         }
1990
1991         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
1992         if (!np) {
1993                 dev_err(dev, "Missing or invalid atmel,smc property\n");
1994                 ret = -EINVAL;
1995                 goto out_release_dma;
1996         }
1997
1998         nc->smc = syscon_node_to_regmap(np);
1999         of_node_put(np);
2000         if (IS_ERR(nc->smc)) {
2001                 ret = PTR_ERR(nc->smc);
2002                 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
2003                 goto out_release_dma;
2004         }
2005
2006         return 0;
2007
2008 out_release_dma:
2009         if (nc->dmac)
2010                 dma_release_channel(nc->dmac);
2011
2012         return ret;
2013 }
2014
2015 static int
2016 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
2017 {
2018         struct device *dev = nc->base.dev;
2019         const struct of_device_id *match;
2020         struct device_node *np;
2021         int ret;
2022
2023         /* We do not retrieve the matrix syscon when parsing old DTs. */
2024         if (nc->base.caps->legacy_of_bindings)
2025                 return 0;
2026
2027         np = of_parse_phandle(dev->parent->of_node, "atmel,matrix", 0);
2028         if (!np)
2029                 return 0;
2030
2031         match = of_match_node(atmel_matrix_of_ids, np);
2032         if (!match) {
2033                 of_node_put(np);
2034                 return 0;
2035         }
2036
2037         nc->matrix = syscon_node_to_regmap(np);
2038         of_node_put(np);
2039         if (IS_ERR(nc->matrix)) {
2040                 ret = PTR_ERR(nc->matrix);
2041                 dev_err(dev, "Could not get Matrix regmap (err = %d)\n", ret);
2042                 return ret;
2043         }
2044
2045         nc->ebi_csa_offs = (uintptr_t)match->data;
2046
2047         /*
2048          * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2049          * add 4 to ->ebi_csa_offs.
2050          */
2051         if (of_device_is_compatible(dev->parent->of_node,
2052                                     "atmel,at91sam9263-ebi1"))
2053                 nc->ebi_csa_offs += 4;
2054
2055         return 0;
2056 }
2057
2058 static int
2059 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2060 {
2061         struct regmap_config regmap_conf = {
2062                 .reg_bits = 32,
2063                 .val_bits = 32,
2064                 .reg_stride = 4,
2065         };
2066
2067         struct device *dev = nc->base.dev;
2068         struct device_node *nand_np, *nfc_np;
2069         void __iomem *iomem;
2070         struct resource res;
2071         int ret;
2072
2073         nand_np = dev->of_node;
2074         nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc");
2075         if (!nfc_np) {
2076                 dev_err(dev, "Could not find device node for sama5d3-nfc\n");
2077                 return -ENODEV;
2078         }
2079
2080         nc->clk = of_clk_get(nfc_np, 0);
2081         if (IS_ERR(nc->clk)) {
2082                 ret = PTR_ERR(nc->clk);
2083                 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
2084                         ret);
2085                 goto out;
2086         }
2087
2088         ret = clk_prepare_enable(nc->clk);
2089         if (ret) {
2090                 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
2091                         ret);
2092                 goto out;
2093         }
2094
2095         nc->irq = of_irq_get(nand_np, 0);
2096         if (nc->irq <= 0) {
2097                 ret = nc->irq ?: -ENXIO;
2098                 if (ret != -EPROBE_DEFER)
2099                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2100                                 ret);
2101                 goto out;
2102         }
2103
2104         ret = of_address_to_resource(nfc_np, 0, &res);
2105         if (ret) {
2106                 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
2107                         ret);
2108                 goto out;
2109         }
2110
2111         iomem = devm_ioremap_resource(dev, &res);
2112         if (IS_ERR(iomem)) {
2113                 ret = PTR_ERR(iomem);
2114                 goto out;
2115         }
2116
2117         regmap_conf.name = "nfc-io";
2118         regmap_conf.max_register = resource_size(&res) - 4;
2119         nc->io = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2120         if (IS_ERR(nc->io)) {
2121                 ret = PTR_ERR(nc->io);
2122                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2123                         ret);
2124                 goto out;
2125         }
2126
2127         ret = of_address_to_resource(nfc_np, 1, &res);
2128         if (ret) {
2129                 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
2130                         ret);
2131                 goto out;
2132         }
2133
2134         iomem = devm_ioremap_resource(dev, &res);
2135         if (IS_ERR(iomem)) {
2136                 ret = PTR_ERR(iomem);
2137                 goto out;
2138         }
2139
2140         regmap_conf.name = "smc";
2141         regmap_conf.max_register = resource_size(&res) - 4;
2142         nc->base.smc = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2143         if (IS_ERR(nc->base.smc)) {
2144                 ret = PTR_ERR(nc->base.smc);
2145                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2146                         ret);
2147                 goto out;
2148         }
2149
2150         ret = of_address_to_resource(nfc_np, 2, &res);
2151         if (ret) {
2152                 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
2153                         ret);
2154                 goto out;
2155         }
2156
2157         nc->sram.virt = devm_ioremap_resource(dev, &res);
2158         if (IS_ERR(nc->sram.virt)) {
2159                 ret = PTR_ERR(nc->sram.virt);
2160                 goto out;
2161         }
2162
2163         nc->sram.dma = res.start;
2164
2165 out:
2166         of_node_put(nfc_np);
2167
2168         return ret;
2169 }
2170
2171 static int
2172 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2173 {
2174         struct device *dev = nc->base.dev;
2175         struct device_node *np;
2176         int ret;
2177
2178         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2179         if (!np) {
2180                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2181                 return -EINVAL;
2182         }
2183
2184         nc->hsmc_layout = atmel_hsmc_get_reg_layout(np);
2185
2186         nc->irq = of_irq_get(np, 0);
2187         of_node_put(np);
2188         if (nc->irq <= 0) {
2189                 ret = nc->irq ?: -ENXIO;
2190                 if (ret != -EPROBE_DEFER)
2191                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2192                                 ret);
2193                 return ret;
2194         }
2195
2196         np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
2197         if (!np) {
2198                 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
2199                 return -EINVAL;
2200         }
2201
2202         nc->io = syscon_node_to_regmap(np);
2203         of_node_put(np);
2204         if (IS_ERR(nc->io)) {
2205                 ret = PTR_ERR(nc->io);
2206                 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
2207                 return ret;
2208         }
2209
2210         nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2211                                          "atmel,nfc-sram", 0);
2212         if (!nc->sram.pool) {
2213                 dev_err(nc->base.dev, "Missing SRAM\n");
2214                 return -ENOMEM;
2215         }
2216
2217         nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool,
2218                                                            ATMEL_NFC_SRAM_SIZE,
2219                                                            &nc->sram.dma);
2220         if (!nc->sram.virt) {
2221                 dev_err(nc->base.dev,
2222                         "Could not allocate memory from the NFC SRAM pool\n");
2223                 return -ENOMEM;
2224         }
2225
2226         return 0;
2227 }
2228
2229 static int
2230 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2231 {
2232         struct atmel_hsmc_nand_controller *hsmc_nc;
2233         int ret;
2234
2235         ret = atmel_nand_controller_remove_nands(nc);
2236         if (ret)
2237                 return ret;
2238
2239         hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2240         if (hsmc_nc->sram.pool)
2241                 gen_pool_free(hsmc_nc->sram.pool,
2242                               (unsigned long)hsmc_nc->sram.virt,
2243                               ATMEL_NFC_SRAM_SIZE);
2244
2245         if (hsmc_nc->clk) {
2246                 clk_disable_unprepare(hsmc_nc->clk);
2247                 clk_put(hsmc_nc->clk);
2248         }
2249
2250         atmel_nand_controller_cleanup(nc);
2251
2252         return 0;
2253 }
2254
2255 static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
2256                                 const struct atmel_nand_controller_caps *caps)
2257 {
2258         struct device *dev = &pdev->dev;
2259         struct atmel_hsmc_nand_controller *nc;
2260         int ret;
2261
2262         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2263         if (!nc)
2264                 return -ENOMEM;
2265
2266         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2267         if (ret)
2268                 return ret;
2269
2270         if (caps->legacy_of_bindings)
2271                 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2272         else
2273                 ret = atmel_hsmc_nand_controller_init(nc);
2274
2275         if (ret)
2276                 return ret;
2277
2278         /* Make sure all irqs are masked before registering our IRQ handler. */
2279         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2280         ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2281                                IRQF_SHARED, "nfc", nc);
2282         if (ret) {
2283                 dev_err(dev,
2284                         "Could not get register NFC interrupt handler (err = %d)\n",
2285                         ret);
2286                 goto err;
2287         }
2288
2289         /* Initial NFC configuration. */
2290         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2291                      ATMEL_HSMC_NFC_CFG_DTO_MAX);
2292
2293         ret = atmel_nand_controller_add_nands(&nc->base);
2294         if (ret)
2295                 goto err;
2296
2297         return 0;
2298
2299 err:
2300         atmel_hsmc_nand_controller_remove(&nc->base);
2301
2302         return ret;
2303 }
2304
2305 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2306         .probe = atmel_hsmc_nand_controller_probe,
2307         .remove = atmel_hsmc_nand_controller_remove,
2308         .ecc_init = atmel_hsmc_nand_ecc_init,
2309         .nand_init = atmel_hsmc_nand_init,
2310         .setup_data_interface = atmel_hsmc_nand_setup_data_interface,
2311 };
2312
2313 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2314         .has_dma = true,
2315         .ale_offs = BIT(21),
2316         .cle_offs = BIT(22),
2317         .ops = &atmel_hsmc_nc_ops,
2318 };
2319
2320 /* Only used to parse old bindings. */
2321 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
2322         .has_dma = true,
2323         .ale_offs = BIT(21),
2324         .cle_offs = BIT(22),
2325         .ops = &atmel_hsmc_nc_ops,
2326         .legacy_of_bindings = true,
2327 };
2328
2329 static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2330                                 const struct atmel_nand_controller_caps *caps)
2331 {
2332         struct device *dev = &pdev->dev;
2333         struct atmel_smc_nand_controller *nc;
2334         int ret;
2335
2336         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2337         if (!nc)
2338                 return -ENOMEM;
2339
2340         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2341         if (ret)
2342                 return ret;
2343
2344         ret = atmel_smc_nand_controller_init(nc);
2345         if (ret)
2346                 return ret;
2347
2348         return atmel_nand_controller_add_nands(&nc->base);
2349 }
2350
2351 static int
2352 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2353 {
2354         int ret;
2355
2356         ret = atmel_nand_controller_remove_nands(nc);
2357         if (ret)
2358                 return ret;
2359
2360         atmel_nand_controller_cleanup(nc);
2361
2362         return 0;
2363 }
2364
2365 /*
2366  * The SMC reg layout of at91rm9200 is completely different which prevents us
2367  * from re-using atmel_smc_nand_setup_data_interface() for the
2368  * ->setup_data_interface() hook.
2369  * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2370  * ->setup_data_interface() unassigned.
2371  */
2372 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2373         .probe = atmel_smc_nand_controller_probe,
2374         .remove = atmel_smc_nand_controller_remove,
2375         .ecc_init = atmel_nand_ecc_init,
2376         .nand_init = atmel_smc_nand_init,
2377 };
2378
2379 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2380         .ale_offs = BIT(21),
2381         .cle_offs = BIT(22),
2382         .ops = &at91rm9200_nc_ops,
2383 };
2384
2385 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2386         .probe = atmel_smc_nand_controller_probe,
2387         .remove = atmel_smc_nand_controller_remove,
2388         .ecc_init = atmel_nand_ecc_init,
2389         .nand_init = atmel_smc_nand_init,
2390         .setup_data_interface = atmel_smc_nand_setup_data_interface,
2391 };
2392
2393 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2394         .ale_offs = BIT(21),
2395         .cle_offs = BIT(22),
2396         .ops = &atmel_smc_nc_ops,
2397 };
2398
2399 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2400         .ale_offs = BIT(22),
2401         .cle_offs = BIT(21),
2402         .ops = &atmel_smc_nc_ops,
2403 };
2404
2405 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2406         .has_dma = true,
2407         .ale_offs = BIT(21),
2408         .cle_offs = BIT(22),
2409         .ops = &atmel_smc_nc_ops,
2410 };
2411
2412 /* Only used to parse old bindings. */
2413 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2414         .ale_offs = BIT(21),
2415         .cle_offs = BIT(22),
2416         .ops = &atmel_smc_nc_ops,
2417         .legacy_of_bindings = true,
2418 };
2419
2420 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2421         .ale_offs = BIT(22),
2422         .cle_offs = BIT(21),
2423         .ops = &atmel_smc_nc_ops,
2424         .legacy_of_bindings = true,
2425 };
2426
2427 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2428         .has_dma = true,
2429         .ale_offs = BIT(21),
2430         .cle_offs = BIT(22),
2431         .ops = &atmel_smc_nc_ops,
2432         .legacy_of_bindings = true,
2433 };
2434
2435 static const struct of_device_id atmel_nand_controller_of_ids[] = {
2436         {
2437                 .compatible = "atmel,at91rm9200-nand-controller",
2438                 .data = &atmel_rm9200_nc_caps,
2439         },
2440         {
2441                 .compatible = "atmel,at91sam9260-nand-controller",
2442                 .data = &atmel_sam9260_nc_caps,
2443         },
2444         {
2445                 .compatible = "atmel,at91sam9261-nand-controller",
2446                 .data = &atmel_sam9261_nc_caps,
2447         },
2448         {
2449                 .compatible = "atmel,at91sam9g45-nand-controller",
2450                 .data = &atmel_sam9g45_nc_caps,
2451         },
2452         {
2453                 .compatible = "atmel,sama5d3-nand-controller",
2454                 .data = &atmel_sama5_nc_caps,
2455         },
2456         /* Support for old/deprecated bindings: */
2457         {
2458                 .compatible = "atmel,at91rm9200-nand",
2459                 .data = &atmel_rm9200_nand_caps,
2460         },
2461         {
2462                 .compatible = "atmel,sama5d4-nand",
2463                 .data = &atmel_rm9200_nand_caps,
2464         },
2465         {
2466                 .compatible = "atmel,sama5d2-nand",
2467                 .data = &atmel_rm9200_nand_caps,
2468         },
2469         { /* sentinel */ },
2470 };
2471 MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2472
2473 static int atmel_nand_controller_probe(struct platform_device *pdev)
2474 {
2475         const struct atmel_nand_controller_caps *caps;
2476
2477         if (pdev->id_entry)
2478                 caps = (void *)pdev->id_entry->driver_data;
2479         else
2480                 caps = of_device_get_match_data(&pdev->dev);
2481
2482         if (!caps) {
2483                 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2484                 return -EINVAL;
2485         }
2486
2487         if (caps->legacy_of_bindings) {
2488                 struct device_node *nfc_node;
2489                 u32 ale_offs = 21;
2490
2491                 /*
2492                  * If we are parsing legacy DT props and the DT contains a
2493                  * valid NFC node, forward the request to the sama5 logic.
2494                  */
2495                 nfc_node = of_get_compatible_child(pdev->dev.of_node,
2496                                                    "atmel,sama5d3-nfc");
2497                 if (nfc_node) {
2498                         caps = &atmel_sama5_nand_caps;
2499                         of_node_put(nfc_node);
2500                 }
2501
2502                 /*
2503                  * Even if the compatible says we are dealing with an
2504                  * at91rm9200 controller, the atmel,nand-has-dma specify that
2505                  * this controller supports DMA, which means we are in fact
2506                  * dealing with an at91sam9g45+ controller.
2507                  */
2508                 if (!caps->has_dma &&
2509                     of_property_read_bool(pdev->dev.of_node,
2510                                           "atmel,nand-has-dma"))
2511                         caps = &atmel_sam9g45_nand_caps;
2512
2513                 /*
2514                  * All SoCs except the at91sam9261 are assigning ALE to A21 and
2515                  * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2516                  * actually dealing with an at91sam9261 controller.
2517                  */
2518                 of_property_read_u32(pdev->dev.of_node,
2519                                      "atmel,nand-addr-offset", &ale_offs);
2520                 if (ale_offs != 21)
2521                         caps = &atmel_sam9261_nand_caps;
2522         }
2523
2524         return caps->ops->probe(pdev, caps);
2525 }
2526
2527 static int atmel_nand_controller_remove(struct platform_device *pdev)
2528 {
2529         struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2530
2531         return nc->caps->ops->remove(nc);
2532 }
2533
2534 static __maybe_unused int atmel_nand_controller_resume(struct device *dev)
2535 {
2536         struct atmel_nand_controller *nc = dev_get_drvdata(dev);
2537         struct atmel_nand *nand;
2538
2539         if (nc->pmecc)
2540                 atmel_pmecc_reset(nc->pmecc);
2541
2542         list_for_each_entry(nand, &nc->chips, node) {
2543                 int i;
2544
2545                 for (i = 0; i < nand->numcs; i++)
2546                         nand_reset(&nand->base, i);
2547         }
2548
2549         return 0;
2550 }
2551
2552 static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL,
2553                          atmel_nand_controller_resume);
2554
2555 static struct platform_driver atmel_nand_controller_driver = {
2556         .driver = {
2557                 .name = "atmel-nand-controller",
2558                 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2559                 .pm = &atmel_nand_controller_pm_ops,
2560         },
2561         .probe = atmel_nand_controller_probe,
2562         .remove = atmel_nand_controller_remove,
2563 };
2564 module_platform_driver(atmel_nand_controller_driver);
2565
2566 MODULE_LICENSE("GPL");
2567 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2568 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2569 MODULE_ALIAS("platform:atmel-nand-controller");