drivers/mtd/nand/raw/atmel/nand-controller.c

   1 /*
   2  * Copyright 2017 ATMEL
   3  * Copyright 2017 Free Electrons
   4  *
   5  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
   6  *
   7  * Derived from the atmel_nand.c driver which contained the following
   8  * copyrights:
   9  *
  10  *   Copyright 2003 Rick Bronson
  11  *
  12  *   Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
  13  *      Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
  14  *
  15  *   Derived from drivers/mtd/spia.c (removed in v3.8)
  16  *      Copyright 2000 Steven J. Hill (sjhill@cotw.com)
  17  *
  18  *
  19  *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  20  *      Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
  21  *
  22  *   Derived from Das U-Boot source code
  23  *      (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  24  *      Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  25  *
  26  *   Add Programmable Multibit ECC support for various AT91 SoC
  27  *      Copyright 2012 ATMEL, Hong Xu
  28  *
  29  *   Add Nand Flash Controller support for SAMA5 SoC
  30  *      Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
  31  *
  32  * This program is free software; you can redistribute it and/or modify
  33  * it under the terms of the GNU General Public License version 2 as
  34  * published by the Free Software Foundation.
  35  *
  36  * A few words about the naming convention in this file. This convention
  37  * applies to structure and function names.
  38  *
  39  * Prefixes:
  40  *
  41  * - atmel_nand_: all generic structures/functions
  42  * - atmel_smc_nand_: all structures/functions specific to the SMC interface
  43  *                    (at91sam9 and avr32 SoCs)
  44  * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
  45  *                     (sama5 SoCs and later)
  46  * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
  47  *               that is available in the HSMC block
  48  * - <soc>_nand_: all SoC specific structures/functions
  49  */
  50
  51 #include <linux/clk.h>
  52 #include <linux/dma-mapping.h>
  53 #include <linux/dmaengine.h>
  54 #include <linux/genalloc.h>
  55 #include <linux/gpio/consumer.h>
  56 #include <linux/interrupt.h>
  57 #include <linux/mfd/syscon.h>
  58 #include <linux/mfd/syscon/atmel-matrix.h>
  59 #include <linux/mfd/syscon/atmel-smc.h>
  60 #include <linux/module.h>
  61 #include <linux/mtd/rawnand.h>
  62 #include <linux/of_address.h>
  63 #include <linux/of_irq.h>
  64 #include <linux/of_platform.h>
  65 #include <linux/iopoll.h>
  66 #include <linux/platform_device.h>
  67 #include <linux/regmap.h>
  68
  69 #include "pmecc.h"
  70
  71 #define ATMEL_HSMC_NFC_CFG                      0x0
  72 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)         (((x) / 4) << 24)
  73 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK       GENMASK(30, 24)
  74 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul)        (((cyc) << 16) | ((mul) << 20))
  75 #define ATMEL_HSMC_NFC_CFG_DTO_MAX              GENMASK(22, 16)
  76 #define ATMEL_HSMC_NFC_CFG_RBEDGE               BIT(13)
  77 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE         BIT(12)
  78 #define ATMEL_HSMC_NFC_CFG_RSPARE               BIT(9)
  79 #define ATMEL_HSMC_NFC_CFG_WSPARE               BIT(8)
  80 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK        GENMASK(2, 0)
  81 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x)          (fls((x) / 512) - 1)
  82
  83 #define ATMEL_HSMC_NFC_CTRL                     0x4
  84 #define ATMEL_HSMC_NFC_CTRL_EN                  BIT(0)
  85 #define ATMEL_HSMC_NFC_CTRL_DIS                 BIT(1)
  86
  87 #define ATMEL_HSMC_NFC_SR                       0x8
  88 #define ATMEL_HSMC_NFC_IER                      0xc
  89 #define ATMEL_HSMC_NFC_IDR                      0x10
  90 #define ATMEL_HSMC_NFC_IMR                      0x14
  91 #define ATMEL_HSMC_NFC_SR_ENABLED               BIT(1)
  92 #define ATMEL_HSMC_NFC_SR_RB_RISE               BIT(4)
  93 #define ATMEL_HSMC_NFC_SR_RB_FALL               BIT(5)
  94 #define ATMEL_HSMC_NFC_SR_BUSY                  BIT(8)
  95 #define ATMEL_HSMC_NFC_SR_WR                    BIT(11)
  96 #define ATMEL_HSMC_NFC_SR_CSID                  GENMASK(14, 12)
  97 #define ATMEL_HSMC_NFC_SR_XFRDONE               BIT(16)
  98 #define ATMEL_HSMC_NFC_SR_CMDDONE               BIT(17)
  99 #define ATMEL_HSMC_NFC_SR_DTOE                  BIT(20)
 100 #define ATMEL_HSMC_NFC_SR_UNDEF                 BIT(21)
 101 #define ATMEL_HSMC_NFC_SR_AWB                   BIT(22)
 102 #define ATMEL_HSMC_NFC_SR_NFCASE                BIT(23)
 103 #define ATMEL_HSMC_NFC_SR_ERRORS                (ATMEL_HSMC_NFC_SR_DTOE | \
 104                                                  ATMEL_HSMC_NFC_SR_UNDEF | \
 105                                                  ATMEL_HSMC_NFC_SR_AWB | \
 106                                                  ATMEL_HSMC_NFC_SR_NFCASE)
 107 #define ATMEL_HSMC_NFC_SR_RBEDGE(x)             BIT((x) + 24)
 108
 109 #define ATMEL_HSMC_NFC_ADDR                     0x18
 110 #define ATMEL_HSMC_NFC_BANK                     0x1c
 111
 112 #define ATMEL_NFC_MAX_RB_ID                     7
 113
 114 #define ATMEL_NFC_SRAM_SIZE                     0x2400
 115
 116 #define ATMEL_NFC_CMD(pos, cmd)                 ((cmd) << (((pos) * 8) + 2))
 117 #define ATMEL_NFC_VCMD2                         BIT(18)
 118 #define ATMEL_NFC_ACYCLE(naddrs)                ((naddrs) << 19)
 119 #define ATMEL_NFC_CSID(cs)                      ((cs) << 22)
 120 #define ATMEL_NFC_DATAEN                        BIT(25)
 121 #define ATMEL_NFC_NFCWR                         BIT(26)
 122
 123 #define ATMEL_NFC_MAX_ADDR_CYCLES               5
 124
 125 #define ATMEL_NAND_ALE_OFFSET                   BIT(21)
 126 #define ATMEL_NAND_CLE_OFFSET                   BIT(22)
 127
 128 #define DEFAULT_TIMEOUT_MS                      1000
 129 #define MIN_DMA_LEN                             128
 130
 131 static bool atmel_nand_avoid_dma __read_mostly;
 132
 133 MODULE_PARM_DESC(avoiddma, "Avoid using DMA");
 134 module_param_named(avoiddma, atmel_nand_avoid_dma, bool, 0400);
 135
 136 enum atmel_nand_rb_type {
 137         ATMEL_NAND_NO_RB,
 138         ATMEL_NAND_NATIVE_RB,
 139         ATMEL_NAND_GPIO_RB,
 140 };
 141
 142 struct atmel_nand_rb {
 143         enum atmel_nand_rb_type type;
 144         union {
 145                 struct gpio_desc *gpio;
 146                 int id;
 147         };
 148 };
 149
 150 struct atmel_nand_cs {
 151         int id;
 152         struct atmel_nand_rb rb;
 153         struct gpio_desc *csgpio;
 154         struct {
 155                 void __iomem *virt;
 156                 dma_addr_t dma;
 157         } io;
 158
 159         struct atmel_smc_cs_conf smcconf;
 160 };
 161
 162 struct atmel_nand {
 163         struct list_head node;
 164         struct device *dev;
 165         struct nand_chip base;
 166         struct atmel_nand_cs *activecs;
 167         struct atmel_pmecc_user *pmecc;
 168         struct gpio_desc *cdgpio;
 169         int numcs;
 170         struct atmel_nand_cs cs[];
 171 };
 172
 173 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
 174 {
 175         return container_of(chip, struct atmel_nand, base);
 176 }
 177
 178 enum atmel_nfc_data_xfer {
 179         ATMEL_NFC_NO_DATA,
 180         ATMEL_NFC_READ_DATA,
 181         ATMEL_NFC_WRITE_DATA,
 182 };
 183
 184 struct atmel_nfc_op {
 185         u8 cs;
 186         u8 ncmds;
 187         u8 cmds[2];
 188         u8 naddrs;
 189         u8 addrs[5];
 190         enum atmel_nfc_data_xfer data;
 191         u32 wait;
 192         u32 errors;
 193 };
 194
 195 struct atmel_nand_controller;
 196 struct atmel_nand_controller_caps;
 197
 198 struct atmel_nand_controller_ops {
 199         int (*probe)(struct platform_device *pdev,
 200                      const struct atmel_nand_controller_caps *caps);
 201         int (*remove)(struct atmel_nand_controller *nc);
 202         void (*nand_init)(struct atmel_nand_controller *nc,
 203                           struct atmel_nand *nand);
 204         int (*ecc_init)(struct nand_chip *chip);
 205         int (*setup_data_interface)(struct atmel_nand *nand, int csline,
 206                                     const struct nand_data_interface *conf);
 207 };
 208
 209 struct atmel_nand_controller_caps {
 210         bool has_dma;
 211         bool legacy_of_bindings;
 212         u32 ale_offs;
 213         u32 cle_offs;
 214         const struct atmel_nand_controller_ops *ops;
 215 };
 216
 217 struct atmel_nand_controller {
 218         struct nand_controller base;
 219         const struct atmel_nand_controller_caps *caps;
 220         struct device *dev;
 221         struct regmap *smc;
 222         struct dma_chan *dmac;
 223         struct atmel_pmecc *pmecc;
 224         struct list_head chips;
 225         struct clk *mck;
 226 };
 227
 228 static inline struct atmel_nand_controller *
 229 to_nand_controller(struct nand_controller *ctl)
 230 {
 231         return container_of(ctl, struct atmel_nand_controller, base);
 232 }
 233
 234 struct atmel_smc_nand_controller {
 235         struct atmel_nand_controller base;
 236         struct regmap *matrix;
 237         unsigned int ebi_csa_offs;
 238 };
 239
 240 static inline struct atmel_smc_nand_controller *
 241 to_smc_nand_controller(struct nand_controller *ctl)
 242 {
 243         return container_of(to_nand_controller(ctl),
 244                             struct atmel_smc_nand_controller, base);
 245 }
 246
 247 struct atmel_hsmc_nand_controller {
 248         struct atmel_nand_controller base;
 249         struct {
 250                 struct gen_pool *pool;
 251                 void __iomem *virt;
 252                 dma_addr_t dma;
 253         } sram;
 254         const struct atmel_hsmc_reg_layout *hsmc_layout;
 255         struct regmap *io;
 256         struct atmel_nfc_op op;
 257         struct completion complete;
 258         int irq;
 259
 260         /* Only used when instantiating from legacy DT bindings. */
 261         struct clk *clk;
 262 };
 263
 264 static inline struct atmel_hsmc_nand_controller *
 265 to_hsmc_nand_controller(struct nand_controller *ctl)
 266 {
 267         return container_of(to_nand_controller(ctl),
 268                             struct atmel_hsmc_nand_controller, base);
 269 }
 270
 271 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
 272 {
 273         op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
 274         op->wait ^= status & op->wait;
 275
 276         return !op->wait || op->errors;
 277 }
 278
 279 static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
 280 {
 281         struct atmel_hsmc_nand_controller *nc = data;
 282         u32 sr, rcvd;
 283         bool done;
 284
 285         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
 286
 287         rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
 288         done = atmel_nfc_op_done(&nc->op, sr);
 289
 290         if (rcvd)
 291                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
 292
 293         if (done)
 294                 complete(&nc->complete);
 295
 296         return rcvd ? IRQ_HANDLED : IRQ_NONE;
 297 }
 298
 299 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
 300                           unsigned int timeout_ms)
 301 {
 302         int ret;
 303
 304         if (!timeout_ms)
 305                 timeout_ms = DEFAULT_TIMEOUT_MS;
 306
 307         if (poll) {
 308                 u32 status;
 309
 310                 ret = regmap_read_poll_timeout(nc->base.smc,
 311                                                ATMEL_HSMC_NFC_SR, status,
 312                                                atmel_nfc_op_done(&nc->op,
 313                                                                  status),
 314                                                0, timeout_ms * 1000);
 315         } else {
 316                 init_completion(&nc->complete);
 317                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
 318                              nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
 319                 ret = wait_for_completion_timeout(&nc->complete,
 320                                                 msecs_to_jiffies(timeout_ms));
 321                 if (!ret)
 322                         ret = -ETIMEDOUT;
 323                 else
 324                         ret = 0;
 325
 326                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
 327         }
 328
 329         if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
 330                 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
 331                 ret = -ETIMEDOUT;
 332         }
 333
 334         if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
 335                 dev_err(nc->base.dev, "Access to an undefined area\n");
 336                 ret = -EIO;
 337         }
 338
 339         if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
 340                 dev_err(nc->base.dev, "Access while busy\n");
 341                 ret = -EIO;
 342         }
 343
 344         if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
 345                 dev_err(nc->base.dev, "Wrong access size\n");
 346                 ret = -EIO;
 347         }
 348
 349         return ret;
 350 }
 351
 352 static void atmel_nand_dma_transfer_finished(void *data)
 353 {
 354         struct completion *finished = data;
 355
 356         complete(finished);
 357 }
 358
 359 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
 360                                    void *buf, dma_addr_t dev_dma, size_t len,
 361                                    enum dma_data_direction dir)
 362 {
 363         DECLARE_COMPLETION_ONSTACK(finished);
 364         dma_addr_t src_dma, dst_dma, buf_dma;
 365         struct dma_async_tx_descriptor *tx;
 366         dma_cookie_t cookie;
 367
 368         buf_dma = dma_map_single(nc->dev, buf, len, dir);
 369         if (dma_mapping_error(nc->dev, dev_dma)) {
 370                 dev_err(nc->dev,
 371                         "Failed to prepare a buffer for DMA access\n");
 372                 goto err;
 373         }
 374
 375         if (dir == DMA_FROM_DEVICE) {
 376                 src_dma = dev_dma;
 377                 dst_dma = buf_dma;
 378         } else {
 379                 src_dma = buf_dma;
 380                 dst_dma = dev_dma;
 381         }
 382
 383         tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
 384                                        DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
 385         if (!tx) {
 386                 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
 387                 goto err_unmap;
 388         }
 389
 390         tx->callback = atmel_nand_dma_transfer_finished;
 391         tx->callback_param = &finished;
 392
 393         cookie = dmaengine_submit(tx);
 394         if (dma_submit_error(cookie)) {
 395                 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
 396                 goto err_unmap;
 397         }
 398
 399         dma_async_issue_pending(nc->dmac);
 400         wait_for_completion(&finished);
 401         dma_unmap_single(nc->dev, buf_dma, len, dir);
 402
 403         return 0;
 404
 405 err_unmap:
 406         dma_unmap_single(nc->dev, buf_dma, len, dir);
 407
 408 err:
 409         dev_dbg(nc->dev, "Fall back to CPU I/O\n");
 410
 411         return -EIO;
 412 }
 413
 414 static u8 atmel_nand_read_byte(struct mtd_info *mtd)
 415 {
 416         struct nand_chip *chip = mtd_to_nand(mtd);
 417         struct atmel_nand *nand = to_atmel_nand(chip);
 418
 419         return ioread8(nand->activecs->io.virt);
 420 }
 421
 422 static u16 atmel_nand_read_word(struct mtd_info *mtd)
 423 {
 424         struct nand_chip *chip = mtd_to_nand(mtd);
 425         struct atmel_nand *nand = to_atmel_nand(chip);
 426
 427         return ioread16(nand->activecs->io.virt);
 428 }
 429
 430 static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
 431 {
 432         struct nand_chip *chip = mtd_to_nand(mtd);
 433         struct atmel_nand *nand = to_atmel_nand(chip);
 434
 435         if (chip->options & NAND_BUSWIDTH_16)
 436                 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
 437         else
 438                 iowrite8(byte, nand->activecs->io.virt);
 439 }
 440
 441 static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 442 {
 443         struct nand_chip *chip = mtd_to_nand(mtd);
 444         struct atmel_nand *nand = to_atmel_nand(chip);
 445         struct atmel_nand_controller *nc;
 446
 447         nc = to_nand_controller(chip->controller);
 448
 449         /*
 450          * If the controller supports DMA, the buffer address is DMA-able and
 451          * len is long enough to make DMA transfers profitable, let's trigger
 452          * a DMA transfer. If it fails, fallback to PIO mode.
 453          */
 454         if (nc->dmac && virt_addr_valid(buf) &&
 455             len >= MIN_DMA_LEN &&
 456             !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
 457                                      DMA_FROM_DEVICE))
 458                 return;
 459
 460         if (chip->options & NAND_BUSWIDTH_16)
 461                 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
 462         else
 463                 ioread8_rep(nand->activecs->io.virt, buf, len);
 464 }
 465
 466 static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 467 {
 468         struct nand_chip *chip = mtd_to_nand(mtd);
 469         struct atmel_nand *nand = to_atmel_nand(chip);
 470         struct atmel_nand_controller *nc;
 471
 472         nc = to_nand_controller(chip->controller);
 473
 474         /*
 475          * If the controller supports DMA, the buffer address is DMA-able and
 476          * len is long enough to make DMA transfers profitable, let's trigger
 477          * a DMA transfer. If it fails, fallback to PIO mode.
 478          */
 479         if (nc->dmac && virt_addr_valid(buf) &&
 480             len >= MIN_DMA_LEN &&
 481             !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
 482                                      len, DMA_TO_DEVICE))
 483                 return;
 484
 485         if (chip->options & NAND_BUSWIDTH_16)
 486                 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
 487         else
 488                 iowrite8_rep(nand->activecs->io.virt, buf, len);
 489 }
 490
 491 static int atmel_nand_dev_ready(struct mtd_info *mtd)
 492 {
 493         struct nand_chip *chip = mtd_to_nand(mtd);
 494         struct atmel_nand *nand = to_atmel_nand(chip);
 495
 496         return gpiod_get_value(nand->activecs->rb.gpio);
 497 }
 498
 499 static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
 500 {
 501         struct nand_chip *chip = mtd_to_nand(mtd);
 502         struct atmel_nand *nand = to_atmel_nand(chip);
 503
 504         if (cs < 0 || cs >= nand->numcs) {
 505                 nand->activecs = NULL;
 506                 chip->dev_ready = NULL;
 507                 return;
 508         }
 509
 510         nand->activecs = &nand->cs[cs];
 511
 512         if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
 513                 chip->dev_ready = atmel_nand_dev_ready;
 514 }
 515
 516 static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
 517 {
 518         struct nand_chip *chip = mtd_to_nand(mtd);
 519         struct atmel_nand *nand = to_atmel_nand(chip);
 520         struct atmel_hsmc_nand_controller *nc;
 521         u32 status;
 522
 523         nc = to_hsmc_nand_controller(chip->controller);
 524
 525         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
 526
 527         return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
 528 }
 529
 530 static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
 531 {
 532         struct nand_chip *chip = mtd_to_nand(mtd);
 533         struct atmel_nand *nand = to_atmel_nand(chip);
 534         struct atmel_hsmc_nand_controller *nc;
 535
 536         nc = to_hsmc_nand_controller(chip->controller);
 537
 538         atmel_nand_select_chip(mtd, cs);
 539
 540         if (!nand->activecs) {
 541                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 542                              ATMEL_HSMC_NFC_CTRL_DIS);
 543                 return;
 544         }
 545
 546         if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
 547                 chip->dev_ready = atmel_hsmc_nand_dev_ready;
 548
 549         regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
 550                            ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
 551                            ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
 552                            ATMEL_HSMC_NFC_CFG_RSPARE |
 553                            ATMEL_HSMC_NFC_CFG_WSPARE,
 554                            ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
 555                            ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
 556                            ATMEL_HSMC_NFC_CFG_RSPARE);
 557         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 558                      ATMEL_HSMC_NFC_CTRL_EN);
 559 }
 560
 561 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
 562 {
 563         u8 *addrs = nc->op.addrs;
 564         unsigned int op = 0;
 565         u32 addr, val;
 566         int i, ret;
 567
 568         nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
 569
 570         for (i = 0; i < nc->op.ncmds; i++)
 571                 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
 572
 573         if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 574                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
 575
 576         op |= ATMEL_NFC_CSID(nc->op.cs) |
 577               ATMEL_NFC_ACYCLE(nc->op.naddrs);
 578
 579         if (nc->op.ncmds > 1)
 580                 op |= ATMEL_NFC_VCMD2;
 581
 582         addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
 583                (addrs[3] << 24);
 584
 585         if (nc->op.data != ATMEL_NFC_NO_DATA) {
 586                 op |= ATMEL_NFC_DATAEN;
 587                 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
 588
 589                 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
 590                         op |= ATMEL_NFC_NFCWR;
 591         }
 592
 593         /* Clear all flags. */
 594         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
 595
 596         /* Send the command. */
 597         regmap_write(nc->io, op, addr);
 598
 599         ret = atmel_nfc_wait(nc, poll, 0);
 600         if (ret)
 601                 dev_err(nc->base.dev,
 602                         "Failed to send NAND command (err = %d)!",
 603                         ret);
 604
 605         /* Reset the op state. */
 606         memset(&nc->op, 0, sizeof(nc->op));
 607
 608         return ret;
 609 }
 610
 611 static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
 612                                      unsigned int ctrl)
 613 {
 614         struct nand_chip *chip = mtd_to_nand(mtd);
 615         struct atmel_nand *nand = to_atmel_nand(chip);
 616         struct atmel_hsmc_nand_controller *nc;
 617
 618         nc = to_hsmc_nand_controller(chip->controller);
 619
 620         if (ctrl & NAND_ALE) {
 621                 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 622                         return;
 623
 624                 nc->op.addrs[nc->op.naddrs++] = dat;
 625         } else if (ctrl & NAND_CLE) {
 626                 if (nc->op.ncmds > 1)
 627                         return;
 628
 629                 nc->op.cmds[nc->op.ncmds++] = dat;
 630         }
 631
 632         if (dat == NAND_CMD_NONE) {
 633                 nc->op.cs = nand->activecs->id;
 634                 atmel_nfc_exec_op(nc, true);
 635         }
 636 }
 637
 638 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 639                                 unsigned int ctrl)
 640 {
 641         struct nand_chip *chip = mtd_to_nand(mtd);
 642         struct atmel_nand *nand = to_atmel_nand(chip);
 643         struct atmel_nand_controller *nc;
 644
 645         nc = to_nand_controller(chip->controller);
 646
 647         if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) {
 648                 if (ctrl & NAND_NCE)
 649                         gpiod_set_value(nand->activecs->csgpio, 0);
 650                 else
 651                         gpiod_set_value(nand->activecs->csgpio, 1);
 652         }
 653
 654         if (ctrl & NAND_ALE)
 655                 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
 656         else if (ctrl & NAND_CLE)
 657                 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
 658 }
 659
 660 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
 661                                    bool oob_required)
 662 {
 663         struct mtd_info *mtd = nand_to_mtd(chip);
 664         struct atmel_hsmc_nand_controller *nc;
 665         int ret = -EIO;
 666
 667         nc = to_hsmc_nand_controller(chip->controller);
 668
 669         if (nc->base.dmac)
 670                 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
 671                                               nc->sram.dma, mtd->writesize,
 672                                               DMA_TO_DEVICE);
 673
 674         /* Falling back to CPU copy. */
 675         if (ret)
 676                 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
 677
 678         if (oob_required)
 679                 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
 680                             mtd->oobsize);
 681 }
 682
 683 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
 684                                      bool oob_required)
 685 {
 686         struct mtd_info *mtd = nand_to_mtd(chip);
 687         struct atmel_hsmc_nand_controller *nc;
 688         int ret = -EIO;
 689
 690         nc = to_hsmc_nand_controller(chip->controller);
 691
 692         if (nc->base.dmac)
 693                 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
 694                                               mtd->writesize, DMA_FROM_DEVICE);
 695
 696         /* Falling back to CPU copy. */
 697         if (ret)
 698                 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
 699
 700         if (oob_required)
 701                 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
 702                               mtd->oobsize);
 703 }
 704
 705 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
 706 {
 707         struct mtd_info *mtd = nand_to_mtd(chip);
 708         struct atmel_hsmc_nand_controller *nc;
 709
 710         nc = to_hsmc_nand_controller(chip->controller);
 711
 712         if (column >= 0) {
 713                 nc->op.addrs[nc->op.naddrs++] = column;
 714
 715                 /*
 716                  * 2 address cycles for the column offset on large page NANDs.
 717                  */
 718                 if (mtd->writesize > 512)
 719                         nc->op.addrs[nc->op.naddrs++] = column >> 8;
 720         }
 721
 722         if (page >= 0) {
 723                 nc->op.addrs[nc->op.naddrs++] = page;
 724                 nc->op.addrs[nc->op.naddrs++] = page >> 8;
 725
 726                 if (chip->options & NAND_ROW_ADDR_3)
 727                         nc->op.addrs[nc->op.naddrs++] = page >> 16;
 728         }
 729 }
 730
 731 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
 732 {
 733         struct atmel_nand *nand = to_atmel_nand(chip);
 734         struct atmel_nand_controller *nc;
 735         int ret;
 736
 737         nc = to_nand_controller(chip->controller);
 738
 739         if (raw)
 740                 return 0;
 741
 742         ret = atmel_pmecc_enable(nand->pmecc, op);
 743         if (ret)
 744                 dev_err(nc->dev,
 745                         "Failed to enable ECC engine (err = %d)\n", ret);
 746
 747         return ret;
 748 }
 749
 750 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
 751 {
 752         struct atmel_nand *nand = to_atmel_nand(chip);
 753
 754         if (!raw)
 755                 atmel_pmecc_disable(nand->pmecc);
 756 }
 757
 758 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
 759 {
 760         struct atmel_nand *nand = to_atmel_nand(chip);
 761         struct mtd_info *mtd = nand_to_mtd(chip);
 762         struct atmel_nand_controller *nc;
 763         struct mtd_oob_region oobregion;
 764         void *eccbuf;
 765         int ret, i;
 766
 767         nc = to_nand_controller(chip->controller);
 768
 769         if (raw)
 770                 return 0;
 771
 772         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 773         if (ret) {
 774                 dev_err(nc->dev,
 775                         "Failed to transfer NAND page data (err = %d)\n",
 776                         ret);
 777                 return ret;
 778         }
 779
 780         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 781         eccbuf = chip->oob_poi + oobregion.offset;
 782
 783         for (i = 0; i < chip->ecc.steps; i++) {
 784                 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
 785                                                    eccbuf);
 786                 eccbuf += chip->ecc.bytes;
 787         }
 788
 789         return 0;
 790 }
 791
 792 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
 793                                          bool raw)
 794 {
 795         struct atmel_nand *nand = to_atmel_nand(chip);
 796         struct mtd_info *mtd = nand_to_mtd(chip);
 797         struct atmel_nand_controller *nc;
 798         struct mtd_oob_region oobregion;
 799         int ret, i, max_bitflips = 0;
 800         void *databuf, *eccbuf;
 801
 802         nc = to_nand_controller(chip->controller);
 803
 804         if (raw)
 805                 return 0;
 806
 807         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 808         if (ret) {
 809                 dev_err(nc->dev,
 810                         "Failed to read NAND page data (err = %d)\n",
 811                         ret);
 812                 return ret;
 813         }
 814
 815         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 816         eccbuf = chip->oob_poi + oobregion.offset;
 817         databuf = buf;
 818
 819         for (i = 0; i < chip->ecc.steps; i++) {
 820                 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
 821                                                  eccbuf);
 822                 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
 823                         ret = nand_check_erased_ecc_chunk(databuf,
 824                                                           chip->ecc.size,
 825                                                           eccbuf,
 826                                                           chip->ecc.bytes,
 827                                                           NULL, 0,
 828                                                           chip->ecc.strength);
 829
 830                 if (ret >= 0) {
 831                         mtd->ecc_stats.corrected += ret;
 832                         max_bitflips = max(ret, max_bitflips);
 833                 } else {
 834                         mtd->ecc_stats.failed++;
 835                 }
 836
 837                 databuf += chip->ecc.size;
 838                 eccbuf += chip->ecc.bytes;
 839         }
 840
 841         return max_bitflips;
 842 }
 843
 844 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
 845                                      bool oob_required, int page, bool raw)
 846 {
 847         struct mtd_info *mtd = nand_to_mtd(chip);
 848         struct atmel_nand *nand = to_atmel_nand(chip);
 849         int ret;
 850
 851         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
 852
 853         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 854         if (ret)
 855                 return ret;
 856
 857         atmel_nand_write_buf(mtd, buf, mtd->writesize);
 858
 859         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 860         if (ret) {
 861                 atmel_pmecc_disable(nand->pmecc);
 862                 return ret;
 863         }
 864
 865         atmel_nand_pmecc_disable(chip, raw);
 866
 867         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 868
 869         return nand_prog_page_end_op(chip);
 870 }
 871
 872 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 873                                        struct nand_chip *chip, const u8 *buf,
 874                                        int oob_required, int page)
 875 {
 876         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
 877 }
 878
 879 static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
 880                                            struct nand_chip *chip,
 881                                            const u8 *buf, int oob_required,
 882                                            int page)
 883 {
 884         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
 885 }
 886
 887 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 888                                     bool oob_required, int page, bool raw)
 889 {
 890         struct mtd_info *mtd = nand_to_mtd(chip);
 891         int ret;
 892
 893         nand_read_page_op(chip, page, 0, NULL, 0);
 894
 895         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
 896         if (ret)
 897                 return ret;
 898
 899         atmel_nand_read_buf(mtd, buf, mtd->writesize);
 900         atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 901
 902         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
 903
 904         atmel_nand_pmecc_disable(chip, raw);
 905
 906         return ret;
 907 }
 908
 909 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 910                                       struct nand_chip *chip, u8 *buf,
 911                                       int oob_required, int page)
 912 {
 913         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
 914 }
 915
 916 static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
 917                                           struct nand_chip *chip, u8 *buf,
 918                                           int oob_required, int page)
 919 {
 920         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
 921 }
 922
 923 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
 924                                           const u8 *buf, bool oob_required,
 925                                           int page, bool raw)
 926 {
 927         struct mtd_info *mtd = nand_to_mtd(chip);
 928         struct atmel_nand *nand = to_atmel_nand(chip);
 929         struct atmel_hsmc_nand_controller *nc;
 930         int ret, status;
 931
 932         nc = to_hsmc_nand_controller(chip->controller);
 933
 934         atmel_nfc_copy_to_sram(chip, buf, false);
 935
 936         nc->op.cmds[0] = NAND_CMD_SEQIN;
 937         nc->op.ncmds = 1;
 938         atmel_nfc_set_op_addr(chip, page, 0x0);
 939         nc->op.cs = nand->activecs->id;
 940         nc->op.data = ATMEL_NFC_WRITE_DATA;
 941
 942         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 943         if (ret)
 944                 return ret;
 945
 946         ret = atmel_nfc_exec_op(nc, false);
 947         if (ret) {
 948                 atmel_nand_pmecc_disable(chip, raw);
 949                 dev_err(nc->base.dev,
 950                         "Failed to transfer NAND page data (err = %d)\n",
 951                         ret);
 952                 return ret;
 953         }
 954
 955         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 956
 957         atmel_nand_pmecc_disable(chip, raw);
 958
 959         if (ret)
 960                 return ret;
 961
 962         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 963
 964         nc->op.cmds[0] = NAND_CMD_PAGEPROG;
 965         nc->op.ncmds = 1;
 966         nc->op.cs = nand->activecs->id;
 967         ret = atmel_nfc_exec_op(nc, false);
 968         if (ret)
 969                 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
 970                         ret);
 971
 972         status = chip->waitfunc(mtd, chip);
 973         if (status & NAND_STATUS_FAIL)
 974                 return -EIO;
 975
 976         return ret;
 977 }
 978
 979 static int atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd,
 980                                             struct nand_chip *chip,
 981                                             const u8 *buf, int oob_required,
 982                                             int page)
 983 {
 984         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 985                                               false);
 986 }
 987
 988 static int atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd,
 989                                                 struct nand_chip *chip,
 990                                                 const u8 *buf,
 991                                                 int oob_required, int page)
 992 {
 993         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 994                                               true);
 995 }
 996
 997 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 998                                          bool oob_required, int page,
 999                                          bool raw)
1000 {
1001         struct mtd_info *mtd = nand_to_mtd(chip);
1002         struct atmel_nand *nand = to_atmel_nand(chip);
1003         struct atmel_hsmc_nand_controller *nc;
1004         int ret;
1005
1006         nc = to_hsmc_nand_controller(chip->controller);
1007
1008         /*
1009          * Optimized read page accessors only work when the NAND R/B pin is
1010          * connected to a native SoC R/B pin. If that's not the case, fallback
1011          * to the non-optimized one.
1012          */
1013         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
1014                 nand_read_page_op(chip, page, 0, NULL, 0);
1015
1016                 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
1017                                                 raw);
1018         }
1019
1020         nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1021
1022         if (mtd->writesize > 512)
1023                 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1024
1025         atmel_nfc_set_op_addr(chip, page, 0x0);
1026         nc->op.cs = nand->activecs->id;
1027         nc->op.data = ATMEL_NFC_READ_DATA;
1028
1029         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1030         if (ret)
1031                 return ret;
1032
1033         ret = atmel_nfc_exec_op(nc, false);
1034         if (ret) {
1035                 atmel_nand_pmecc_disable(chip, raw);
1036                 dev_err(nc->base.dev,
1037                         "Failed to load NAND page data (err = %d)\n",
1038                         ret);
1039                 return ret;
1040         }
1041
1042         atmel_nfc_copy_from_sram(chip, buf, true);
1043
1044         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1045
1046         atmel_nand_pmecc_disable(chip, raw);
1047
1048         return ret;
1049 }
1050
1051 static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
1052                                            struct nand_chip *chip, u8 *buf,
1053                                            int oob_required, int page)
1054 {
1055         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1056                                              false);
1057 }
1058
1059 static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
1060                                                struct nand_chip *chip,
1061                                                u8 *buf, int oob_required,
1062                                                int page)
1063 {
1064         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1065                                              true);
1066 }
1067
1068 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1069 {
1070         struct mtd_info *mtd = nand_to_mtd(chip);
1071         struct atmel_nand *nand = to_atmel_nand(chip);
1072         struct atmel_nand_controller *nc;
1073         struct atmel_pmecc_user_req req;
1074
1075         nc = to_nand_controller(chip->controller);
1076
1077         if (!nc->pmecc) {
1078                 dev_err(nc->dev, "HW ECC not supported\n");
1079                 return -ENOTSUPP;
1080         }
1081
1082         if (nc->caps->legacy_of_bindings) {
1083                 u32 val;
1084
1085                 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1086                                           &val))
1087                         chip->ecc.strength = val;
1088
1089                 if (!of_property_read_u32(nc->dev->of_node,
1090                                           "atmel,pmecc-sector-size",
1091                                           &val))
1092                         chip->ecc.size = val;
1093         }
1094
1095         if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1096                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1097         else if (chip->ecc.strength)
1098                 req.ecc.strength = chip->ecc.strength;
1099         else if (chip->ecc_strength_ds)
1100                 req.ecc.strength = chip->ecc_strength_ds;
1101         else
1102                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1103
1104         if (chip->ecc.size)
1105                 req.ecc.sectorsize = chip->ecc.size;
1106         else if (chip->ecc_step_ds)
1107                 req.ecc.sectorsize = chip->ecc_step_ds;
1108         else
1109                 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1110
1111         req.pagesize = mtd->writesize;
1112         req.oobsize = mtd->oobsize;
1113
1114         if (mtd->writesize <= 512) {
1115                 req.ecc.bytes = 4;
1116                 req.ecc.ooboffset = 0;
1117         } else {
1118                 req.ecc.bytes = mtd->oobsize - 2;
1119                 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1120         }
1121
1122         nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1123         if (IS_ERR(nand->pmecc))
1124                 return PTR_ERR(nand->pmecc);
1125
1126         chip->ecc.algo = NAND_ECC_BCH;
1127         chip->ecc.size = req.ecc.sectorsize;
1128         chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1129         chip->ecc.strength = req.ecc.strength;
1130
1131         chip->options |= NAND_NO_SUBPAGE_WRITE;
1132
1133         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1134
1135         return 0;
1136 }
1137
1138 static int atmel_nand_ecc_init(struct nand_chip *chip)
1139 {
1140         struct atmel_nand_controller *nc;
1141         int ret;
1142
1143         nc = to_nand_controller(chip->controller);
1144
1145         switch (chip->ecc.mode) {
1146         case NAND_ECC_NONE:
1147         case NAND_ECC_SOFT:
1148                 /*
1149                  * Nothing to do, the core will initialize everything for us.
1150                  */
1151                 break;
1152
1153         case NAND_ECC_HW:
1154                 ret = atmel_nand_pmecc_init(chip);
1155                 if (ret)
1156                         return ret;
1157
1158                 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1159                 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1160                 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1161                 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1162                 break;
1163
1164         default:
1165                 /* Other modes are not supported. */
1166                 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1167                         chip->ecc.mode);
1168                 return -ENOTSUPP;
1169         }
1170
1171         return 0;
1172 }
1173
1174 static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
1175 {
1176         int ret;
1177
1178         ret = atmel_nand_ecc_init(chip);
1179         if (ret)
1180                 return ret;
1181
1182         if (chip->ecc.mode != NAND_ECC_HW)
1183                 return 0;
1184
1185         /* Adjust the ECC operations for the HSMC IP. */
1186         chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1187         chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1188         chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1189         chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1190
1191         return 0;
1192 }
1193
1194 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1195                                         const struct nand_data_interface *conf,
1196                                         struct atmel_smc_cs_conf *smcconf)
1197 {
1198         u32 ncycles, totalcycles, timeps, mckperiodps;
1199         struct atmel_nand_controller *nc;
1200         int ret;
1201
1202         nc = to_nand_controller(nand->base.controller);
1203
1204         /* DDR interface not supported. */
1205         if (conf->type != NAND_SDR_IFACE)
1206                 return -ENOTSUPP;
1207
1208         /*
1209          * tRC < 30ns implies EDO mode. This controller does not support this
1210          * mode.
1211          */
1212         if (conf->timings.sdr.tRC_min < 30000)
1213                 return -ENOTSUPP;
1214
1215         atmel_smc_cs_conf_init(smcconf);
1216
1217         mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1218         mckperiodps *= 1000;
1219
1220         /*
1221          * Set write pulse timing. This one is easy to extract:
1222          *
1223          * NWE_PULSE = tWP
1224          */
1225         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1226         totalcycles = ncycles;
1227         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1228                                           ncycles);
1229         if (ret)
1230                 return ret;
1231
1232         /*
1233          * The write setup timing depends on the operation done on the NAND.
1234          * All operations goes through the same data bus, but the operation
1235          * type depends on the address we are writing to (ALE/CLE address
1236          * lines).
1237          * Since we have no way to differentiate the different operations at
1238          * the SMC level, we must consider the worst case (the biggest setup
1239          * time among all operation types):
1240          *
1241          * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1242          */
1243         timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1244                       conf->timings.sdr.tALS_min);
1245         timeps = max(timeps, conf->timings.sdr.tDS_min);
1246         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1247         ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1248         totalcycles += ncycles;
1249         ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1250                                           ncycles);
1251         if (ret)
1252                 return ret;
1253
1254         /*
1255          * As for the write setup timing, the write hold timing depends on the
1256          * operation done on the NAND:
1257          *
1258          * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1259          */
1260         timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1261                       conf->timings.sdr.tALH_min);
1262         timeps = max3(timeps, conf->timings.sdr.tDH_min,
1263                       conf->timings.sdr.tWH_min);
1264         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1265         totalcycles += ncycles;
1266
1267         /*
1268          * The write cycle timing is directly matching tWC, but is also
1269          * dependent on the other timings on the setup and hold timings we
1270          * calculated earlier, which gives:
1271          *
1272          * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1273          */
1274         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1275         ncycles = max(totalcycles, ncycles);
1276         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1277                                           ncycles);
1278         if (ret)
1279                 return ret;
1280
1281         /*
1282          * We don't want the CS line to be toggled between each byte/word
1283          * transfer to the NAND. The only way to guarantee that is to have the
1284          * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1285          *
1286          * NCS_WR_PULSE = NWE_CYCLE
1287          */
1288         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1289                                           ncycles);
1290         if (ret)
1291                 return ret;
1292
1293         /*
1294          * As for the write setup timing, the read hold timing depends on the
1295          * operation done on the NAND:
1296          *
1297          * NRD_HOLD = max(tREH, tRHOH)
1298          */
1299         timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1300         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1301         totalcycles = ncycles;
1302
1303         /*
1304          * TDF = tRHZ - NRD_HOLD
1305          */
1306         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1307         ncycles -= totalcycles;
1308
1309         /*
1310          * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1311          * we might end up with a config that does not fit in the TDF field.
1312          * Just take the max value in this case and hope that the NAND is more
1313          * tolerant than advertised.
1314          */
1315         if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1316                 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1317         else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1318                 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1319
1320         smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1321                          ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1322
1323         /*
1324          * Read pulse timing directly matches tRP:
1325          *
1326          * NRD_PULSE = tRP
1327          */
1328         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1329         totalcycles += ncycles;
1330         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1331                                           ncycles);
1332         if (ret)
1333                 return ret;
1334
1335         /*
1336          * The write cycle timing is directly matching tWC, but is also
1337          * dependent on the setup and hold timings we calculated earlier,
1338          * which gives:
1339          *
1340          * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1341          *
1342          * NRD_SETUP is always 0.
1343          */
1344         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1345         ncycles = max(totalcycles, ncycles);
1346         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1347                                           ncycles);
1348         if (ret)
1349                 return ret;
1350
1351         /*
1352          * We don't want the CS line to be toggled between each byte/word
1353          * transfer from the NAND. The only way to guarantee that is to have
1354          * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1355          *
1356          * NCS_RD_PULSE = NRD_CYCLE
1357          */
1358         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1359                                           ncycles);
1360         if (ret)
1361                 return ret;
1362
1363         /* Txxx timings are directly matching tXXX ones. */
1364         ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1365         ret = atmel_smc_cs_conf_set_timing(smcconf,
1366                                            ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1367                                            ncycles);
1368         if (ret)
1369                 return ret;
1370
1371         ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1372         ret = atmel_smc_cs_conf_set_timing(smcconf,
1373                                            ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1374                                            ncycles);
1375         /*
1376          * Version 4 of the ONFI spec mandates that tADL be at least 400
1377          * nanoseconds, but, depending on the master clock rate, 400 ns may not
1378          * fit in the tADL field of the SMC reg. We need to relax the check and
1379          * accept the -ERANGE return code.
1380          *
1381          * Note that previous versions of the ONFI spec had a lower tADL_min
1382          * (100 or 200 ns). It's not clear why this timing constraint got
1383          * increased but it seems most NANDs are fine with values lower than
1384          * 400ns, so we should be safe.
1385          */
1386         if (ret && ret != -ERANGE)
1387                 return ret;
1388
1389         ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1390         ret = atmel_smc_cs_conf_set_timing(smcconf,
1391                                            ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1392                                            ncycles);
1393         if (ret)
1394                 return ret;
1395
1396         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1397         ret = atmel_smc_cs_conf_set_timing(smcconf,
1398                                            ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1399                                            ncycles);
1400         if (ret)
1401                 return ret;
1402
1403         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1404         ret = atmel_smc_cs_conf_set_timing(smcconf,
1405                                            ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1406                                            ncycles);
1407         if (ret)
1408                 return ret;
1409
1410         /* Attach the CS line to the NFC logic. */
1411         smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1412
1413         /* Set the appropriate data bus width. */
1414         if (nand->base.options & NAND_BUSWIDTH_16)
1415                 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1416
1417         /* Operate in NRD/NWE READ/WRITEMODE. */
1418         smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1419                          ATMEL_SMC_MODE_WRITEMODE_NWE;
1420
1421         return 0;
1422 }
1423
1424 static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
1425                                         int csline,
1426                                         const struct nand_data_interface *conf)
1427 {
1428         struct atmel_nand_controller *nc;
1429         struct atmel_smc_cs_conf smcconf;
1430         struct atmel_nand_cs *cs;
1431         int ret;
1432
1433         nc = to_nand_controller(nand->base.controller);
1434
1435         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1436         if (ret)
1437                 return ret;
1438
1439         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1440                 return 0;
1441
1442         cs = &nand->cs[csline];
1443         cs->smcconf = smcconf;
1444         atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1445
1446         return 0;
1447 }
1448
1449 static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
1450                                         int csline,
1451                                         const struct nand_data_interface *conf)
1452 {
1453         struct atmel_hsmc_nand_controller *nc;
1454         struct atmel_smc_cs_conf smcconf;
1455         struct atmel_nand_cs *cs;
1456         int ret;
1457
1458         nc = to_hsmc_nand_controller(nand->base.controller);
1459
1460         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1461         if (ret)
1462                 return ret;
1463
1464         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1465                 return 0;
1466
1467         cs = &nand->cs[csline];
1468         cs->smcconf = smcconf;
1469
1470         if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1471                 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1472
1473         atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1474                                  &cs->smcconf);
1475
1476         return 0;
1477 }
1478
1479 static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
1480                                         const struct nand_data_interface *conf)
1481 {
1482         struct nand_chip *chip = mtd_to_nand(mtd);
1483         struct atmel_nand *nand = to_atmel_nand(chip);
1484         struct atmel_nand_controller *nc;
1485
1486         nc = to_nand_controller(nand->base.controller);
1487
1488         if (csline >= nand->numcs ||
1489             (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1490                 return -EINVAL;
1491
1492         return nc->caps->ops->setup_data_interface(nand, csline, conf);
1493 }
1494
1495 static void atmel_nand_init(struct atmel_nand_controller *nc,
1496                             struct atmel_nand *nand)
1497 {
1498         struct nand_chip *chip = &nand->base;
1499         struct mtd_info *mtd = nand_to_mtd(chip);
1500
1501         mtd->dev.parent = nc->dev;
1502         nand->base.controller = &nc->base;
1503
1504         chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1505         chip->read_byte = atmel_nand_read_byte;
1506         chip->read_word = atmel_nand_read_word;
1507         chip->write_byte = atmel_nand_write_byte;
1508         chip->read_buf = atmel_nand_read_buf;
1509         chip->write_buf = atmel_nand_write_buf;
1510         chip->select_chip = atmel_nand_select_chip;
1511
1512         if (nc->mck && nc->caps->ops->setup_data_interface)
1513                 chip->setup_data_interface = atmel_nand_setup_data_interface;
1514
1515         /* Some NANDs require a longer delay than the default one (20us). */
1516         chip->chip_delay = 40;
1517
1518         /*
1519          * Use a bounce buffer when the buffer passed by the MTD user is not
1520          * suitable for DMA.
1521          */
1522         if (nc->dmac)
1523                 chip->options |= NAND_USE_BOUNCE_BUFFER;
1524
1525         /* Default to HW ECC if pmecc is available. */
1526         if (nc->pmecc)
1527                 chip->ecc.mode = NAND_ECC_HW;
1528 }
1529
1530 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1531                                 struct atmel_nand *nand)
1532 {
1533         struct nand_chip *chip = &nand->base;
1534         struct atmel_smc_nand_controller *smc_nc;
1535         int i;
1536
1537         atmel_nand_init(nc, nand);
1538
1539         smc_nc = to_smc_nand_controller(chip->controller);
1540         if (!smc_nc->matrix)
1541                 return;
1542
1543         /* Attach the CS to the NAND Flash logic. */
1544         for (i = 0; i < nand->numcs; i++)
1545                 regmap_update_bits(smc_nc->matrix, smc_nc->ebi_csa_offs,
1546                                    BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1547 }
1548
1549 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1550                                  struct atmel_nand *nand)
1551 {
1552         struct nand_chip *chip = &nand->base;
1553
1554         atmel_nand_init(nc, nand);
1555
1556         /* Overload some methods for the HSMC controller. */
1557         chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1558         chip->select_chip = atmel_hsmc_nand_select_chip;
1559 }
1560
1561 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
1562 {
1563         struct nand_chip *chip = &nand->base;
1564         struct mtd_info *mtd = nand_to_mtd(chip);
1565         int ret;
1566
1567         ret = mtd_device_unregister(mtd);
1568         if (ret)
1569                 return ret;
1570
1571         nand_cleanup(chip);
1572         list_del(&nand->node);
1573
1574         return 0;
1575 }
1576
1577 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1578                                             struct device_node *np,
1579                                             int reg_cells)
1580 {
1581         struct atmel_nand *nand;
1582         struct gpio_desc *gpio;
1583         int numcs, ret, i;
1584
1585         numcs = of_property_count_elems_of_size(np, "reg",
1586                                                 reg_cells * sizeof(u32));
1587         if (numcs < 1) {
1588                 dev_err(nc->dev, "Missing or invalid reg property\n");
1589                 return ERR_PTR(-EINVAL);
1590         }
1591
1592         nand = devm_kzalloc(nc->dev,
1593                             sizeof(*nand) + (numcs * sizeof(*nand->cs)),
1594                             GFP_KERNEL);
1595         if (!nand) {
1596                 dev_err(nc->dev, "Failed to allocate NAND object\n");
1597                 return ERR_PTR(-ENOMEM);
1598         }
1599
1600         nand->numcs = numcs;
1601
1602         gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "det", 0,
1603                                                       &np->fwnode, GPIOD_IN,
1604                                                       "nand-det");
1605         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1606                 dev_err(nc->dev,
1607                         "Failed to get detect gpio (err = %ld)\n",
1608                         PTR_ERR(gpio));
1609                 return ERR_CAST(gpio);
1610         }
1611
1612         if (!IS_ERR(gpio))
1613                 nand->cdgpio = gpio;
1614
1615         for (i = 0; i < numcs; i++) {
1616                 struct resource res;
1617                 u32 val;
1618
1619                 ret = of_address_to_resource(np, 0, &res);
1620                 if (ret) {
1621                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1622                                 ret);
1623                         return ERR_PTR(ret);
1624                 }
1625
1626                 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1627                                                  &val);
1628                 if (ret) {
1629                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1630                                 ret);
1631                         return ERR_PTR(ret);
1632                 }
1633
1634                 nand->cs[i].id = val;
1635
1636                 nand->cs[i].io.dma = res.start;
1637                 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1638                 if (IS_ERR(nand->cs[i].io.virt))
1639                         return ERR_CAST(nand->cs[i].io.virt);
1640
1641                 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1642                         if (val > ATMEL_NFC_MAX_RB_ID)
1643                                 return ERR_PTR(-EINVAL);
1644
1645                         nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1646                         nand->cs[i].rb.id = val;
1647                 } else {
1648                         gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev,
1649                                                         "rb", i, &np->fwnode,
1650                                                         GPIOD_IN, "nand-rb");
1651                         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1652                                 dev_err(nc->dev,
1653                                         "Failed to get R/B gpio (err = %ld)\n",
1654                                         PTR_ERR(gpio));
1655                                 return ERR_CAST(gpio);
1656                         }
1657
1658                         if (!IS_ERR(gpio)) {
1659                                 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1660                                 nand->cs[i].rb.gpio = gpio;
1661                         }
1662                 }
1663
1664                 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "cs",
1665                                                               i, &np->fwnode,
1666                                                               GPIOD_OUT_HIGH,
1667                                                               "nand-cs");
1668                 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1669                         dev_err(nc->dev,
1670                                 "Failed to get CS gpio (err = %ld)\n",
1671                                 PTR_ERR(gpio));
1672                         return ERR_CAST(gpio);
1673                 }
1674
1675                 if (!IS_ERR(gpio))
1676                         nand->cs[i].csgpio = gpio;
1677         }
1678
1679         nand_set_flash_node(&nand->base, np);
1680
1681         return nand;
1682 }
1683
1684 static int
1685 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1686                                struct atmel_nand *nand)
1687 {
1688         struct nand_chip *chip = &nand->base;
1689         struct mtd_info *mtd = nand_to_mtd(chip);
1690         int ret;
1691
1692         /* No card inserted, skip this NAND. */
1693         if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1694                 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1695                 return 0;
1696         }
1697
1698         nc->caps->ops->nand_init(nc, nand);
1699
1700         ret = nand_scan(chip, nand->numcs);
1701         if (ret) {
1702                 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1703                 return ret;
1704         }
1705
1706         ret = mtd_device_register(mtd, NULL, 0);
1707         if (ret) {
1708                 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1709                 nand_cleanup(chip);
1710                 return ret;
1711         }
1712
1713         list_add_tail(&nand->node, &nc->chips);
1714
1715         return 0;
1716 }
1717
1718 static int
1719 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1720 {
1721         struct atmel_nand *nand, *tmp;
1722         int ret;
1723
1724         list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1725                 ret = atmel_nand_controller_remove_nand(nand);
1726                 if (ret)
1727                         return ret;
1728         }
1729
1730         return 0;
1731 }
1732
1733 static int
1734 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1735 {
1736         struct device *dev = nc->dev;
1737         struct platform_device *pdev = to_platform_device(dev);
1738         struct atmel_nand *nand;
1739         struct gpio_desc *gpio;
1740         struct resource *res;
1741
1742         /*
1743          * Legacy bindings only allow connecting a single NAND with a unique CS
1744          * line to the controller.
1745          */
1746         nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1747                             GFP_KERNEL);
1748         if (!nand)
1749                 return -ENOMEM;
1750
1751         nand->numcs = 1;
1752
1753         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1754         nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1755         if (IS_ERR(nand->cs[0].io.virt))
1756                 return PTR_ERR(nand->cs[0].io.virt);
1757
1758         nand->cs[0].io.dma = res->start;
1759
1760         /*
1761          * The old driver was hardcoding the CS id to 3 for all sama5
1762          * controllers. Since this id is only meaningful for the sama5
1763          * controller we can safely assign this id to 3 no matter the
1764          * controller.
1765          * If one wants to connect a NAND to a different CS line, he will
1766          * have to use the new bindings.
1767          */
1768         nand->cs[0].id = 3;
1769
1770         /* R/B GPIO. */
1771         gpio = devm_gpiod_get_index_optional(dev, NULL, 0,  GPIOD_IN);
1772         if (IS_ERR(gpio)) {
1773                 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1774                         PTR_ERR(gpio));
1775                 return PTR_ERR(gpio);
1776         }
1777
1778         if (gpio) {
1779                 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1780                 nand->cs[0].rb.gpio = gpio;
1781         }
1782
1783         /* CS GPIO. */
1784         gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1785         if (IS_ERR(gpio)) {
1786                 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1787                         PTR_ERR(gpio));
1788                 return PTR_ERR(gpio);
1789         }
1790
1791         nand->cs[0].csgpio = gpio;
1792
1793         /* Card detect GPIO. */
1794         gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1795         if (IS_ERR(gpio)) {
1796                 dev_err(dev,
1797                         "Failed to get detect gpio (err = %ld)\n",
1798                         PTR_ERR(gpio));
1799                 return PTR_ERR(gpio);
1800         }
1801
1802         nand->cdgpio = gpio;
1803
1804         nand_set_flash_node(&nand->base, nc->dev->of_node);
1805
1806         return atmel_nand_controller_add_nand(nc, nand);
1807 }
1808
1809 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1810 {
1811         struct device_node *np, *nand_np;
1812         struct device *dev = nc->dev;
1813         int ret, reg_cells;
1814         u32 val;
1815
1816         /* We do not retrieve the SMC syscon when parsing old DTs. */
1817         if (nc->caps->legacy_of_bindings)
1818                 return atmel_nand_controller_legacy_add_nands(nc);
1819
1820         np = dev->of_node;
1821
1822         ret = of_property_read_u32(np, "#address-cells", &val);
1823         if (ret) {
1824                 dev_err(dev, "missing #address-cells property\n");
1825                 return ret;
1826         }
1827
1828         reg_cells = val;
1829
1830         ret = of_property_read_u32(np, "#size-cells", &val);
1831         if (ret) {
1832                 dev_err(dev, "missing #size-cells property\n");
1833                 return ret;
1834         }
1835
1836         reg_cells += val;
1837
1838         for_each_child_of_node(np, nand_np) {
1839                 struct atmel_nand *nand;
1840
1841                 nand = atmel_nand_create(nc, nand_np, reg_cells);
1842                 if (IS_ERR(nand)) {
1843                         ret = PTR_ERR(nand);
1844                         goto err;
1845                 }
1846
1847                 ret = atmel_nand_controller_add_nand(nc, nand);
1848                 if (ret)
1849                         goto err;
1850         }
1851
1852         return 0;
1853
1854 err:
1855         atmel_nand_controller_remove_nands(nc);
1856
1857         return ret;
1858 }
1859
1860 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1861 {
1862         if (nc->dmac)
1863                 dma_release_channel(nc->dmac);
1864
1865         clk_put(nc->mck);
1866 }
1867
1868 static const struct of_device_id atmel_matrix_of_ids[] = {
1869         {
1870                 .compatible = "atmel,at91sam9260-matrix",
1871                 .data = (void *)AT91SAM9260_MATRIX_EBICSA,
1872         },
1873         {
1874                 .compatible = "atmel,at91sam9261-matrix",
1875                 .data = (void *)AT91SAM9261_MATRIX_EBICSA,
1876         },
1877         {
1878                 .compatible = "atmel,at91sam9263-matrix",
1879                 .data = (void *)AT91SAM9263_MATRIX_EBI0CSA,
1880         },
1881         {
1882                 .compatible = "atmel,at91sam9rl-matrix",
1883                 .data = (void *)AT91SAM9RL_MATRIX_EBICSA,
1884         },
1885         {
1886                 .compatible = "atmel,at91sam9g45-matrix",
1887                 .data = (void *)AT91SAM9G45_MATRIX_EBICSA,
1888         },
1889         {
1890                 .compatible = "atmel,at91sam9n12-matrix",
1891                 .data = (void *)AT91SAM9N12_MATRIX_EBICSA,
1892         },
1893         {
1894                 .compatible = "atmel,at91sam9x5-matrix",
1895                 .data = (void *)AT91SAM9X5_MATRIX_EBICSA,
1896         },
1897         { /* sentinel */ },
1898 };
1899
1900 static int atmel_nand_attach_chip(struct nand_chip *chip)
1901 {
1902         struct atmel_nand_controller *nc = to_nand_controller(chip->controller);
1903         struct atmel_nand *nand = to_atmel_nand(chip);
1904         struct mtd_info *mtd = nand_to_mtd(chip);
1905         int ret;
1906
1907         ret = nc->caps->ops->ecc_init(chip);
1908         if (ret)
1909                 return ret;
1910
1911         if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1912                 /*
1913                  * We keep the MTD name unchanged to avoid breaking platforms
1914                  * where the MTD cmdline parser is used and the bootloader
1915                  * has not been updated to use the new naming scheme.
1916                  */
1917                 mtd->name = "atmel_nand";
1918         } else if (!mtd->name) {
1919                 /*
1920                  * If the new bindings are used and the bootloader has not been
1921                  * updated to pass a new mtdparts parameter on the cmdline, you
1922                  * should define the following property in your nand node:
1923                  *
1924                  *      label = "atmel_nand";
1925                  *
1926                  * This way, mtd->name will be set by the core when
1927                  * nand_set_flash_node() is called.
1928                  */
1929                 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
1930                                            "%s:nand.%d", dev_name(nc->dev),
1931                                            nand->cs[0].id);
1932                 if (!mtd->name) {
1933                         dev_err(nc->dev, "Failed to allocate mtd->name\n");
1934                         return -ENOMEM;
1935                 }
1936         }
1937
1938         return 0;
1939 }
1940
1941 static const struct nand_controller_ops atmel_nand_controller_ops = {
1942         .attach_chip = atmel_nand_attach_chip,
1943 };
1944
1945 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
1946                                 struct platform_device *pdev,
1947                                 const struct atmel_nand_controller_caps *caps)
1948 {
1949         struct device *dev = &pdev->dev;
1950         struct device_node *np = dev->of_node;
1951         int ret;
1952
1953         nand_controller_init(&nc->base);
1954         nc->base.ops = &atmel_nand_controller_ops;
1955         INIT_LIST_HEAD(&nc->chips);
1956         nc->dev = dev;
1957         nc->caps = caps;
1958
1959         platform_set_drvdata(pdev, nc);
1960
1961         nc->pmecc = devm_atmel_pmecc_get(dev);
1962         if (IS_ERR(nc->pmecc)) {
1963                 ret = PTR_ERR(nc->pmecc);
1964                 if (ret != -EPROBE_DEFER)
1965                         dev_err(dev, "Could not get PMECC object (err = %d)\n",
1966                                 ret);
1967                 return ret;
1968         }
1969
1970         if (nc->caps->has_dma && !atmel_nand_avoid_dma) {
1971                 dma_cap_mask_t mask;
1972
1973                 dma_cap_zero(mask);
1974                 dma_cap_set(DMA_MEMCPY, mask);
1975
1976                 nc->dmac = dma_request_channel(mask, NULL, NULL);
1977                 if (!nc->dmac)
1978                         dev_err(nc->dev, "Failed to request DMA channel\n");
1979         }
1980
1981         /* We do not retrieve the SMC syscon when parsing old DTs. */
1982         if (nc->caps->legacy_of_bindings)
1983                 return 0;
1984
1985         nc->mck = of_clk_get(dev->parent->of_node, 0);
1986         if (IS_ERR(nc->mck)) {
1987                 dev_err(dev, "Failed to retrieve MCK clk\n");
1988                 ret = PTR_ERR(nc->mck);
1989                 goto out_release_dma;
1990         }
1991
1992         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
1993         if (!np) {
1994                 dev_err(dev, "Missing or invalid atmel,smc property\n");
1995                 ret = -EINVAL;
1996                 goto out_release_dma;
1997         }
1998
1999         nc->smc = syscon_node_to_regmap(np);
2000         of_node_put(np);
2001         if (IS_ERR(nc->smc)) {
2002                 ret = PTR_ERR(nc->smc);
2003                 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
2004                 goto out_release_dma;
2005         }
2006
2007         return 0;
2008
2009 out_release_dma:
2010         if (nc->dmac)
2011                 dma_release_channel(nc->dmac);
2012
2013         return ret;
2014 }
2015
2016 static int
2017 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
2018 {
2019         struct device *dev = nc->base.dev;
2020         const struct of_device_id *match;
2021         struct device_node *np;
2022         int ret;
2023
2024         /* We do not retrieve the matrix syscon when parsing old DTs. */
2025         if (nc->base.caps->legacy_of_bindings)
2026                 return 0;
2027
2028         np = of_parse_phandle(dev->parent->of_node, "atmel,matrix", 0);
2029         if (!np)
2030                 return 0;
2031
2032         match = of_match_node(atmel_matrix_of_ids, np);
2033         if (!match) {
2034                 of_node_put(np);
2035                 return 0;
2036         }
2037
2038         nc->matrix = syscon_node_to_regmap(np);
2039         of_node_put(np);
2040         if (IS_ERR(nc->matrix)) {
2041                 ret = PTR_ERR(nc->matrix);
2042                 dev_err(dev, "Could not get Matrix regmap (err = %d)\n", ret);
2043                 return ret;
2044         }
2045
2046         nc->ebi_csa_offs = (uintptr_t)match->data;
2047
2048         /*
2049          * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2050          * add 4 to ->ebi_csa_offs.
2051          */
2052         if (of_device_is_compatible(dev->parent->of_node,
2053                                     "atmel,at91sam9263-ebi1"))
2054                 nc->ebi_csa_offs += 4;
2055
2056         return 0;
2057 }
2058
2059 static int
2060 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2061 {
2062         struct regmap_config regmap_conf = {
2063                 .reg_bits = 32,
2064                 .val_bits = 32,
2065                 .reg_stride = 4,
2066         };
2067
2068         struct device *dev = nc->base.dev;
2069         struct device_node *nand_np, *nfc_np;
2070         void __iomem *iomem;
2071         struct resource res;
2072         int ret;
2073
2074         nand_np = dev->of_node;
2075         nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc");
2076         if (!nfc_np) {
2077                 dev_err(dev, "Could not find device node for sama5d3-nfc\n");
2078                 return -ENODEV;
2079         }
2080
2081         nc->clk = of_clk_get(nfc_np, 0);
2082         if (IS_ERR(nc->clk)) {
2083                 ret = PTR_ERR(nc->clk);
2084                 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
2085                         ret);
2086                 goto out;
2087         }
2088
2089         ret = clk_prepare_enable(nc->clk);
2090         if (ret) {
2091                 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
2092                         ret);
2093                 goto out;
2094         }
2095
2096         nc->irq = of_irq_get(nand_np, 0);
2097         if (nc->irq <= 0) {
2098                 ret = nc->irq ?: -ENXIO;
2099                 if (ret != -EPROBE_DEFER)
2100                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2101                                 ret);
2102                 goto out;
2103         }
2104
2105         ret = of_address_to_resource(nfc_np, 0, &res);
2106         if (ret) {
2107                 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
2108                         ret);
2109                 goto out;
2110         }
2111
2112         iomem = devm_ioremap_resource(dev, &res);
2113         if (IS_ERR(iomem)) {
2114                 ret = PTR_ERR(iomem);
2115                 goto out;
2116         }
2117
2118         regmap_conf.name = "nfc-io";
2119         regmap_conf.max_register = resource_size(&res) - 4;
2120         nc->io = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2121         if (IS_ERR(nc->io)) {
2122                 ret = PTR_ERR(nc->io);
2123                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2124                         ret);
2125                 goto out;
2126         }
2127
2128         ret = of_address_to_resource(nfc_np, 1, &res);
2129         if (ret) {
2130                 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
2131                         ret);
2132                 goto out;
2133         }
2134
2135         iomem = devm_ioremap_resource(dev, &res);
2136         if (IS_ERR(iomem)) {
2137                 ret = PTR_ERR(iomem);
2138                 goto out;
2139         }
2140
2141         regmap_conf.name = "smc";
2142         regmap_conf.max_register = resource_size(&res) - 4;
2143         nc->base.smc = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2144         if (IS_ERR(nc->base.smc)) {
2145                 ret = PTR_ERR(nc->base.smc);
2146                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2147                         ret);
2148                 goto out;
2149         }
2150
2151         ret = of_address_to_resource(nfc_np, 2, &res);
2152         if (ret) {
2153                 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
2154                         ret);
2155                 goto out;
2156         }
2157
2158         nc->sram.virt = devm_ioremap_resource(dev, &res);
2159         if (IS_ERR(nc->sram.virt)) {
2160                 ret = PTR_ERR(nc->sram.virt);
2161                 goto out;
2162         }
2163
2164         nc->sram.dma = res.start;
2165
2166 out:
2167         of_node_put(nfc_np);
2168
2169         return ret;
2170 }
2171
2172 static int
2173 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2174 {
2175         struct device *dev = nc->base.dev;
2176         struct device_node *np;
2177         int ret;
2178
2179         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2180         if (!np) {
2181                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2182                 return -EINVAL;
2183         }
2184
2185         nc->hsmc_layout = atmel_hsmc_get_reg_layout(np);
2186
2187         nc->irq = of_irq_get(np, 0);
2188         of_node_put(np);
2189         if (nc->irq <= 0) {
2190                 ret = nc->irq ?: -ENXIO;
2191                 if (ret != -EPROBE_DEFER)
2192                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2193                                 ret);
2194                 return ret;
2195         }
2196
2197         np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
2198         if (!np) {
2199                 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
2200                 return -EINVAL;
2201         }
2202
2203         nc->io = syscon_node_to_regmap(np);
2204         of_node_put(np);
2205         if (IS_ERR(nc->io)) {
2206                 ret = PTR_ERR(nc->io);
2207                 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
2208                 return ret;
2209         }
2210
2211         nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2212                                          "atmel,nfc-sram", 0);
2213         if (!nc->sram.pool) {
2214                 dev_err(nc->base.dev, "Missing SRAM\n");
2215                 return -ENOMEM;
2216         }
2217
2218         nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool,
2219                                                            ATMEL_NFC_SRAM_SIZE,
2220                                                            &nc->sram.dma);
2221         if (!nc->sram.virt) {
2222                 dev_err(nc->base.dev,
2223                         "Could not allocate memory from the NFC SRAM pool\n");
2224                 return -ENOMEM;
2225         }
2226
2227         return 0;
2228 }
2229
2230 static int
2231 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2232 {
2233         struct atmel_hsmc_nand_controller *hsmc_nc;
2234         int ret;
2235
2236         ret = atmel_nand_controller_remove_nands(nc);
2237         if (ret)
2238                 return ret;
2239
2240         hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2241         if (hsmc_nc->sram.pool)
2242                 gen_pool_free(hsmc_nc->sram.pool,
2243                               (unsigned long)hsmc_nc->sram.virt,
2244                               ATMEL_NFC_SRAM_SIZE);
2245
2246         if (hsmc_nc->clk) {
2247                 clk_disable_unprepare(hsmc_nc->clk);
2248                 clk_put(hsmc_nc->clk);
2249         }
2250
2251         atmel_nand_controller_cleanup(nc);
2252
2253         return 0;
2254 }
2255
2256 static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
2257                                 const struct atmel_nand_controller_caps *caps)
2258 {
2259         struct device *dev = &pdev->dev;
2260         struct atmel_hsmc_nand_controller *nc;
2261         int ret;
2262
2263         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2264         if (!nc)
2265                 return -ENOMEM;
2266
2267         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2268         if (ret)
2269                 return ret;
2270
2271         if (caps->legacy_of_bindings)
2272                 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2273         else
2274                 ret = atmel_hsmc_nand_controller_init(nc);
2275
2276         if (ret)
2277                 return ret;
2278
2279         /* Make sure all irqs are masked before registering our IRQ handler. */
2280         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2281         ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2282                                IRQF_SHARED, "nfc", nc);
2283         if (ret) {
2284                 dev_err(dev,
2285                         "Could not get register NFC interrupt handler (err = %d)\n",
2286                         ret);
2287                 goto err;
2288         }
2289
2290         /* Initial NFC configuration. */
2291         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2292                      ATMEL_HSMC_NFC_CFG_DTO_MAX);
2293
2294         ret = atmel_nand_controller_add_nands(&nc->base);
2295         if (ret)
2296                 goto err;
2297
2298         return 0;
2299
2300 err:
2301         atmel_hsmc_nand_controller_remove(&nc->base);
2302
2303         return ret;
2304 }
2305
2306 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2307         .probe = atmel_hsmc_nand_controller_probe,
2308         .remove = atmel_hsmc_nand_controller_remove,
2309         .ecc_init = atmel_hsmc_nand_ecc_init,
2310         .nand_init = atmel_hsmc_nand_init,
2311         .setup_data_interface = atmel_hsmc_nand_setup_data_interface,
2312 };
2313
2314 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2315         .has_dma = true,
2316         .ale_offs = BIT(21),
2317         .cle_offs = BIT(22),
2318         .ops = &atmel_hsmc_nc_ops,
2319 };
2320
2321 /* Only used to parse old bindings. */
2322 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
2323         .has_dma = true,
2324         .ale_offs = BIT(21),
2325         .cle_offs = BIT(22),
2326         .ops = &atmel_hsmc_nc_ops,
2327         .legacy_of_bindings = true,
2328 };
2329
2330 static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2331                                 const struct atmel_nand_controller_caps *caps)
2332 {
2333         struct device *dev = &pdev->dev;
2334         struct atmel_smc_nand_controller *nc;
2335         int ret;
2336
2337         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2338         if (!nc)
2339                 return -ENOMEM;
2340
2341         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2342         if (ret)
2343                 return ret;
2344
2345         ret = atmel_smc_nand_controller_init(nc);
2346         if (ret)
2347                 return ret;
2348
2349         return atmel_nand_controller_add_nands(&nc->base);
2350 }
2351
2352 static int
2353 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2354 {
2355         int ret;
2356
2357         ret = atmel_nand_controller_remove_nands(nc);
2358         if (ret)
2359                 return ret;
2360
2361         atmel_nand_controller_cleanup(nc);
2362
2363         return 0;
2364 }
2365
2366 /*
2367  * The SMC reg layout of at91rm9200 is completely different which prevents us
2368  * from re-using atmel_smc_nand_setup_data_interface() for the
2369  * ->setup_data_interface() hook.
2370  * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2371  * ->setup_data_interface() unassigned.
2372  */
2373 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2374         .probe = atmel_smc_nand_controller_probe,
2375         .remove = atmel_smc_nand_controller_remove,
2376         .ecc_init = atmel_nand_ecc_init,
2377         .nand_init = atmel_smc_nand_init,
2378 };
2379
2380 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2381         .ale_offs = BIT(21),
2382         .cle_offs = BIT(22),
2383         .ops = &at91rm9200_nc_ops,
2384 };
2385
2386 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2387         .probe = atmel_smc_nand_controller_probe,
2388         .remove = atmel_smc_nand_controller_remove,
2389         .ecc_init = atmel_nand_ecc_init,
2390         .nand_init = atmel_smc_nand_init,
2391         .setup_data_interface = atmel_smc_nand_setup_data_interface,
2392 };
2393
2394 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2395         .ale_offs = BIT(21),
2396         .cle_offs = BIT(22),
2397         .ops = &atmel_smc_nc_ops,
2398 };
2399
2400 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2401         .ale_offs = BIT(22),
2402         .cle_offs = BIT(21),
2403         .ops = &atmel_smc_nc_ops,
2404 };
2405
2406 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2407         .has_dma = true,
2408         .ale_offs = BIT(21),
2409         .cle_offs = BIT(22),
2410         .ops = &atmel_smc_nc_ops,
2411 };
2412
2413 /* Only used to parse old bindings. */
2414 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2415         .ale_offs = BIT(21),
2416         .cle_offs = BIT(22),
2417         .ops = &atmel_smc_nc_ops,
2418         .legacy_of_bindings = true,
2419 };
2420
2421 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2422         .ale_offs = BIT(22),
2423         .cle_offs = BIT(21),
2424         .ops = &atmel_smc_nc_ops,
2425         .legacy_of_bindings = true,
2426 };
2427
2428 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2429         .has_dma = true,
2430         .ale_offs = BIT(21),
2431         .cle_offs = BIT(22),
2432         .ops = &atmel_smc_nc_ops,
2433         .legacy_of_bindings = true,
2434 };
2435
2436 static const struct of_device_id atmel_nand_controller_of_ids[] = {
2437         {
2438                 .compatible = "atmel,at91rm9200-nand-controller",
2439                 .data = &atmel_rm9200_nc_caps,
2440         },
2441         {
2442                 .compatible = "atmel,at91sam9260-nand-controller",
2443                 .data = &atmel_sam9260_nc_caps,
2444         },
2445         {
2446                 .compatible = "atmel,at91sam9261-nand-controller",
2447                 .data = &atmel_sam9261_nc_caps,
2448         },
2449         {
2450                 .compatible = "atmel,at91sam9g45-nand-controller",
2451                 .data = &atmel_sam9g45_nc_caps,
2452         },
2453         {
2454                 .compatible = "atmel,sama5d3-nand-controller",
2455                 .data = &atmel_sama5_nc_caps,
2456         },
2457         /* Support for old/deprecated bindings: */
2458         {
2459                 .compatible = "atmel,at91rm9200-nand",
2460                 .data = &atmel_rm9200_nand_caps,
2461         },
2462         {
2463                 .compatible = "atmel,sama5d4-nand",
2464                 .data = &atmel_rm9200_nand_caps,
2465         },
2466         {
2467                 .compatible = "atmel,sama5d2-nand",
2468                 .data = &atmel_rm9200_nand_caps,
2469         },
2470         { /* sentinel */ },
2471 };
2472 MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2473
2474 static int atmel_nand_controller_probe(struct platform_device *pdev)
2475 {
2476         const struct atmel_nand_controller_caps *caps;
2477
2478         if (pdev->id_entry)
2479                 caps = (void *)pdev->id_entry->driver_data;
2480         else
2481                 caps = of_device_get_match_data(&pdev->dev);
2482
2483         if (!caps) {
2484                 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2485                 return -EINVAL;
2486         }
2487
2488         if (caps->legacy_of_bindings) {
2489                 struct device_node *nfc_node;
2490                 u32 ale_offs = 21;
2491
2492                 /*
2493                  * If we are parsing legacy DT props and the DT contains a
2494                  * valid NFC node, forward the request to the sama5 logic.
2495                  */
2496                 nfc_node = of_get_compatible_child(pdev->dev.of_node,
2497                                                    "atmel,sama5d3-nfc");
2498                 if (nfc_node) {
2499                         caps = &atmel_sama5_nand_caps;
2500                         of_node_put(nfc_node);
2501                 }
2502
2503                 /*
2504                  * Even if the compatible says we are dealing with an
2505                  * at91rm9200 controller, the atmel,nand-has-dma specify that
2506                  * this controller supports DMA, which means we are in fact
2507                  * dealing with an at91sam9g45+ controller.
2508                  */
2509                 if (!caps->has_dma &&
2510                     of_property_read_bool(pdev->dev.of_node,
2511                                           "atmel,nand-has-dma"))
2512                         caps = &atmel_sam9g45_nand_caps;
2513
2514                 /*
2515                  * All SoCs except the at91sam9261 are assigning ALE to A21 and
2516                  * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2517                  * actually dealing with an at91sam9261 controller.
2518                  */
2519                 of_property_read_u32(pdev->dev.of_node,
2520                                      "atmel,nand-addr-offset", &ale_offs);
2521                 if (ale_offs != 21)
2522                         caps = &atmel_sam9261_nand_caps;
2523         }
2524
2525         return caps->ops->probe(pdev, caps);
2526 }
2527
2528 static int atmel_nand_controller_remove(struct platform_device *pdev)
2529 {
2530         struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2531
2532         return nc->caps->ops->remove(nc);
2533 }
2534
2535 static __maybe_unused int atmel_nand_controller_resume(struct device *dev)
2536 {
2537         struct atmel_nand_controller *nc = dev_get_drvdata(dev);
2538         struct atmel_nand *nand;
2539
2540         if (nc->pmecc)
2541                 atmel_pmecc_reset(nc->pmecc);
2542
2543         list_for_each_entry(nand, &nc->chips, node) {
2544                 int i;
2545
2546                 for (i = 0; i < nand->numcs; i++)
2547                         nand_reset(&nand->base, i);
2548         }
2549
2550         return 0;
2551 }
2552
2553 static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL,
2554                          atmel_nand_controller_resume);
2555
2556 static struct platform_driver atmel_nand_controller_driver = {
2557         .driver = {
2558                 .name = "atmel-nand-controller",
2559                 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2560                 .pm = &atmel_nand_controller_pm_ops,
2561         },
2562         .probe = atmel_nand_controller_probe,
2563         .remove = atmel_nand_controller_remove,
2564 };
2565 module_platform_driver(atmel_nand_controller_driver);
2566
2567 MODULE_LICENSE("GPL");
2568 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2569 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2570 MODULE_ALIAS("platform:atmel-nand-controller");