drivers/mtd/nand/raw/arasan-nand-controller.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Arasan NAND Flash Controller Driver
   4  *
   5  * Copyright (C) 2014 - 2020 Xilinx, Inc.
   6  * Author:
   7  *   Miquel Raynal <miquel.raynal@bootlin.com>
   8  * Original work (fully rewritten):
   9  *   Punnaiah Choudary Kalluri <punnaia@xilinx.com>
  10  *   Naga Sureshkumar Relli <nagasure@xilinx.com>
  11  */
  12
  13 #include <linux/bch.h>
  14 #include <linux/bitfield.h>
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/module.h>
  21 #include <linux/mtd/mtd.h>
  22 #include <linux/mtd/partitions.h>
  23 #include <linux/mtd/rawnand.h>
  24 #include <linux/of.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27
  28 #define PKT_REG                         0x00
  29 #define   PKT_SIZE(x)                   FIELD_PREP(GENMASK(10, 0), (x))
  30 #define   PKT_STEPS(x)                  FIELD_PREP(GENMASK(23, 12), (x))
  31
  32 #define MEM_ADDR1_REG                   0x04
  33
  34 #define MEM_ADDR2_REG                   0x08
  35 #define   ADDR2_STRENGTH(x)             FIELD_PREP(GENMASK(27, 25), (x))
  36 #define   ADDR2_CS(x)                   FIELD_PREP(GENMASK(31, 30), (x))
  37
  38 #define CMD_REG                         0x0C
  39 #define   CMD_1(x)                      FIELD_PREP(GENMASK(7, 0), (x))
  40 #define   CMD_2(x)                      FIELD_PREP(GENMASK(15, 8), (x))
  41 #define   CMD_PAGE_SIZE(x)              FIELD_PREP(GENMASK(25, 23), (x))
  42 #define   CMD_DMA_ENABLE                BIT(27)
  43 #define   CMD_NADDRS(x)                 FIELD_PREP(GENMASK(30, 28), (x))
  44 #define   CMD_ECC_ENABLE                BIT(31)
  45
  46 #define PROG_REG                        0x10
  47 #define   PROG_PGRD                     BIT(0)
  48 #define   PROG_ERASE                    BIT(2)
  49 #define   PROG_STATUS                   BIT(3)
  50 #define   PROG_PGPROG                   BIT(4)
  51 #define   PROG_RDID                     BIT(6)
  52 #define   PROG_RDPARAM                  BIT(7)
  53 #define   PROG_RST                      BIT(8)
  54 #define   PROG_GET_FEATURE              BIT(9)
  55 #define   PROG_SET_FEATURE              BIT(10)
  56
  57 #define INTR_STS_EN_REG                 0x14
  58 #define INTR_SIG_EN_REG                 0x18
  59 #define INTR_STS_REG                    0x1C
  60 #define   WRITE_READY                   BIT(0)
  61 #define   READ_READY                    BIT(1)
  62 #define   XFER_COMPLETE                 BIT(2)
  63 #define   DMA_BOUNDARY                  BIT(6)
  64 #define   EVENT_MASK                    GENMASK(7, 0)
  65
  66 #define READY_STS_REG                   0x20
  67
  68 #define DMA_ADDR0_REG                   0x50
  69 #define DMA_ADDR1_REG                   0x24
  70
  71 #define FLASH_STS_REG                   0x28
  72
  73 #define DATA_PORT_REG                   0x30
  74
  75 #define ECC_CONF_REG                    0x34
  76 #define   ECC_CONF_COL(x)               FIELD_PREP(GENMASK(15, 0), (x))
  77 #define   ECC_CONF_LEN(x)               FIELD_PREP(GENMASK(26, 16), (x))
  78 #define   ECC_CONF_BCH_EN               BIT(27)
  79
  80 #define ECC_ERR_CNT_REG                 0x38
  81 #define   GET_PKT_ERR_CNT(x)            FIELD_GET(GENMASK(7, 0), (x))
  82 #define   GET_PAGE_ERR_CNT(x)           FIELD_GET(GENMASK(16, 8), (x))
  83
  84 #define ECC_SP_REG                      0x3C
  85 #define   ECC_SP_CMD1(x)                FIELD_PREP(GENMASK(7, 0), (x))
  86 #define   ECC_SP_CMD2(x)                FIELD_PREP(GENMASK(15, 8), (x))
  87 #define   ECC_SP_ADDRS(x)               FIELD_PREP(GENMASK(30, 28), (x))
  88
  89 #define ECC_1ERR_CNT_REG                0x40
  90 #define ECC_2ERR_CNT_REG                0x44
  91
  92 #define DATA_INTERFACE_REG              0x6C
  93 #define   DIFACE_SDR_MODE(x)            FIELD_PREP(GENMASK(2, 0), (x))
  94 #define   DIFACE_DDR_MODE(x)            FIELD_PREP(GENMASK(5, 3), (x))
  95 #define   DIFACE_SDR                    0
  96 #define   DIFACE_NVDDR                  BIT(9)
  97
  98 #define ANFC_MAX_CS                     2
  99 #define ANFC_DFLT_TIMEOUT_US            1000000
 100 #define ANFC_MAX_CHUNK_SIZE             SZ_1M
 101 #define ANFC_MAX_PARAM_SIZE             SZ_4K
 102 #define ANFC_MAX_STEPS                  SZ_2K
 103 #define ANFC_MAX_PKT_SIZE               (SZ_2K - 1)
 104 #define ANFC_MAX_ADDR_CYC               5U
 105 #define ANFC_RSVD_ECC_BYTES             21
 106
 107 #define ANFC_XLNX_SDR_DFLT_CORE_CLK     100000000
 108 #define ANFC_XLNX_SDR_HS_CORE_CLK       80000000
 109
 110 /**
 111  * struct anfc_op - Defines how to execute an operation
 112  * @pkt_reg: Packet register
 113  * @addr1_reg: Memory address 1 register
 114  * @addr2_reg: Memory address 2 register
 115  * @cmd_reg: Command register
 116  * @prog_reg: Program register
 117  * @steps: Number of "packets" to read/write
 118  * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin
 119  * @len: Data transfer length
 120  * @read: Data transfer direction from the controller point of view
 121  */
 122 struct anfc_op {
 123         u32 pkt_reg;
 124         u32 addr1_reg;
 125         u32 addr2_reg;
 126         u32 cmd_reg;
 127         u32 prog_reg;
 128         int steps;
 129         unsigned int rdy_timeout_ms;
 130         unsigned int len;
 131         bool read;
 132         u8 *buf;
 133 };
 134
 135 /**
 136  * struct anand - Defines the NAND chip related information
 137  * @node:               Used to store NAND chips into a list
 138  * @chip:               NAND chip information structure
 139  * @cs:                 Chip select line
 140  * @rb:                 Ready-busy line
 141  * @page_sz:            Register value of the page_sz field to use
 142  * @clk:                Expected clock frequency to use
 143  * @timings:            Data interface timing mode to use
 144  * @ecc_conf:           Hardware ECC configuration value
 145  * @strength:           Register value of the ECC strength
 146  * @raddr_cycles:       Row address cycle information
 147  * @caddr_cycles:       Column address cycle information
 148  * @ecc_bits:           Exact number of ECC bits per syndrome
 149  * @ecc_total:          Total number of ECC bytes
 150  * @errloc:             Array of errors located with soft BCH
 151  * @hw_ecc:             Buffer to store syndromes computed by hardware
 152  * @bch:                BCH structure
 153  */
 154 struct anand {
 155         struct list_head node;
 156         struct nand_chip chip;
 157         unsigned int cs;
 158         unsigned int rb;
 159         unsigned int page_sz;
 160         unsigned long clk;
 161         u32 timings;
 162         u32 ecc_conf;
 163         u32 strength;
 164         u16 raddr_cycles;
 165         u16 caddr_cycles;
 166         unsigned int ecc_bits;
 167         unsigned int ecc_total;
 168         unsigned int *errloc;
 169         u8 *hw_ecc;
 170         struct bch_control *bch;
 171 };
 172
 173 /**
 174  * struct arasan_nfc - Defines the Arasan NAND flash controller driver instance
 175  * @dev:                Pointer to the device structure
 176  * @base:               Remapped register area
 177  * @controller_clk:             Pointer to the system clock
 178  * @bus_clk:            Pointer to the flash clock
 179  * @controller:         Base controller structure
 180  * @chips:              List of all NAND chips attached to the controller
 181  * @assigned_cs:        Bitmask describing already assigned CS lines
 182  * @cur_clk:            Current clock rate
 183  */
 184 struct arasan_nfc {
 185         struct device *dev;
 186         void __iomem *base;
 187         struct clk *controller_clk;
 188         struct clk *bus_clk;
 189         struct nand_controller controller;
 190         struct list_head chips;
 191         unsigned long assigned_cs;
 192         unsigned int cur_clk;
 193 };
 194
 195 static struct anand *to_anand(struct nand_chip *nand)
 196 {
 197         return container_of(nand, struct anand, chip);
 198 }
 199
 200 static struct arasan_nfc *to_anfc(struct nand_controller *ctrl)
 201 {
 202         return container_of(ctrl, struct arasan_nfc, controller);
 203 }
 204
 205 static int anfc_wait_for_event(struct arasan_nfc *nfc, unsigned int event)
 206 {
 207         u32 val;
 208         int ret;
 209
 210         ret = readl_relaxed_poll_timeout(nfc->base + INTR_STS_REG, val,
 211                                          val & event, 0,
 212                                          ANFC_DFLT_TIMEOUT_US);
 213         if (ret) {
 214                 dev_err(nfc->dev, "Timeout waiting for event 0x%x\n", event);
 215                 return -ETIMEDOUT;
 216         }
 217
 218         writel_relaxed(event, nfc->base + INTR_STS_REG);
 219
 220         return 0;
 221 }
 222
 223 static int anfc_wait_for_rb(struct arasan_nfc *nfc, struct nand_chip *chip,
 224                             unsigned int timeout_ms)
 225 {
 226         struct anand *anand = to_anand(chip);
 227         u32 val;
 228         int ret;
 229
 230         /* There is no R/B interrupt, we must poll a register */
 231         ret = readl_relaxed_poll_timeout(nfc->base + READY_STS_REG, val,
 232                                          val & BIT(anand->rb),
 233                                          1, timeout_ms * 1000);
 234         if (ret) {
 235                 dev_err(nfc->dev, "Timeout waiting for R/B 0x%x\n",
 236                         readl_relaxed(nfc->base + READY_STS_REG));
 237                 return -ETIMEDOUT;
 238         }
 239
 240         return 0;
 241 }
 242
 243 static void anfc_trigger_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)
 244 {
 245         writel_relaxed(nfc_op->pkt_reg, nfc->base + PKT_REG);
 246         writel_relaxed(nfc_op->addr1_reg, nfc->base + MEM_ADDR1_REG);
 247         writel_relaxed(nfc_op->addr2_reg, nfc->base + MEM_ADDR2_REG);
 248         writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG);
 249         writel_relaxed(nfc_op->prog_reg, nfc->base + PROG_REG);
 250 }
 251
 252 static int anfc_pkt_len_config(unsigned int len, unsigned int *steps,
 253                                unsigned int *pktsize)
 254 {
 255         unsigned int nb, sz;
 256
 257         for (nb = 1; nb < ANFC_MAX_STEPS; nb *= 2) {
 258                 sz = len / nb;
 259                 if (sz <= ANFC_MAX_PKT_SIZE)
 260                         break;
 261         }
 262
 263         if (sz * nb != len)
 264                 return -ENOTSUPP;
 265
 266         if (steps)
 267                 *steps = nb;
 268
 269         if (pktsize)
 270                 *pktsize = sz;
 271
 272         return 0;
 273 }
 274
 275 static int anfc_select_target(struct nand_chip *chip, int target)
 276 {
 277         struct anand *anand = to_anand(chip);
 278         struct arasan_nfc *nfc = to_anfc(chip->controller);
 279         int ret;
 280
 281         /* Update the controller timings and the potential ECC configuration */
 282         writel_relaxed(anand->timings, nfc->base + DATA_INTERFACE_REG);
 283
 284         /* Update clock frequency */
 285         if (nfc->cur_clk != anand->clk) {
 286                 clk_disable_unprepare(nfc->bus_clk);
 287                 ret = clk_set_rate(nfc->bus_clk, anand->clk);
 288                 if (ret) {
 289                         dev_err(nfc->dev, "Failed to change clock rate\n");
 290                         return ret;
 291                 }
 292
 293                 ret = clk_prepare_enable(nfc->bus_clk);
 294                 if (ret) {
 295                         dev_err(nfc->dev,
 296                                 "Failed to re-enable the bus clock\n");
 297                         return ret;
 298                 }
 299
 300                 nfc->cur_clk = anand->clk;
 301         }
 302
 303         return 0;
 304 }
 305
 306 /*
 307  * When using the embedded hardware ECC engine, the controller is in charge of
 308  * feeding the engine with, first, the ECC residue present in the data array.
 309  * A typical read operation is:
 310  * 1/ Assert the read operation by sending the relevant command/address cycles
 311  *    but targeting the column of the first ECC bytes in the OOB area instead of
 312  *    the main data directly.
 313  * 2/ After having read the relevant number of ECC bytes, the controller uses
 314  *    the RNDOUT/RNDSTART commands which are set into the "ECC Spare Command
 315  *    Register" to move the pointer back at the beginning of the main data.
 316  * 3/ It will read the content of the main area for a given size (pktsize) and
 317  *    will feed the ECC engine with this buffer again.
 318  * 4/ The ECC engine derives the ECC bytes for the given data and compare them
 319  *    with the ones already received. It eventually trigger status flags and
 320  *    then set the "Buffer Read Ready" flag.
 321  * 5/ The corrected data is then available for reading from the data port
 322  *    register.
 323  *
 324  * The hardware BCH ECC engine is known to be inconstent in BCH mode and never
 325  * reports uncorrectable errors. Because of this bug, we have to use the
 326  * software BCH implementation in the read path.
 327  */
 328 static int anfc_read_page_hw_ecc(struct nand_chip *chip, u8 *buf,
 329                                  int oob_required, int page)
 330 {
 331         struct arasan_nfc *nfc = to_anfc(chip->controller);
 332         struct mtd_info *mtd = nand_to_mtd(chip);
 333         struct anand *anand = to_anand(chip);
 334         unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0);
 335         unsigned int max_bitflips = 0;
 336         dma_addr_t dma_addr;
 337         int step, ret;
 338         struct anfc_op nfc_op = {
 339                 .pkt_reg =
 340                         PKT_SIZE(chip->ecc.size) |
 341                         PKT_STEPS(chip->ecc.steps),
 342                 .addr1_reg =
 343                         (page & 0xFF) << (8 * (anand->caddr_cycles)) |
 344                         (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))),
 345                 .addr2_reg =
 346                         ((page >> 16) & 0xFF) |
 347                         ADDR2_STRENGTH(anand->strength) |
 348                         ADDR2_CS(anand->cs),
 349                 .cmd_reg =
 350                         CMD_1(NAND_CMD_READ0) |
 351                         CMD_2(NAND_CMD_READSTART) |
 352                         CMD_PAGE_SIZE(anand->page_sz) |
 353                         CMD_DMA_ENABLE |
 354                         CMD_NADDRS(anand->caddr_cycles +
 355                                    anand->raddr_cycles),
 356                 .prog_reg = PROG_PGRD,
 357         };
 358
 359         dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_FROM_DEVICE);
 360         if (dma_mapping_error(nfc->dev, dma_addr)) {
 361                 dev_err(nfc->dev, "Buffer mapping error");
 362                 return -EIO;
 363         }
 364
 365         writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
 366         writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);
 367
 368         anfc_trigger_op(nfc, &nfc_op);
 369
 370         ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
 371         dma_unmap_single(nfc->dev, dma_addr, len, DMA_FROM_DEVICE);
 372         if (ret) {
 373                 dev_err(nfc->dev, "Error reading page %d\n", page);
 374                 return ret;
 375         }
 376
 377         /* Store the raw OOB bytes as well */
 378         ret = nand_change_read_column_op(chip, mtd->writesize, chip->oob_poi,
 379                                          mtd->oobsize, 0);
 380         if (ret)
 381                 return ret;
 382
 383         /*
 384          * For each step, compute by softare the BCH syndrome over the raw data.
 385          * Compare the theoretical amount of errors and compare with the
 386          * hardware engine feedback.
 387          */
 388         for (step = 0; step < chip->ecc.steps; step++) {
 389                 u8 *raw_buf = &buf[step * chip->ecc.size];
 390                 unsigned int bit, byte;
 391                 int bf, i;
 392
 393                 /* Extract the syndrome, it is not necessarily aligned */
 394                 memset(anand->hw_ecc, 0, chip->ecc.bytes);
 395                 nand_extract_bits(anand->hw_ecc, 0,
 396                                   &chip->oob_poi[mtd->oobsize - anand->ecc_total],
 397                                   anand->ecc_bits * step, anand->ecc_bits);
 398
 399                 bf = bch_decode(anand->bch, raw_buf, chip->ecc.size,
 400                                 anand->hw_ecc, NULL, NULL, anand->errloc);
 401                 if (!bf) {
 402                         continue;
 403                 } else if (bf > 0) {
 404                         for (i = 0; i < bf; i++) {
 405                                 /* Only correct the data, not the syndrome */
 406                                 if (anand->errloc[i] < (chip->ecc.size * 8)) {
 407                                         bit = BIT(anand->errloc[i] & 7);
 408                                         byte = anand->errloc[i] >> 3;
 409                                         raw_buf[byte] ^= bit;
 410                                 }
 411                         }
 412
 413                         mtd->ecc_stats.corrected += bf;
 414                         max_bitflips = max_t(unsigned int, max_bitflips, bf);
 415
 416                         continue;
 417                 }
 418
 419                 bf = nand_check_erased_ecc_chunk(raw_buf, chip->ecc.size,
 420                                                  NULL, 0, NULL, 0,
 421                                                  chip->ecc.strength);
 422                 if (bf > 0) {
 423                         mtd->ecc_stats.corrected += bf;
 424                         max_bitflips = max_t(unsigned int, max_bitflips, bf);
 425                         memset(raw_buf, 0xFF, chip->ecc.size);
 426                 } else if (bf < 0) {
 427                         mtd->ecc_stats.failed++;
 428                 }
 429         }
 430
 431         return 0;
 432 }
 433
 434 static int anfc_sel_read_page_hw_ecc(struct nand_chip *chip, u8 *buf,
 435                                      int oob_required, int page)
 436 {
 437         int ret;
 438
 439         ret = anfc_select_target(chip, chip->cur_cs);
 440         if (ret)
 441                 return ret;
 442
 443         return anfc_read_page_hw_ecc(chip, buf, oob_required, page);
 444 };
 445
 446 static int anfc_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf,
 447                                   int oob_required, int page)
 448 {
 449         struct anand *anand = to_anand(chip);
 450         struct arasan_nfc *nfc = to_anfc(chip->controller);
 451         struct mtd_info *mtd = nand_to_mtd(chip);
 452         unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0);
 453         dma_addr_t dma_addr;
 454         int ret;
 455         struct anfc_op nfc_op = {
 456                 .pkt_reg =
 457                         PKT_SIZE(chip->ecc.size) |
 458                         PKT_STEPS(chip->ecc.steps),
 459                 .addr1_reg =
 460                         (page & 0xFF) << (8 * (anand->caddr_cycles)) |
 461                         (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))),
 462                 .addr2_reg =
 463                         ((page >> 16) & 0xFF) |
 464                         ADDR2_STRENGTH(anand->strength) |
 465                         ADDR2_CS(anand->cs),
 466                 .cmd_reg =
 467                         CMD_1(NAND_CMD_SEQIN) |
 468                         CMD_2(NAND_CMD_PAGEPROG) |
 469                         CMD_PAGE_SIZE(anand->page_sz) |
 470                         CMD_DMA_ENABLE |
 471                         CMD_NADDRS(anand->caddr_cycles +
 472                                    anand->raddr_cycles) |
 473                         CMD_ECC_ENABLE,
 474                 .prog_reg = PROG_PGPROG,
 475         };
 476
 477         writel_relaxed(anand->ecc_conf, nfc->base + ECC_CONF_REG);
 478         writel_relaxed(ECC_SP_CMD1(NAND_CMD_RNDIN) |
 479                        ECC_SP_ADDRS(anand->caddr_cycles),
 480                        nfc->base + ECC_SP_REG);
 481
 482         dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_TO_DEVICE);
 483         if (dma_mapping_error(nfc->dev, dma_addr)) {
 484                 dev_err(nfc->dev, "Buffer mapping error");
 485                 return -EIO;
 486         }
 487
 488         writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
 489         writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);
 490
 491         anfc_trigger_op(nfc, &nfc_op);
 492         ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
 493         dma_unmap_single(nfc->dev, dma_addr, len, DMA_TO_DEVICE);
 494         if (ret) {
 495                 dev_err(nfc->dev, "Error writing page %d\n", page);
 496                 return ret;
 497         }
 498
 499         /* Spare data is not protected */
 500         if (oob_required)
 501                 ret = nand_write_oob_std(chip, page);
 502
 503         return ret;
 504 }
 505
 506 static int anfc_sel_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf,
 507                                       int oob_required, int page)
 508 {
 509         int ret;
 510
 511         ret = anfc_select_target(chip, chip->cur_cs);
 512         if (ret)
 513                 return ret;
 514
 515         return anfc_write_page_hw_ecc(chip, buf, oob_required, page);
 516 };
 517
 518 /* NAND framework ->exec_op() hooks and related helpers */
 519 static int anfc_parse_instructions(struct nand_chip *chip,
 520                                    const struct nand_subop *subop,
 521                                    struct anfc_op *nfc_op)
 522 {
 523         struct anand *anand = to_anand(chip);
 524         const struct nand_op_instr *instr = NULL;
 525         bool first_cmd = true;
 526         unsigned int op_id;
 527         int ret, i;
 528
 529         memset(nfc_op, 0, sizeof(*nfc_op));
 530         nfc_op->addr2_reg = ADDR2_CS(anand->cs);
 531         nfc_op->cmd_reg = CMD_PAGE_SIZE(anand->page_sz);
 532
 533         for (op_id = 0; op_id < subop->ninstrs; op_id++) {
 534                 unsigned int offset, naddrs, pktsize;
 535                 const u8 *addrs;
 536                 u8 *buf;
 537
 538                 instr = &subop->instrs[op_id];
 539
 540                 switch (instr->type) {
 541                 case NAND_OP_CMD_INSTR:
 542                         if (first_cmd)
 543                                 nfc_op->cmd_reg |= CMD_1(instr->ctx.cmd.opcode);
 544                         else
 545                                 nfc_op->cmd_reg |= CMD_2(instr->ctx.cmd.opcode);
 546
 547                         first_cmd = false;
 548                         break;
 549
 550                 case NAND_OP_ADDR_INSTR:
 551                         offset = nand_subop_get_addr_start_off(subop, op_id);
 552                         naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
 553                         addrs = &instr->ctx.addr.addrs[offset];
 554                         nfc_op->cmd_reg |= CMD_NADDRS(naddrs);
 555
 556                         for (i = 0; i < min(ANFC_MAX_ADDR_CYC, naddrs); i++) {
 557                                 if (i < 4)
 558                                         nfc_op->addr1_reg |= (u32)addrs[i] << i * 8;
 559                                 else
 560                                         nfc_op->addr2_reg |= addrs[i];
 561                         }
 562
 563                         break;
 564                 case NAND_OP_DATA_IN_INSTR:
 565                         nfc_op->read = true;
 566                         fallthrough;
 567                 case NAND_OP_DATA_OUT_INSTR:
 568                         offset = nand_subop_get_data_start_off(subop, op_id);
 569                         buf = instr->ctx.data.buf.in;
 570                         nfc_op->buf = &buf[offset];
 571                         nfc_op->len = nand_subop_get_data_len(subop, op_id);
 572                         ret = anfc_pkt_len_config(nfc_op->len, &nfc_op->steps,
 573                                                   &pktsize);
 574                         if (ret)
 575                                 return ret;
 576
 577                         /*
 578                          * Number of DATA cycles must be aligned on 4, this
 579                          * means the controller might read/write more than
 580                          * requested. This is harmless most of the time as extra
 581                          * DATA are discarded in the write path and read pointer
 582                          * adjusted in the read path.
 583                          *
 584                          * FIXME: The core should mark operations where
 585                          * reading/writing more is allowed so the exec_op()
 586                          * implementation can take the right decision when the
 587                          * alignment constraint is not met: adjust the number of
 588                          * DATA cycles when it's allowed, reject the operation
 589                          * otherwise.
 590                          */
 591                         nfc_op->pkt_reg |= PKT_SIZE(round_up(pktsize, 4)) |
 592                                            PKT_STEPS(nfc_op->steps);
 593                         break;
 594                 case NAND_OP_WAITRDY_INSTR:
 595                         nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;
 596                         break;
 597                 }
 598         }
 599
 600         return 0;
 601 }
 602
 603 static int anfc_rw_pio_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)
 604 {
 605         unsigned int dwords = (nfc_op->len / 4) / nfc_op->steps;
 606         unsigned int last_len = nfc_op->len % 4;
 607         unsigned int offset, dir;
 608         u8 *buf = nfc_op->buf;
 609         int ret, i;
 610
 611         for (i = 0; i < nfc_op->steps; i++) {
 612                 dir = nfc_op->read ? READ_READY : WRITE_READY;
 613                 ret = anfc_wait_for_event(nfc, dir);
 614                 if (ret) {
 615                         dev_err(nfc->dev, "PIO %s ready signal not received\n",
 616                                 nfc_op->read ? "Read" : "Write");
 617                         return ret;
 618                 }
 619
 620                 offset = i * (dwords * 4);
 621                 if (nfc_op->read)
 622                         ioread32_rep(nfc->base + DATA_PORT_REG, &buf[offset],
 623                                      dwords);
 624                 else
 625                         iowrite32_rep(nfc->base + DATA_PORT_REG, &buf[offset],
 626                                       dwords);
 627         }
 628
 629         if (last_len) {
 630                 u32 remainder;
 631
 632                 offset = nfc_op->len - last_len;
 633
 634                 if (nfc_op->read) {
 635                         remainder = readl_relaxed(nfc->base + DATA_PORT_REG);
 636                         memcpy(&buf[offset], &remainder, last_len);
 637                 } else {
 638                         memcpy(&remainder, &buf[offset], last_len);
 639                         writel_relaxed(remainder, nfc->base + DATA_PORT_REG);
 640                 }
 641         }
 642
 643         return anfc_wait_for_event(nfc, XFER_COMPLETE);
 644 }
 645
 646 static int anfc_misc_data_type_exec(struct nand_chip *chip,
 647                                     const struct nand_subop *subop,
 648                                     u32 prog_reg)
 649 {
 650         struct arasan_nfc *nfc = to_anfc(chip->controller);
 651         struct anfc_op nfc_op = {};
 652         int ret;
 653
 654         ret = anfc_parse_instructions(chip, subop, &nfc_op);
 655         if (ret)
 656                 return ret;
 657
 658         nfc_op.prog_reg = prog_reg;
 659         anfc_trigger_op(nfc, &nfc_op);
 660
 661         if (nfc_op.rdy_timeout_ms) {
 662                 ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
 663                 if (ret)
 664                         return ret;
 665         }
 666
 667         return anfc_rw_pio_op(nfc, &nfc_op);
 668 }
 669
 670 static int anfc_param_read_type_exec(struct nand_chip *chip,
 671                                      const struct nand_subop *subop)
 672 {
 673         return anfc_misc_data_type_exec(chip, subop, PROG_RDPARAM);
 674 }
 675
 676 static int anfc_data_read_type_exec(struct nand_chip *chip,
 677                                     const struct nand_subop *subop)
 678 {
 679         return anfc_misc_data_type_exec(chip, subop, PROG_PGRD);
 680 }
 681
 682 static int anfc_param_write_type_exec(struct nand_chip *chip,
 683                                       const struct nand_subop *subop)
 684 {
 685         return anfc_misc_data_type_exec(chip, subop, PROG_SET_FEATURE);
 686 }
 687
 688 static int anfc_data_write_type_exec(struct nand_chip *chip,
 689                                      const struct nand_subop *subop)
 690 {
 691         return anfc_misc_data_type_exec(chip, subop, PROG_PGPROG);
 692 }
 693
 694 static int anfc_misc_zerolen_type_exec(struct nand_chip *chip,
 695                                        const struct nand_subop *subop,
 696                                        u32 prog_reg)
 697 {
 698         struct arasan_nfc *nfc = to_anfc(chip->controller);
 699         struct anfc_op nfc_op = {};
 700         int ret;
 701
 702         ret = anfc_parse_instructions(chip, subop, &nfc_op);
 703         if (ret)
 704                 return ret;
 705
 706         nfc_op.prog_reg = prog_reg;
 707         anfc_trigger_op(nfc, &nfc_op);
 708
 709         ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
 710         if (ret)
 711                 return ret;
 712
 713         if (nfc_op.rdy_timeout_ms)
 714                 ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
 715
 716         return ret;
 717 }
 718
 719 static int anfc_status_type_exec(struct nand_chip *chip,
 720                                  const struct nand_subop *subop)
 721 {
 722         struct arasan_nfc *nfc = to_anfc(chip->controller);
 723         u32 tmp;
 724         int ret;
 725
 726         /* See anfc_check_op() for details about this constraint */
 727         if (subop->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS)
 728                 return -ENOTSUPP;
 729
 730         ret = anfc_misc_zerolen_type_exec(chip, subop, PROG_STATUS);
 731         if (ret)
 732                 return ret;
 733
 734         tmp = readl_relaxed(nfc->base + FLASH_STS_REG);
 735         memcpy(subop->instrs[1].ctx.data.buf.in, &tmp, 1);
 736
 737         return 0;
 738 }
 739
 740 static int anfc_reset_type_exec(struct nand_chip *chip,
 741                                 const struct nand_subop *subop)
 742 {
 743         return anfc_misc_zerolen_type_exec(chip, subop, PROG_RST);
 744 }
 745
 746 static int anfc_erase_type_exec(struct nand_chip *chip,
 747                                 const struct nand_subop *subop)
 748 {
 749         return anfc_misc_zerolen_type_exec(chip, subop, PROG_ERASE);
 750 }
 751
 752 static int anfc_wait_type_exec(struct nand_chip *chip,
 753                                const struct nand_subop *subop)
 754 {
 755         struct arasan_nfc *nfc = to_anfc(chip->controller);
 756         struct anfc_op nfc_op = {};
 757         int ret;
 758
 759         ret = anfc_parse_instructions(chip, subop, &nfc_op);
 760         if (ret)
 761                 return ret;
 762
 763         return anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
 764 }
 765
 766 static const struct nand_op_parser anfc_op_parser = NAND_OP_PARSER(
 767         NAND_OP_PARSER_PATTERN(
 768                 anfc_param_read_type_exec,
 769                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 770                 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
 771                 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
 772                 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, ANFC_MAX_CHUNK_SIZE)),
 773         NAND_OP_PARSER_PATTERN(
 774                 anfc_param_write_type_exec,
 775                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 776                 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
 777                 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, ANFC_MAX_PARAM_SIZE)),
 778         NAND_OP_PARSER_PATTERN(
 779                 anfc_data_read_type_exec,
 780                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 781                 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
 782                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 783                 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
 784                 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, ANFC_MAX_CHUNK_SIZE)),
 785         NAND_OP_PARSER_PATTERN(
 786                 anfc_data_write_type_exec,
 787                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 788                 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
 789                 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, ANFC_MAX_CHUNK_SIZE),
 790                 NAND_OP_PARSER_PAT_CMD_ELEM(false)),
 791         NAND_OP_PARSER_PATTERN(
 792                 anfc_reset_type_exec,
 793                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 794                 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
 795         NAND_OP_PARSER_PATTERN(
 796                 anfc_erase_type_exec,
 797                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 798                 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
 799                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 800                 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
 801         NAND_OP_PARSER_PATTERN(
 802                 anfc_status_type_exec,
 803                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 804                 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, ANFC_MAX_CHUNK_SIZE)),
 805         NAND_OP_PARSER_PATTERN(
 806                 anfc_wait_type_exec,
 807                 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
 808         );
 809
 810 static int anfc_check_op(struct nand_chip *chip,
 811                          const struct nand_operation *op)
 812 {
 813         const struct nand_op_instr *instr;
 814         int op_id;
 815
 816         /*
 817          * The controller abstracts all the NAND operations and do not support
 818          * data only operations.
 819          *
 820          * TODO: The nand_op_parser framework should be extended to
 821          * support custom checks on DATA instructions.
 822          */
 823         for (op_id = 0; op_id < op->ninstrs; op_id++) {
 824                 instr = &op->instrs[op_id];
 825
 826                 switch (instr->type) {
 827                 case NAND_OP_ADDR_INSTR:
 828                         if (instr->ctx.addr.naddrs > ANFC_MAX_ADDR_CYC)
 829                                 return -ENOTSUPP;
 830
 831                         break;
 832                 case NAND_OP_DATA_IN_INSTR:
 833                 case NAND_OP_DATA_OUT_INSTR:
 834                         if (instr->ctx.data.len > ANFC_MAX_CHUNK_SIZE)
 835                                 return -ENOTSUPP;
 836
 837                         if (anfc_pkt_len_config(instr->ctx.data.len, 0, 0))
 838                                 return -ENOTSUPP;
 839
 840                         break;
 841                 default:
 842                         break;
 843                 }
 844         }
 845
 846         /*
 847          * The controller does not allow to proceed with a CMD+DATA_IN cycle
 848          * manually on the bus by reading data from the data register. Instead,
 849          * the controller abstract a status read operation with its own status
 850          * register after ordering a read status operation. Hence, we cannot
 851          * support any CMD+DATA_IN operation other than a READ STATUS.
 852          *
 853          * TODO: The nand_op_parser() framework should be extended to describe
 854          * fixed patterns instead of open-coding this check here.
 855          */
 856         if (op->ninstrs == 2 &&
 857             op->instrs[0].type == NAND_OP_CMD_INSTR &&
 858             op->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS &&
 859             op->instrs[1].type == NAND_OP_DATA_IN_INSTR)
 860                 return -ENOTSUPP;
 861
 862         return nand_op_parser_exec_op(chip, &anfc_op_parser, op, true);
 863 }
 864
 865 static int anfc_exec_op(struct nand_chip *chip,
 866                         const struct nand_operation *op,
 867                         bool check_only)
 868 {
 869         int ret;
 870
 871         if (check_only)
 872                 return anfc_check_op(chip, op);
 873
 874         ret = anfc_select_target(chip, op->cs);
 875         if (ret)
 876                 return ret;
 877
 878         return nand_op_parser_exec_op(chip, &anfc_op_parser, op, check_only);
 879 }
 880
 881 static int anfc_setup_interface(struct nand_chip *chip, int target,
 882                                 const struct nand_interface_config *conf)
 883 {
 884         struct anand *anand = to_anand(chip);
 885         struct arasan_nfc *nfc = to_anfc(chip->controller);
 886         struct device_node *np = nfc->dev->of_node;
 887         const struct nand_sdr_timings *sdr;
 888         const struct nand_nvddr_timings *nvddr;
 889
 890         if (nand_interface_is_nvddr(conf)) {
 891                 nvddr = nand_get_nvddr_timings(conf);
 892                 if (IS_ERR(nvddr))
 893                         return PTR_ERR(nvddr);
 894
 895                 /*
 896                  * The controller only supports data payload requests which are
 897                  * a multiple of 4. In practice, most data accesses are 4-byte
 898                  * aligned and this is not an issue. However, rounding up will
 899                  * simply be refused by the controller if we reached the end of
 900                  * the device *and* we are using the NV-DDR interface(!). In
 901                  * this situation, unaligned data requests ending at the device
 902                  * boundary will confuse the controller and cannot be performed.
 903                  *
 904                  * This is something that happens in nand_read_subpage() when
 905                  * selecting software ECC support and must be avoided.
 906                  */
 907                 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT)
 908                         return -ENOTSUPP;
 909         } else {
 910                 sdr = nand_get_sdr_timings(conf);
 911                 if (IS_ERR(sdr))
 912                         return PTR_ERR(sdr);
 913         }
 914
 915         if (target < 0)
 916                 return 0;
 917
 918         if (nand_interface_is_sdr(conf))
 919                 anand->timings = DIFACE_SDR |
 920                                  DIFACE_SDR_MODE(conf->timings.mode);
 921         else
 922                 anand->timings = DIFACE_NVDDR |
 923                                  DIFACE_DDR_MODE(conf->timings.mode);
 924
 925         if (nand_interface_is_sdr(conf)) {
 926                 anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
 927         } else {
 928                 /* ONFI timings are defined in picoseconds */
 929                 anand->clk = div_u64((u64)NSEC_PER_SEC * 1000,
 930                                      conf->timings.nvddr.tCK_min);
 931         }
 932
 933         /*
 934          * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work
 935          * with f > 90MHz (default clock is 100MHz) but signals are unstable
 936          * with higher modes. Hence we decrease a little bit the clock rate to
 937          * 80MHz when using SDR modes 2-5 with this SoC.
 938          */
 939         if (of_device_is_compatible(np, "xlnx,zynqmp-nand-controller") &&
 940             nand_interface_is_sdr(conf) && conf->timings.mode >= 2)
 941                 anand->clk = ANFC_XLNX_SDR_HS_CORE_CLK;
 942
 943         return 0;
 944 }
 945
 946 static int anfc_calc_hw_ecc_bytes(int step_size, int strength)
 947 {
 948         unsigned int bch_gf_mag, ecc_bits;
 949
 950         switch (step_size) {
 951         case SZ_512:
 952                 bch_gf_mag = 13;
 953                 break;
 954         case SZ_1K:
 955                 bch_gf_mag = 14;
 956                 break;
 957         default:
 958                 return -EINVAL;
 959         }
 960
 961         ecc_bits = bch_gf_mag * strength;
 962
 963         return DIV_ROUND_UP(ecc_bits, 8);
 964 }
 965
 966 static const int anfc_hw_ecc_512_strengths[] = {4, 8, 12};
 967
 968 static const int anfc_hw_ecc_1024_strengths[] = {24};
 969
 970 static const struct nand_ecc_step_info anfc_hw_ecc_step_infos[] = {
 971         {
 972                 .stepsize = SZ_512,
 973                 .strengths = anfc_hw_ecc_512_strengths,
 974                 .nstrengths = ARRAY_SIZE(anfc_hw_ecc_512_strengths),
 975         },
 976         {
 977                 .stepsize = SZ_1K,
 978                 .strengths = anfc_hw_ecc_1024_strengths,
 979                 .nstrengths = ARRAY_SIZE(anfc_hw_ecc_1024_strengths),
 980         },
 981 };
 982
 983 static const struct nand_ecc_caps anfc_hw_ecc_caps = {
 984         .stepinfos = anfc_hw_ecc_step_infos,
 985         .nstepinfos = ARRAY_SIZE(anfc_hw_ecc_step_infos),
 986         .calc_ecc_bytes = anfc_calc_hw_ecc_bytes,
 987 };
 988
 989 static int anfc_init_hw_ecc_controller(struct arasan_nfc *nfc,
 990                                        struct nand_chip *chip)
 991 {
 992         struct anand *anand = to_anand(chip);
 993         struct mtd_info *mtd = nand_to_mtd(chip);
 994         struct nand_ecc_ctrl *ecc = &chip->ecc;
 995         unsigned int bch_prim_poly = 0, bch_gf_mag = 0, ecc_offset;
 996         int ret;
 997
 998         switch (mtd->writesize) {
 999         case SZ_512:
1000         case SZ_2K:
1001         case SZ_4K:
1002         case SZ_8K:
1003         case SZ_16K:
1004                 break;
1005         default:
1006                 dev_err(nfc->dev, "Unsupported page size %d\n", mtd->writesize);
1007                 return -EINVAL;
1008         }
1009
1010         ret = nand_ecc_choose_conf(chip, &anfc_hw_ecc_caps, mtd->oobsize);
1011         if (ret)
1012                 return ret;
1013
1014         switch (ecc->strength) {
1015         case 12:
1016                 anand->strength = 0x1;
1017                 break;
1018         case 8:
1019                 anand->strength = 0x2;
1020                 break;
1021         case 4:
1022                 anand->strength = 0x3;
1023                 break;
1024         case 24:
1025                 anand->strength = 0x4;
1026                 break;
1027         default:
1028                 dev_err(nfc->dev, "Unsupported strength %d\n", ecc->strength);
1029                 return -EINVAL;
1030         }
1031
1032         switch (ecc->size) {
1033         case SZ_512:
1034                 bch_gf_mag = 13;
1035                 bch_prim_poly = 0x201b;
1036                 break;
1037         case SZ_1K:
1038                 bch_gf_mag = 14;
1039                 bch_prim_poly = 0x4443;
1040                 break;
1041         default:
1042                 dev_err(nfc->dev, "Unsupported step size %d\n", ecc->strength);
1043                 return -EINVAL;
1044         }
1045
1046         mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
1047
1048         ecc->steps = mtd->writesize / ecc->size;
1049         ecc->algo = NAND_ECC_ALGO_BCH;
1050         anand->ecc_bits = bch_gf_mag * ecc->strength;
1051         ecc->bytes = DIV_ROUND_UP(anand->ecc_bits, 8);
1052         anand->ecc_total = DIV_ROUND_UP(anand->ecc_bits * ecc->steps, 8);
1053         ecc_offset = mtd->writesize + mtd->oobsize - anand->ecc_total;
1054         anand->ecc_conf = ECC_CONF_COL(ecc_offset) |
1055                           ECC_CONF_LEN(anand->ecc_total) |
1056                           ECC_CONF_BCH_EN;
1057
1058         anand->errloc = devm_kmalloc_array(nfc->dev, ecc->strength,
1059                                            sizeof(*anand->errloc), GFP_KERNEL);
1060         if (!anand->errloc)
1061                 return -ENOMEM;
1062
1063         anand->hw_ecc = devm_kmalloc(nfc->dev, ecc->bytes, GFP_KERNEL);
1064         if (!anand->hw_ecc)
1065                 return -ENOMEM;
1066
1067         /* Enforce bit swapping to fit the hardware */
1068         anand->bch = bch_init(bch_gf_mag, ecc->strength, bch_prim_poly, true);
1069         if (!anand->bch)
1070                 return -EINVAL;
1071
1072         ecc->read_page = anfc_sel_read_page_hw_ecc;
1073         ecc->write_page = anfc_sel_write_page_hw_ecc;
1074
1075         return 0;
1076 }
1077
1078 static int anfc_attach_chip(struct nand_chip *chip)
1079 {
1080         struct anand *anand = to_anand(chip);
1081         struct arasan_nfc *nfc = to_anfc(chip->controller);
1082         struct mtd_info *mtd = nand_to_mtd(chip);
1083         int ret = 0;
1084
1085         if (mtd->writesize <= SZ_512)
1086                 anand->caddr_cycles = 1;
1087         else
1088                 anand->caddr_cycles = 2;
1089
1090         if (chip->options & NAND_ROW_ADDR_3)
1091                 anand->raddr_cycles = 3;
1092         else
1093                 anand->raddr_cycles = 2;
1094
1095         switch (mtd->writesize) {
1096         case 512:
1097                 anand->page_sz = 0;
1098                 break;
1099         case 1024:
1100                 anand->page_sz = 5;
1101                 break;
1102         case 2048:
1103                 anand->page_sz = 1;
1104                 break;
1105         case 4096:
1106                 anand->page_sz = 2;
1107                 break;
1108         case 8192:
1109                 anand->page_sz = 3;
1110                 break;
1111         case 16384:
1112                 anand->page_sz = 4;
1113                 break;
1114         default:
1115                 return -EINVAL;
1116         }
1117
1118         /* These hooks are valid for all ECC providers */
1119         chip->ecc.read_page_raw = nand_monolithic_read_page_raw;
1120         chip->ecc.write_page_raw = nand_monolithic_write_page_raw;
1121
1122         switch (chip->ecc.engine_type) {
1123         case NAND_ECC_ENGINE_TYPE_NONE:
1124         case NAND_ECC_ENGINE_TYPE_SOFT:
1125         case NAND_ECC_ENGINE_TYPE_ON_DIE:
1126                 break;
1127         case NAND_ECC_ENGINE_TYPE_ON_HOST:
1128                 ret = anfc_init_hw_ecc_controller(nfc, chip);
1129                 break;
1130         default:
1131                 dev_err(nfc->dev, "Unsupported ECC mode: %d\n",
1132                         chip->ecc.engine_type);
1133                 return -EINVAL;
1134         }
1135
1136         return ret;
1137 }
1138
1139 static void anfc_detach_chip(struct nand_chip *chip)
1140 {
1141         struct anand *anand = to_anand(chip);
1142
1143         if (anand->bch)
1144                 bch_free(anand->bch);
1145 }
1146
1147 static const struct nand_controller_ops anfc_ops = {
1148         .exec_op = anfc_exec_op,
1149         .setup_interface = anfc_setup_interface,
1150         .attach_chip = anfc_attach_chip,
1151         .detach_chip = anfc_detach_chip,
1152 };
1153
1154 static int anfc_chip_init(struct arasan_nfc *nfc, struct device_node *np)
1155 {
1156         struct anand *anand;
1157         struct nand_chip *chip;
1158         struct mtd_info *mtd;
1159         int cs, rb, ret;
1160
1161         anand = devm_kzalloc(nfc->dev, sizeof(*anand), GFP_KERNEL);
1162         if (!anand)
1163                 return -ENOMEM;
1164
1165         /* We do not support multiple CS per chip yet */
1166         if (of_property_count_elems_of_size(np, "reg", sizeof(u32)) != 1) {
1167                 dev_err(nfc->dev, "Invalid reg property\n");
1168                 return -EINVAL;
1169         }
1170
1171         ret = of_property_read_u32(np, "reg", &cs);
1172         if (ret)
1173                 return ret;
1174
1175         ret = of_property_read_u32(np, "nand-rb", &rb);
1176         if (ret)
1177                 return ret;
1178
1179         if (cs >= ANFC_MAX_CS || rb >= ANFC_MAX_CS) {
1180                 dev_err(nfc->dev, "Wrong CS %d or RB %d\n", cs, rb);
1181                 return -EINVAL;
1182         }
1183
1184         if (test_and_set_bit(cs, &nfc->assigned_cs)) {
1185                 dev_err(nfc->dev, "Already assigned CS %d\n", cs);
1186                 return -EINVAL;
1187         }
1188
1189         anand->cs = cs;
1190         anand->rb = rb;
1191
1192         chip = &anand->chip;
1193         mtd = nand_to_mtd(chip);
1194         mtd->dev.parent = nfc->dev;
1195         chip->controller = &nfc->controller;
1196         chip->options = NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
1197                         NAND_USES_DMA;
1198
1199         nand_set_flash_node(chip, np);
1200         if (!mtd->name) {
1201                 dev_err(nfc->dev, "NAND label property is mandatory\n");
1202                 return -EINVAL;
1203         }
1204
1205         ret = nand_scan(chip, 1);
1206         if (ret) {
1207                 dev_err(nfc->dev, "Scan operation failed\n");
1208                 return ret;
1209         }
1210
1211         ret = mtd_device_register(mtd, NULL, 0);
1212         if (ret) {
1213                 nand_cleanup(chip);
1214                 return ret;
1215         }
1216
1217         list_add_tail(&anand->node, &nfc->chips);
1218
1219         return 0;
1220 }
1221
1222 static void anfc_chips_cleanup(struct arasan_nfc *nfc)
1223 {
1224         struct anand *anand, *tmp;
1225         struct nand_chip *chip;
1226         int ret;
1227
1228         list_for_each_entry_safe(anand, tmp, &nfc->chips, node) {
1229                 chip = &anand->chip;
1230                 ret = mtd_device_unregister(nand_to_mtd(chip));
1231                 WARN_ON(ret);
1232                 nand_cleanup(chip);
1233                 list_del(&anand->node);
1234         }
1235 }
1236
1237 static int anfc_chips_init(struct arasan_nfc *nfc)
1238 {
1239         struct device_node *np = nfc->dev->of_node, *nand_np;
1240         int nchips = of_get_child_count(np);
1241         int ret;
1242
1243         if (!nchips || nchips > ANFC_MAX_CS) {
1244                 dev_err(nfc->dev, "Incorrect number of NAND chips (%d)\n",
1245                         nchips);
1246                 return -EINVAL;
1247         }
1248
1249         for_each_child_of_node(np, nand_np) {
1250                 ret = anfc_chip_init(nfc, nand_np);
1251                 if (ret) {
1252                         of_node_put(nand_np);
1253                         anfc_chips_cleanup(nfc);
1254                         break;
1255                 }
1256         }
1257
1258         return ret;
1259 }
1260
1261 static void anfc_reset(struct arasan_nfc *nfc)
1262 {
1263         /* Disable interrupt signals */
1264         writel_relaxed(0, nfc->base + INTR_SIG_EN_REG);
1265
1266         /* Enable interrupt status */
1267         writel_relaxed(EVENT_MASK, nfc->base + INTR_STS_EN_REG);
1268 }
1269
1270 static int anfc_probe(struct platform_device *pdev)
1271 {
1272         struct arasan_nfc *nfc;
1273         int ret;
1274
1275         nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
1276         if (!nfc)
1277                 return -ENOMEM;
1278
1279         nfc->dev = &pdev->dev;
1280         nand_controller_init(&nfc->controller);
1281         nfc->controller.ops = &anfc_ops;
1282         INIT_LIST_HEAD(&nfc->chips);
1283
1284         nfc->base = devm_platform_ioremap_resource(pdev, 0);
1285         if (IS_ERR(nfc->base))
1286                 return PTR_ERR(nfc->base);
1287
1288         anfc_reset(nfc);
1289
1290         nfc->controller_clk = devm_clk_get(&pdev->dev, "controller");
1291         if (IS_ERR(nfc->controller_clk))
1292                 return PTR_ERR(nfc->controller_clk);
1293
1294         nfc->bus_clk = devm_clk_get(&pdev->dev, "bus");
1295         if (IS_ERR(nfc->bus_clk))
1296                 return PTR_ERR(nfc->bus_clk);
1297
1298         ret = clk_prepare_enable(nfc->controller_clk);
1299         if (ret)
1300                 return ret;
1301
1302         ret = clk_prepare_enable(nfc->bus_clk);
1303         if (ret)
1304                 goto disable_controller_clk;
1305
1306         ret = anfc_chips_init(nfc);
1307         if (ret)
1308                 goto disable_bus_clk;
1309
1310         platform_set_drvdata(pdev, nfc);
1311
1312         return 0;
1313
1314 disable_bus_clk:
1315         clk_disable_unprepare(nfc->bus_clk);
1316
1317 disable_controller_clk:
1318         clk_disable_unprepare(nfc->controller_clk);
1319
1320         return ret;
1321 }
1322
1323 static int anfc_remove(struct platform_device *pdev)
1324 {
1325         struct arasan_nfc *nfc = platform_get_drvdata(pdev);
1326
1327         anfc_chips_cleanup(nfc);
1328
1329         clk_disable_unprepare(nfc->bus_clk);
1330         clk_disable_unprepare(nfc->controller_clk);
1331
1332         return 0;
1333 }
1334
1335 static const struct of_device_id anfc_ids[] = {
1336         {
1337                 .compatible = "xlnx,zynqmp-nand-controller",
1338         },
1339         {
1340                 .compatible = "arasan,nfc-v3p10",
1341         },
1342         {}
1343 };
1344 MODULE_DEVICE_TABLE(of, anfc_ids);
1345
1346 static struct platform_driver anfc_driver = {
1347         .driver = {
1348                 .name = "arasan-nand-controller",
1349                 .of_match_table = anfc_ids,
1350         },
1351         .probe = anfc_probe,
1352         .remove = anfc_remove,
1353 };
1354 module_platform_driver(anfc_driver);
1355
1356 MODULE_LICENSE("GPL v2");
1357 MODULE_AUTHOR("Punnaiah Choudary Kalluri <punnaia@xilinx.com>");
1358 MODULE_AUTHOR("Naga Sureshkumar Relli <nagasure@xilinx.com>");
1359 MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
1360 MODULE_DESCRIPTION("Arasan NAND Flash Controller Driver");