2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
36 #include <linux/of_device.h>
38 #include <asm/mach/flash.h>
39 #include <linux/platform_data/mtd-mxc_nand.h>
41 #define DRIVER_NAME "mxc_nand"
43 /* Addresses for NFC registers */
44 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
45 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
46 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
47 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
48 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
49 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
50 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
51 #define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10)
52 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
53 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
54 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
55 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
56 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
57 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
58 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
59 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
60 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
61 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
62 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
63 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
64 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
65 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
67 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
68 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
69 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
70 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
71 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
72 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
73 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
74 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
75 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
76 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
78 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
81 * Operation modes for the NFC. Valid for v1, v2 and v3
84 #define NFC_CMD (1 << 0)
85 #define NFC_ADDR (1 << 1)
86 #define NFC_INPUT (1 << 2)
87 #define NFC_OUTPUT (1 << 3)
88 #define NFC_ID (1 << 4)
89 #define NFC_STATUS (1 << 5)
91 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
92 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
94 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
95 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
96 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
98 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
100 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
102 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
103 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
104 #define NFC_V3_WRPROT_LOCK (1 << 1)
105 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
106 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
108 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
110 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
111 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
112 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
113 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
114 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
115 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
116 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
117 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
118 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
119 #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
120 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
121 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
122 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
123 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
125 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
126 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
127 #define NFC_V3_CONFIG3_FW8 (1 << 3)
128 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
129 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
130 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
131 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
133 #define NFC_V3_IPC (host->regs_ip + 0x2C)
134 #define NFC_V3_IPC_CREQ (1 << 0)
135 #define NFC_V3_IPC_INT (1 << 31)
137 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
139 struct mxc_nand_host;
141 struct mxc_nand_devtype_data {
142 void (*preset)(struct mtd_info *);
143 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
144 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
145 void (*send_page)(struct mtd_info *, unsigned int);
146 void (*send_read_id)(struct mxc_nand_host *);
147 uint16_t (*get_dev_status)(struct mxc_nand_host *);
148 int (*check_int)(struct mxc_nand_host *);
149 void (*irq_control)(struct mxc_nand_host *, int);
150 u32 (*get_ecc_status)(struct mxc_nand_host *);
151 const struct mtd_ooblayout_ops *ooblayout;
152 void (*select_chip)(struct mtd_info *mtd, int chip);
153 int (*correct_data)(struct mtd_info *mtd, u_char *dat,
154 u_char *read_ecc, u_char *calc_ecc);
155 int (*setup_data_interface)(struct mtd_info *mtd,
156 const struct nand_data_interface *conf,
160 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
161 * (CONFIG1:INT_MSK is set). To handle this the driver uses
162 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
164 int irqpending_quirk;
168 size_t spare0_offset;
177 struct mxc_nand_host {
178 struct nand_chip nand;
181 void __iomem *spare0;
182 void __iomem *main_area0;
186 void __iomem *regs_axi;
187 void __iomem *regs_ip;
196 struct completion op_completion;
199 unsigned int buf_start;
201 const struct mxc_nand_devtype_data *devtype_data;
202 struct mxc_nand_platform_data pdata;
205 static const char * const part_probes[] = {
206 "cmdlinepart", "RedBoot", "ofpart", NULL };
208 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
212 const __iomem u32 *s = src;
214 for (i = 0; i < (size >> 2); i++)
215 *t++ = __raw_readl(s++);
218 static void memcpy16_fromio(void *trg, const void __iomem *src, size_t size)
222 const __iomem u16 *s = src;
224 /* We assume that src (IO) is always 32bit aligned */
225 if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) {
226 memcpy32_fromio(trg, src, size);
230 for (i = 0; i < (size >> 1); i++)
231 *t++ = __raw_readw(s++);
234 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
236 /* __iowrite32_copy use 32bit size values so divide by 4 */
237 __iowrite32_copy(trg, src, size / 4);
240 static void memcpy16_toio(void __iomem *trg, const void *src, int size)
243 __iomem u16 *t = trg;
246 /* We assume that trg (IO) is always 32bit aligned */
247 if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) {
248 memcpy32_toio(trg, src, size);
252 for (i = 0; i < (size >> 1); i++)
253 __raw_writew(*s++, t++);
256 static int check_int_v3(struct mxc_nand_host *host)
260 tmp = readl(NFC_V3_IPC);
261 if (!(tmp & NFC_V3_IPC_INT))
264 tmp &= ~NFC_V3_IPC_INT;
265 writel(tmp, NFC_V3_IPC);
270 static int check_int_v1_v2(struct mxc_nand_host *host)
274 tmp = readw(NFC_V1_V2_CONFIG2);
275 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
278 if (!host->devtype_data->irqpending_quirk)
279 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
284 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
288 tmp = readw(NFC_V1_V2_CONFIG1);
291 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
293 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
295 writew(tmp, NFC_V1_V2_CONFIG1);
298 static void irq_control_v3(struct mxc_nand_host *host, int activate)
302 tmp = readl(NFC_V3_CONFIG2);
305 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
307 tmp |= NFC_V3_CONFIG2_INT_MSK;
309 writel(tmp, NFC_V3_CONFIG2);
312 static void irq_control(struct mxc_nand_host *host, int activate)
314 if (host->devtype_data->irqpending_quirk) {
316 enable_irq(host->irq);
318 disable_irq_nosync(host->irq);
320 host->devtype_data->irq_control(host, activate);
324 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
326 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
329 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
331 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
334 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
336 return readl(NFC_V3_ECC_STATUS_RESULT);
339 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
341 struct mxc_nand_host *host = dev_id;
343 if (!host->devtype_data->check_int(host))
346 irq_control(host, 0);
348 complete(&host->op_completion);
353 /* This function polls the NANDFC to wait for the basic operation to
354 * complete by checking the INT bit of config2 register.
356 static int wait_op_done(struct mxc_nand_host *host, int useirq)
361 * If operation is already complete, don't bother to setup an irq or a
364 if (host->devtype_data->check_int(host))
368 unsigned long timeout;
370 reinit_completion(&host->op_completion);
372 irq_control(host, 1);
374 timeout = wait_for_completion_timeout(&host->op_completion, HZ);
375 if (!timeout && !host->devtype_data->check_int(host)) {
376 dev_dbg(host->dev, "timeout waiting for irq\n");
380 int max_retries = 8000;
386 done = host->devtype_data->check_int(host);
390 } while (--max_retries);
393 dev_dbg(host->dev, "timeout polling for completion\n");
398 WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
403 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
406 writel(cmd, NFC_V3_FLASH_CMD);
408 /* send out command */
409 writel(NFC_CMD, NFC_V3_LAUNCH);
411 /* Wait for operation to complete */
412 wait_op_done(host, useirq);
415 /* This function issues the specified command to the NAND device and
416 * waits for completion. */
417 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
419 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
421 writew(cmd, NFC_V1_V2_FLASH_CMD);
422 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
424 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
425 int max_retries = 100;
426 /* Reset completion is indicated by NFC_CONFIG2 */
428 while (max_retries-- > 0) {
429 if (readw(NFC_V1_V2_CONFIG2) == 0) {
435 pr_debug("%s: RESET failed\n", __func__);
437 /* Wait for operation to complete */
438 wait_op_done(host, useirq);
442 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
445 writel(addr, NFC_V3_FLASH_ADDR0);
447 /* send out address */
448 writel(NFC_ADDR, NFC_V3_LAUNCH);
450 wait_op_done(host, 0);
453 /* This function sends an address (or partial address) to the
454 * NAND device. The address is used to select the source/destination for
456 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
458 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
460 writew(addr, NFC_V1_V2_FLASH_ADDR);
461 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
463 /* Wait for operation to complete */
464 wait_op_done(host, islast);
467 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
469 struct nand_chip *nand_chip = mtd_to_nand(mtd);
470 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
473 tmp = readl(NFC_V3_CONFIG1);
475 writel(tmp, NFC_V3_CONFIG1);
477 /* transfer data from NFC ram to nand */
478 writel(ops, NFC_V3_LAUNCH);
480 wait_op_done(host, false);
483 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
485 struct nand_chip *nand_chip = mtd_to_nand(mtd);
486 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
488 /* NANDFC buffer 0 is used for page read/write */
489 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
491 writew(ops, NFC_V1_V2_CONFIG2);
493 /* Wait for operation to complete */
494 wait_op_done(host, true);
497 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
499 struct nand_chip *nand_chip = mtd_to_nand(mtd);
500 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
503 if (mtd->writesize > 512)
508 for (i = 0; i < bufs; i++) {
510 /* NANDFC buffer 0 is used for page read/write */
511 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
513 writew(ops, NFC_V1_V2_CONFIG2);
515 /* Wait for operation to complete */
516 wait_op_done(host, true);
520 static void send_read_id_v3(struct mxc_nand_host *host)
522 /* Read ID into main buffer */
523 writel(NFC_ID, NFC_V3_LAUNCH);
525 wait_op_done(host, true);
527 memcpy32_fromio(host->data_buf, host->main_area0, 16);
530 /* Request the NANDFC to perform a read of the NAND device ID. */
531 static void send_read_id_v1_v2(struct mxc_nand_host *host)
533 /* NANDFC buffer 0 is used for device ID output */
534 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
536 writew(NFC_ID, NFC_V1_V2_CONFIG2);
538 /* Wait for operation to complete */
539 wait_op_done(host, true);
541 memcpy32_fromio(host->data_buf, host->main_area0, 16);
544 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
546 writew(NFC_STATUS, NFC_V3_LAUNCH);
547 wait_op_done(host, true);
549 return readl(NFC_V3_CONFIG1) >> 16;
552 /* This function requests the NANDFC to perform a read of the
553 * NAND device status and returns the current status. */
554 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
556 void __iomem *main_buf = host->main_area0;
560 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
563 * The device status is stored in main_area0. To
564 * prevent corruption of the buffer save the value
565 * and restore it afterwards.
567 store = readl(main_buf);
569 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
570 wait_op_done(host, true);
572 ret = readw(main_buf);
574 writel(store, main_buf);
579 /* This functions is used by upper layer to checks if device is ready */
580 static int mxc_nand_dev_ready(struct mtd_info *mtd)
583 * NFC handles R/B internally. Therefore, this function
584 * always returns status as ready.
589 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
592 * If HW ECC is enabled, we turn it on during init. There is
593 * no need to enable again here.
597 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
598 u_char *read_ecc, u_char *calc_ecc)
600 struct nand_chip *nand_chip = mtd_to_nand(mtd);
601 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
604 * 1-Bit errors are automatically corrected in HW. No need for
605 * additional correction. 2-Bit errors cannot be corrected by
606 * HW ECC, so we need to return failure
608 uint16_t ecc_status = get_ecc_status_v1(host);
610 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
611 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
618 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
619 u_char *read_ecc, u_char *calc_ecc)
621 struct nand_chip *nand_chip = mtd_to_nand(mtd);
622 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
626 u8 ecc_bit_mask, err_limit;
628 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
629 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
631 no_subpages = mtd->writesize >> 9;
633 ecc_stat = host->devtype_data->get_ecc_status(host);
636 err = ecc_stat & ecc_bit_mask;
637 if (err > err_limit) {
638 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
644 } while (--no_subpages);
646 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
651 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
657 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
659 struct nand_chip *nand_chip = mtd_to_nand(mtd);
660 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
663 /* Check for status request */
664 if (host->status_request)
665 return host->devtype_data->get_dev_status(host) & 0xFF;
667 if (nand_chip->options & NAND_BUSWIDTH_16) {
668 /* only take the lower byte of each word */
669 ret = *(uint16_t *)(host->data_buf + host->buf_start);
671 host->buf_start += 2;
673 ret = *(uint8_t *)(host->data_buf + host->buf_start);
677 pr_debug("%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
681 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
683 struct nand_chip *nand_chip = mtd_to_nand(mtd);
684 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
687 ret = *(uint16_t *)(host->data_buf + host->buf_start);
688 host->buf_start += 2;
693 /* Write data of length len to buffer buf. The data to be
694 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
695 * Operation by the NFC, the data is written to NAND Flash */
696 static void mxc_nand_write_buf(struct mtd_info *mtd,
697 const u_char *buf, int len)
699 struct nand_chip *nand_chip = mtd_to_nand(mtd);
700 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
701 u16 col = host->buf_start;
702 int n = mtd->oobsize + mtd->writesize - col;
706 memcpy(host->data_buf + col, buf, n);
708 host->buf_start += n;
711 /* Read the data buffer from the NAND Flash. To read the data from NAND
712 * Flash first the data output cycle is initiated by the NFC, which copies
713 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
715 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
717 struct nand_chip *nand_chip = mtd_to_nand(mtd);
718 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
719 u16 col = host->buf_start;
720 int n = mtd->oobsize + mtd->writesize - col;
724 memcpy(buf, host->data_buf + col, n);
726 host->buf_start += n;
729 /* This function is used by upper layer for select and
730 * deselect of the NAND chip */
731 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
733 struct nand_chip *nand_chip = mtd_to_nand(mtd);
734 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
737 /* Disable the NFC clock */
739 clk_disable_unprepare(host->clk);
745 if (!host->clk_act) {
746 /* Enable the NFC clock */
747 clk_prepare_enable(host->clk);
752 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
754 struct nand_chip *nand_chip = mtd_to_nand(mtd);
755 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
758 /* Disable the NFC clock */
760 clk_disable_unprepare(host->clk);
766 if (!host->clk_act) {
767 /* Enable the NFC clock */
768 clk_prepare_enable(host->clk);
772 host->active_cs = chip;
773 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
777 * The controller splits a page into data chunks of 512 bytes + partial oob.
778 * There are writesize / 512 such chunks, the size of the partial oob parts is
779 * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then
780 * contains additionally the byte lost by rounding (if any).
781 * This function handles the needed shuffling between host->data_buf (which
782 * holds a page in natural order, i.e. writesize bytes data + oobsize bytes
783 * spare) and the NFC buffer.
785 static void copy_spare(struct mtd_info *mtd, bool bfrom)
787 struct nand_chip *this = mtd_to_nand(mtd);
788 struct mxc_nand_host *host = nand_get_controller_data(this);
789 u16 i, oob_chunk_size;
790 u16 num_chunks = mtd->writesize / 512;
792 u8 *d = host->data_buf + mtd->writesize;
793 u8 __iomem *s = host->spare0;
794 u16 sparebuf_size = host->devtype_data->spare_len;
796 /* size of oob chunk for all but possibly the last one */
797 oob_chunk_size = (host->used_oobsize / num_chunks) & ~1;
800 for (i = 0; i < num_chunks - 1; i++)
801 memcpy16_fromio(d + i * oob_chunk_size,
802 s + i * sparebuf_size,
806 memcpy16_fromio(d + i * oob_chunk_size,
807 s + i * sparebuf_size,
808 host->used_oobsize - i * oob_chunk_size);
810 for (i = 0; i < num_chunks - 1; i++)
811 memcpy16_toio(&s[i * sparebuf_size],
812 &d[i * oob_chunk_size],
816 memcpy16_toio(&s[i * sparebuf_size],
817 &d[i * oob_chunk_size],
818 host->used_oobsize - i * oob_chunk_size);
823 * MXC NANDFC can only perform full page+spare or spare-only read/write. When
824 * the upper layers perform a read/write buf operation, the saved column address
825 * is used to index into the full page. So usually this function is called with
826 * column == 0 (unless no column cycle is needed indicated by column == -1)
828 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
830 struct nand_chip *nand_chip = mtd_to_nand(mtd);
831 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
833 /* Write out column address, if necessary */
835 host->devtype_data->send_addr(host, column & 0xff,
837 if (mtd->writesize > 512)
838 /* another col addr cycle for 2k page */
839 host->devtype_data->send_addr(host,
840 (column >> 8) & 0xff,
844 /* Write out page address, if necessary */
845 if (page_addr != -1) {
846 /* paddr_0 - p_addr_7 */
847 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
849 if (mtd->writesize > 512) {
850 if (mtd->size >= 0x10000000) {
851 /* paddr_8 - paddr_15 */
852 host->devtype_data->send_addr(host,
853 (page_addr >> 8) & 0xff,
855 host->devtype_data->send_addr(host,
856 (page_addr >> 16) & 0xff,
859 /* paddr_8 - paddr_15 */
860 host->devtype_data->send_addr(host,
861 (page_addr >> 8) & 0xff, true);
863 /* One more address cycle for higher density devices */
864 if (mtd->size >= 0x4000000) {
865 /* paddr_8 - paddr_15 */
866 host->devtype_data->send_addr(host,
867 (page_addr >> 8) & 0xff,
869 host->devtype_data->send_addr(host,
870 (page_addr >> 16) & 0xff,
873 /* paddr_8 - paddr_15 */
874 host->devtype_data->send_addr(host,
875 (page_addr >> 8) & 0xff, true);
880 #define MXC_V1_ECCBYTES 5
882 static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section,
883 struct mtd_oob_region *oobregion)
885 struct nand_chip *nand_chip = mtd_to_nand(mtd);
887 if (section >= nand_chip->ecc.steps)
890 oobregion->offset = (section * 16) + 6;
891 oobregion->length = MXC_V1_ECCBYTES;
896 static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section,
897 struct mtd_oob_region *oobregion)
899 struct nand_chip *nand_chip = mtd_to_nand(mtd);
901 if (section > nand_chip->ecc.steps)
905 if (mtd->writesize <= 512) {
906 oobregion->offset = 0;
907 oobregion->length = 5;
909 oobregion->offset = 2;
910 oobregion->length = 4;
913 oobregion->offset = ((section - 1) * 16) + MXC_V1_ECCBYTES + 6;
914 if (section < nand_chip->ecc.steps)
915 oobregion->length = (section * 16) + 6 -
918 oobregion->length = mtd->oobsize - oobregion->offset;
924 static const struct mtd_ooblayout_ops mxc_v1_ooblayout_ops = {
925 .ecc = mxc_v1_ooblayout_ecc,
926 .free = mxc_v1_ooblayout_free,
929 static int mxc_v2_ooblayout_ecc(struct mtd_info *mtd, int section,
930 struct mtd_oob_region *oobregion)
932 struct nand_chip *nand_chip = mtd_to_nand(mtd);
933 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
935 if (section >= nand_chip->ecc.steps)
938 oobregion->offset = (section * stepsize) + 7;
939 oobregion->length = nand_chip->ecc.bytes;
944 static int mxc_v2_ooblayout_free(struct mtd_info *mtd, int section,
945 struct mtd_oob_region *oobregion)
947 struct nand_chip *nand_chip = mtd_to_nand(mtd);
948 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
950 if (section >= nand_chip->ecc.steps)
954 if (mtd->writesize <= 512) {
955 oobregion->offset = 0;
956 oobregion->length = 5;
958 oobregion->offset = 2;
959 oobregion->length = 4;
962 oobregion->offset = section * stepsize;
963 oobregion->length = 7;
969 static const struct mtd_ooblayout_ops mxc_v2_ooblayout_ops = {
970 .ecc = mxc_v2_ooblayout_ecc,
971 .free = mxc_v2_ooblayout_free,
975 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
976 * on how much oob the nand chip has. For 8bit ecc we need at least
977 * 26 bytes of oob data per 512 byte block.
979 static int get_eccsize(struct mtd_info *mtd)
981 int oobbytes_per_512 = 0;
983 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
985 if (oobbytes_per_512 < 26)
991 static void preset_v1(struct mtd_info *mtd)
993 struct nand_chip *nand_chip = mtd_to_nand(mtd);
994 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
995 uint16_t config1 = 0;
997 if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize)
998 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1000 if (!host->devtype_data->irqpending_quirk)
1001 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1005 writew(config1, NFC_V1_V2_CONFIG1);
1006 /* preset operation */
1008 /* Unlock the internal RAM Buffer */
1009 writew(0x2, NFC_V1_V2_CONFIG);
1011 /* Blocks to be unlocked */
1012 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
1013 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
1015 /* Unlock Block Command for given address range */
1016 writew(0x4, NFC_V1_V2_WRPROT);
1019 static int mxc_nand_v2_setup_data_interface(struct mtd_info *mtd,
1020 const struct nand_data_interface *conf,
1023 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1024 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1025 int tRC_min_ns, tRC_ps, ret;
1026 unsigned long rate, rate_round;
1027 const struct nand_sdr_timings *timings;
1030 timings = nand_get_sdr_timings(conf);
1031 if (IS_ERR(timings))
1034 config1 = readw(NFC_V1_V2_CONFIG1);
1036 tRC_min_ns = timings->tRC_min / 1000;
1037 rate = 1000000000 / tRC_min_ns;
1040 * For tRC < 30ns we have to use EDO mode. In this case the controller
1041 * does one access per clock cycle. Otherwise the controller does one
1042 * access in two clock cycles, thus we have to double the rate to the
1045 if (tRC_min_ns < 30) {
1046 rate_round = clk_round_rate(host->clk, rate);
1047 config1 |= NFC_V2_CONFIG1_ONE_CYCLE;
1048 tRC_ps = 1000000000 / (rate_round / 1000);
1051 rate_round = clk_round_rate(host->clk, rate);
1052 config1 &= ~NFC_V2_CONFIG1_ONE_CYCLE;
1053 tRC_ps = 1000000000 / (rate_round / 1000 / 2);
1057 * The timing values compared against are from the i.MX25 Automotive
1058 * datasheet, Table 50. NFC Timing Parameters
1060 if (timings->tCLS_min > tRC_ps - 1000 ||
1061 timings->tCLH_min > tRC_ps - 2000 ||
1062 timings->tCS_min > tRC_ps - 1000 ||
1063 timings->tCH_min > tRC_ps - 2000 ||
1064 timings->tWP_min > tRC_ps - 1500 ||
1065 timings->tALS_min > tRC_ps ||
1066 timings->tALH_min > tRC_ps - 3000 ||
1067 timings->tDS_min > tRC_ps ||
1068 timings->tDH_min > tRC_ps - 5000 ||
1069 timings->tWC_min > 2 * tRC_ps ||
1070 timings->tWH_min > tRC_ps - 2500 ||
1071 timings->tRR_min > 6 * tRC_ps ||
1072 timings->tRP_min > 3 * tRC_ps / 2 ||
1073 timings->tRC_min > 2 * tRC_ps ||
1074 timings->tREH_min > (tRC_ps / 2) - 2500) {
1075 dev_dbg(host->dev, "Timing out of bounds\n");
1082 ret = clk_set_rate(host->clk, rate);
1086 writew(config1, NFC_V1_V2_CONFIG1);
1088 dev_dbg(host->dev, "Setting rate to %ldHz, %s mode\n", rate_round,
1089 config1 & NFC_V2_CONFIG1_ONE_CYCLE ? "One cycle (EDO)" :
1095 static void preset_v2(struct mtd_info *mtd)
1097 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1098 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1099 uint16_t config1 = 0;
1101 config1 |= NFC_V2_CONFIG1_FP_INT;
1103 if (!host->devtype_data->irqpending_quirk)
1104 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1106 if (mtd->writesize) {
1107 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
1109 if (nand_chip->ecc.mode == NAND_ECC_HW)
1110 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1112 host->eccsize = get_eccsize(mtd);
1113 if (host->eccsize == 4)
1114 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
1116 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
1121 writew(config1, NFC_V1_V2_CONFIG1);
1122 /* preset operation */
1124 /* spare area size in 16-bit half-words */
1125 writew(mtd->oobsize / 2, NFC_V21_RSLTSPARE_AREA);
1127 /* Unlock the internal RAM Buffer */
1128 writew(0x2, NFC_V1_V2_CONFIG);
1130 /* Blocks to be unlocked */
1131 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
1132 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
1133 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
1134 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
1135 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
1136 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
1137 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
1138 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
1140 /* Unlock Block Command for given address range */
1141 writew(0x4, NFC_V1_V2_WRPROT);
1144 static void preset_v3(struct mtd_info *mtd)
1146 struct nand_chip *chip = mtd_to_nand(mtd);
1147 struct mxc_nand_host *host = nand_get_controller_data(chip);
1148 uint32_t config2, config3;
1151 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
1152 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
1154 /* Unlock the internal RAM Buffer */
1155 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1158 /* Blocks to be unlocked */
1159 for (i = 0; i < NAND_MAX_CHIPS; i++)
1160 writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1162 writel(0, NFC_V3_IPC);
1164 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1165 NFC_V3_CONFIG2_2CMD_PHASES |
1166 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1167 NFC_V3_CONFIG2_ST_CMD(0x70) |
1168 NFC_V3_CONFIG2_INT_MSK |
1169 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1171 addr_phases = fls(chip->pagemask) >> 3;
1173 if (mtd->writesize == 2048) {
1174 config2 |= NFC_V3_CONFIG2_PS_2048;
1175 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1176 } else if (mtd->writesize == 4096) {
1177 config2 |= NFC_V3_CONFIG2_PS_4096;
1178 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1180 config2 |= NFC_V3_CONFIG2_PS_512;
1181 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1184 if (mtd->writesize) {
1185 if (chip->ecc.mode == NAND_ECC_HW)
1186 config2 |= NFC_V3_CONFIG2_ECC_EN;
1188 config2 |= NFC_V3_CONFIG2_PPB(
1189 ffs(mtd->erasesize / mtd->writesize) - 6,
1190 host->devtype_data->ppb_shift);
1191 host->eccsize = get_eccsize(mtd);
1192 if (host->eccsize == 8)
1193 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1196 writel(config2, NFC_V3_CONFIG2);
1198 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1199 NFC_V3_CONFIG3_NO_SDMA |
1200 NFC_V3_CONFIG3_RBB_MODE |
1201 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1202 NFC_V3_CONFIG3_ADD_OP(0);
1204 if (!(chip->options & NAND_BUSWIDTH_16))
1205 config3 |= NFC_V3_CONFIG3_FW8;
1207 writel(config3, NFC_V3_CONFIG3);
1209 writel(0, NFC_V3_DELAY_LINE);
1212 /* Used by the upper layer to write command to NAND Flash for
1213 * different operations to be carried out on NAND Flash */
1214 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1215 int column, int page_addr)
1217 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1218 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1220 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1221 command, column, page_addr);
1223 /* Reset command state information */
1224 host->status_request = false;
1226 /* Command pre-processing step */
1228 case NAND_CMD_RESET:
1229 host->devtype_data->preset(mtd);
1230 host->devtype_data->send_cmd(host, command, false);
1233 case NAND_CMD_STATUS:
1234 host->buf_start = 0;
1235 host->status_request = true;
1237 host->devtype_data->send_cmd(host, command, true);
1238 WARN_ONCE(column != -1 || page_addr != -1,
1239 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1240 command, column, page_addr);
1241 mxc_do_addr_cycle(mtd, column, page_addr);
1244 case NAND_CMD_READ0:
1245 case NAND_CMD_READOOB:
1246 if (command == NAND_CMD_READ0)
1247 host->buf_start = column;
1249 host->buf_start = column + mtd->writesize;
1251 command = NAND_CMD_READ0; /* only READ0 is valid */
1253 host->devtype_data->send_cmd(host, command, false);
1254 WARN_ONCE(column < 0,
1255 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1256 command, column, page_addr);
1257 mxc_do_addr_cycle(mtd, 0, page_addr);
1259 if (mtd->writesize > 512)
1260 host->devtype_data->send_cmd(host,
1261 NAND_CMD_READSTART, true);
1263 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1265 memcpy32_fromio(host->data_buf, host->main_area0,
1267 copy_spare(mtd, true);
1270 case NAND_CMD_SEQIN:
1271 if (column >= mtd->writesize)
1272 /* call ourself to read a page */
1273 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1275 host->buf_start = column;
1277 host->devtype_data->send_cmd(host, command, false);
1278 WARN_ONCE(column < -1,
1279 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1280 command, column, page_addr);
1281 mxc_do_addr_cycle(mtd, 0, page_addr);
1284 case NAND_CMD_PAGEPROG:
1285 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1286 copy_spare(mtd, false);
1287 host->devtype_data->send_page(mtd, NFC_INPUT);
1288 host->devtype_data->send_cmd(host, command, true);
1289 WARN_ONCE(column != -1 || page_addr != -1,
1290 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1291 command, column, page_addr);
1292 mxc_do_addr_cycle(mtd, column, page_addr);
1295 case NAND_CMD_READID:
1296 host->devtype_data->send_cmd(host, command, true);
1297 mxc_do_addr_cycle(mtd, column, page_addr);
1298 host->devtype_data->send_read_id(host);
1299 host->buf_start = 0;
1302 case NAND_CMD_ERASE1:
1303 case NAND_CMD_ERASE2:
1304 host->devtype_data->send_cmd(host, command, false);
1305 WARN_ONCE(column != -1,
1306 "Unexpected column value (cmd=%u, col=%d)\n",
1308 mxc_do_addr_cycle(mtd, column, page_addr);
1311 case NAND_CMD_PARAM:
1312 host->devtype_data->send_cmd(host, command, false);
1313 mxc_do_addr_cycle(mtd, column, page_addr);
1314 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1315 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1316 host->buf_start = 0;
1319 WARN_ONCE(1, "Unimplemented command (cmd=%u)\n",
1325 static int mxc_nand_onfi_set_features(struct mtd_info *mtd,
1326 struct nand_chip *chip, int addr,
1327 u8 *subfeature_param)
1329 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1330 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1333 if (!chip->onfi_version ||
1334 !(le16_to_cpu(chip->onfi_params.opt_cmd)
1335 & ONFI_OPT_CMD_SET_GET_FEATURES))
1338 host->buf_start = 0;
1340 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1341 chip->write_byte(mtd, subfeature_param[i]);
1343 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1344 host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false);
1345 mxc_do_addr_cycle(mtd, addr, -1);
1346 host->devtype_data->send_page(mtd, NFC_INPUT);
1351 static int mxc_nand_onfi_get_features(struct mtd_info *mtd,
1352 struct nand_chip *chip, int addr,
1353 u8 *subfeature_param)
1355 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1356 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1359 if (!chip->onfi_version ||
1360 !(le16_to_cpu(chip->onfi_params.opt_cmd)
1361 & ONFI_OPT_CMD_SET_GET_FEATURES))
1364 host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false);
1365 mxc_do_addr_cycle(mtd, addr, -1);
1366 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1367 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1368 host->buf_start = 0;
1370 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1371 *subfeature_param++ = chip->read_byte(mtd);
1377 * The generic flash bbt decriptors overlap with our ecc
1378 * hardware, so define some i.MX specific ones.
1380 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1381 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1383 static struct nand_bbt_descr bbt_main_descr = {
1384 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1385 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1390 .pattern = bbt_pattern,
1393 static struct nand_bbt_descr bbt_mirror_descr = {
1394 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1395 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1400 .pattern = mirror_pattern,
1403 /* v1 + irqpending_quirk: i.MX21 */
1404 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1405 .preset = preset_v1,
1406 .send_cmd = send_cmd_v1_v2,
1407 .send_addr = send_addr_v1_v2,
1408 .send_page = send_page_v1,
1409 .send_read_id = send_read_id_v1_v2,
1410 .get_dev_status = get_dev_status_v1_v2,
1411 .check_int = check_int_v1_v2,
1412 .irq_control = irq_control_v1_v2,
1413 .get_ecc_status = get_ecc_status_v1,
1414 .ooblayout = &mxc_v1_ooblayout_ops,
1415 .select_chip = mxc_nand_select_chip_v1_v3,
1416 .correct_data = mxc_nand_correct_data_v1,
1417 .irqpending_quirk = 1,
1419 .regs_offset = 0xe00,
1420 .spare0_offset = 0x800,
1426 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1427 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1428 .preset = preset_v1,
1429 .send_cmd = send_cmd_v1_v2,
1430 .send_addr = send_addr_v1_v2,
1431 .send_page = send_page_v1,
1432 .send_read_id = send_read_id_v1_v2,
1433 .get_dev_status = get_dev_status_v1_v2,
1434 .check_int = check_int_v1_v2,
1435 .irq_control = irq_control_v1_v2,
1436 .get_ecc_status = get_ecc_status_v1,
1437 .ooblayout = &mxc_v1_ooblayout_ops,
1438 .select_chip = mxc_nand_select_chip_v1_v3,
1439 .correct_data = mxc_nand_correct_data_v1,
1440 .irqpending_quirk = 0,
1442 .regs_offset = 0xe00,
1443 .spare0_offset = 0x800,
1450 /* v21: i.MX25, i.MX35 */
1451 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1452 .preset = preset_v2,
1453 .send_cmd = send_cmd_v1_v2,
1454 .send_addr = send_addr_v1_v2,
1455 .send_page = send_page_v2,
1456 .send_read_id = send_read_id_v1_v2,
1457 .get_dev_status = get_dev_status_v1_v2,
1458 .check_int = check_int_v1_v2,
1459 .irq_control = irq_control_v1_v2,
1460 .get_ecc_status = get_ecc_status_v2,
1461 .ooblayout = &mxc_v2_ooblayout_ops,
1462 .select_chip = mxc_nand_select_chip_v2,
1463 .correct_data = mxc_nand_correct_data_v2_v3,
1464 .setup_data_interface = mxc_nand_v2_setup_data_interface,
1465 .irqpending_quirk = 0,
1467 .regs_offset = 0x1e00,
1468 .spare0_offset = 0x1000,
1476 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1477 .preset = preset_v3,
1478 .send_cmd = send_cmd_v3,
1479 .send_addr = send_addr_v3,
1480 .send_page = send_page_v3,
1481 .send_read_id = send_read_id_v3,
1482 .get_dev_status = get_dev_status_v3,
1483 .check_int = check_int_v3,
1484 .irq_control = irq_control_v3,
1485 .get_ecc_status = get_ecc_status_v3,
1486 .ooblayout = &mxc_v2_ooblayout_ops,
1487 .select_chip = mxc_nand_select_chip_v1_v3,
1488 .correct_data = mxc_nand_correct_data_v2_v3,
1489 .irqpending_quirk = 0,
1492 .spare0_offset = 0x1000,
1493 .axi_offset = 0x1e00,
1501 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1502 .preset = preset_v3,
1503 .send_cmd = send_cmd_v3,
1504 .send_addr = send_addr_v3,
1505 .send_page = send_page_v3,
1506 .send_read_id = send_read_id_v3,
1507 .get_dev_status = get_dev_status_v3,
1508 .check_int = check_int_v3,
1509 .irq_control = irq_control_v3,
1510 .get_ecc_status = get_ecc_status_v3,
1511 .ooblayout = &mxc_v2_ooblayout_ops,
1512 .select_chip = mxc_nand_select_chip_v1_v3,
1513 .correct_data = mxc_nand_correct_data_v2_v3,
1514 .irqpending_quirk = 0,
1517 .spare0_offset = 0x1000,
1518 .axi_offset = 0x1e00,
1525 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1527 return host->devtype_data == &imx21_nand_devtype_data;
1530 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1532 return host->devtype_data == &imx27_nand_devtype_data;
1535 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1537 return host->devtype_data == &imx25_nand_devtype_data;
1540 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1542 return host->devtype_data == &imx51_nand_devtype_data;
1545 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1547 return host->devtype_data == &imx53_nand_devtype_data;
1550 static const struct platform_device_id mxcnd_devtype[] = {
1552 .name = "imx21-nand",
1553 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1555 .name = "imx27-nand",
1556 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1558 .name = "imx25-nand",
1559 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1561 .name = "imx51-nand",
1562 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1564 .name = "imx53-nand",
1565 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1570 MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1573 static const struct of_device_id mxcnd_dt_ids[] = {
1575 .compatible = "fsl,imx21-nand",
1576 .data = &imx21_nand_devtype_data,
1578 .compatible = "fsl,imx27-nand",
1579 .data = &imx27_nand_devtype_data,
1581 .compatible = "fsl,imx25-nand",
1582 .data = &imx25_nand_devtype_data,
1584 .compatible = "fsl,imx51-nand",
1585 .data = &imx51_nand_devtype_data,
1587 .compatible = "fsl,imx53-nand",
1588 .data = &imx53_nand_devtype_data,
1592 MODULE_DEVICE_TABLE(of, mxcnd_dt_ids);
1594 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1596 struct device_node *np = host->dev->of_node;
1597 const struct of_device_id *of_id =
1598 of_match_device(mxcnd_dt_ids, host->dev);
1603 host->devtype_data = of_id->data;
1608 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1614 static int mxcnd_probe(struct platform_device *pdev)
1616 struct nand_chip *this;
1617 struct mtd_info *mtd;
1618 struct mxc_nand_host *host;
1619 struct resource *res;
1622 /* Allocate memory for MTD device structure and private data */
1623 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1628 /* allocate a temporary buffer for the nand_scan_ident() */
1629 host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1630 if (!host->data_buf)
1633 host->dev = &pdev->dev;
1634 /* structures must be linked */
1636 mtd = nand_to_mtd(this);
1637 mtd->dev.parent = &pdev->dev;
1638 mtd->name = DRIVER_NAME;
1640 /* 50 us command delay time */
1641 this->chip_delay = 5;
1643 nand_set_controller_data(this, host);
1644 nand_set_flash_node(this, pdev->dev.of_node),
1645 this->dev_ready = mxc_nand_dev_ready;
1646 this->cmdfunc = mxc_nand_command;
1647 this->read_byte = mxc_nand_read_byte;
1648 this->read_word = mxc_nand_read_word;
1649 this->write_buf = mxc_nand_write_buf;
1650 this->read_buf = mxc_nand_read_buf;
1651 this->onfi_set_features = mxc_nand_onfi_set_features;
1652 this->onfi_get_features = mxc_nand_onfi_get_features;
1654 host->clk = devm_clk_get(&pdev->dev, NULL);
1655 if (IS_ERR(host->clk))
1656 return PTR_ERR(host->clk);
1658 err = mxcnd_probe_dt(host);
1660 struct mxc_nand_platform_data *pdata =
1661 dev_get_platdata(&pdev->dev);
1663 host->pdata = *pdata;
1664 host->devtype_data = (struct mxc_nand_devtype_data *)
1665 pdev->id_entry->driver_data;
1673 this->setup_data_interface = host->devtype_data->setup_data_interface;
1675 if (host->devtype_data->needs_ip) {
1676 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1677 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1678 if (IS_ERR(host->regs_ip))
1679 return PTR_ERR(host->regs_ip);
1681 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1683 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1686 host->base = devm_ioremap_resource(&pdev->dev, res);
1687 if (IS_ERR(host->base))
1688 return PTR_ERR(host->base);
1690 host->main_area0 = host->base;
1692 if (host->devtype_data->regs_offset)
1693 host->regs = host->base + host->devtype_data->regs_offset;
1694 host->spare0 = host->base + host->devtype_data->spare0_offset;
1695 if (host->devtype_data->axi_offset)
1696 host->regs_axi = host->base + host->devtype_data->axi_offset;
1698 this->ecc.bytes = host->devtype_data->eccbytes;
1699 host->eccsize = host->devtype_data->eccsize;
1701 this->select_chip = host->devtype_data->select_chip;
1702 this->ecc.size = 512;
1703 mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
1705 if (host->pdata.hw_ecc) {
1706 this->ecc.mode = NAND_ECC_HW;
1708 this->ecc.mode = NAND_ECC_SOFT;
1709 this->ecc.algo = NAND_ECC_HAMMING;
1712 /* NAND bus width determines access functions used by upper layer */
1713 if (host->pdata.width == 2)
1714 this->options |= NAND_BUSWIDTH_16;
1716 /* update flash based bbt */
1717 if (host->pdata.flash_bbt)
1718 this->bbt_options |= NAND_BBT_USE_FLASH;
1720 init_completion(&host->op_completion);
1722 host->irq = platform_get_irq(pdev, 0);
1727 * Use host->devtype_data->irq_control() here instead of irq_control()
1728 * because we must not disable_irq_nosync without having requested the
1731 host->devtype_data->irq_control(host, 0);
1733 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1734 0, DRIVER_NAME, host);
1738 err = clk_prepare_enable(host->clk);
1744 * Now that we "own" the interrupt make sure the interrupt mask bit is
1745 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1748 if (host->devtype_data->irqpending_quirk) {
1749 disable_irq_nosync(host->irq);
1750 host->devtype_data->irq_control(host, 1);
1753 /* first scan to find the device and get the page size */
1754 if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) {
1759 switch (this->ecc.mode) {
1761 this->ecc.calculate = mxc_nand_calculate_ecc;
1762 this->ecc.hwctl = mxc_nand_enable_hwecc;
1763 this->ecc.correct = host->devtype_data->correct_data;
1774 if (this->bbt_options & NAND_BBT_USE_FLASH) {
1775 this->bbt_td = &bbt_main_descr;
1776 this->bbt_md = &bbt_mirror_descr;
1779 /* allocate the right size buffer now */
1780 devm_kfree(&pdev->dev, (void *)host->data_buf);
1781 host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize,
1783 if (!host->data_buf) {
1788 /* Call preset again, with correct writesize this time */
1789 host->devtype_data->preset(mtd);
1791 if (!this->ecc.bytes) {
1792 if (host->eccsize == 8)
1793 this->ecc.bytes = 18;
1794 else if (host->eccsize == 4)
1795 this->ecc.bytes = 9;
1799 * Experimentation shows that i.MX NFC can only handle up to 218 oob
1800 * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare()
1801 * into copying invalid data to/from the spare IO buffer, as this
1802 * might cause ECC data corruption when doing sub-page write to a
1803 * partially written page.
1805 host->used_oobsize = min(mtd->oobsize, 218U);
1807 if (this->ecc.mode == NAND_ECC_HW) {
1808 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1809 this->ecc.strength = 1;
1811 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1814 /* second phase scan */
1815 if (nand_scan_tail(mtd)) {
1820 /* Register the partitions */
1821 mtd_device_parse_register(mtd, part_probes,
1824 host->pdata.nr_parts);
1826 platform_set_drvdata(pdev, host);
1832 clk_disable_unprepare(host->clk);
1837 static int mxcnd_remove(struct platform_device *pdev)
1839 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1841 nand_release(&host->nand);
1843 clk_disable_unprepare(host->clk);
1848 static struct platform_driver mxcnd_driver = {
1850 .name = DRIVER_NAME,
1851 .of_match_table = of_match_ptr(mxcnd_dt_ids),
1853 .id_table = mxcnd_devtype,
1854 .probe = mxcnd_probe,
1855 .remove = mxcnd_remove,
1857 module_platform_driver(mxcnd_driver);
1859 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1860 MODULE_DESCRIPTION("MXC NAND MTD driver");
1861 MODULE_LICENSE("GPL");