drivers/mtd/nand/mxc_nand.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA 02110-1301, USA.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/rawnand.h>
  26 #include <linux/mtd/partitions.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/clk.h>
  31 #include <linux/err.h>
  32 #include <linux/io.h>
  33 #include <linux/irq.h>
  34 #include <linux/completion.h>
  35 #include <linux/of.h>
  36 #include <linux/of_device.h>
  37
  38 #include <asm/mach/flash.h>
  39 #include <linux/platform_data/mtd-mxc_nand.h>
  40
  41 #define DRIVER_NAME "mxc_nand"
  42
  43 /* Addresses for NFC registers */
  44 #define NFC_V1_V2_BUF_SIZE              (host->regs + 0x00)
  45 #define NFC_V1_V2_BUF_ADDR              (host->regs + 0x04)
  46 #define NFC_V1_V2_FLASH_ADDR            (host->regs + 0x06)
  47 #define NFC_V1_V2_FLASH_CMD             (host->regs + 0x08)
  48 #define NFC_V1_V2_CONFIG                (host->regs + 0x0a)
  49 #define NFC_V1_V2_ECC_STATUS_RESULT     (host->regs + 0x0c)
  50 #define NFC_V1_V2_RSLTMAIN_AREA         (host->regs + 0x0e)
  51 #define NFC_V21_RSLTSPARE_AREA          (host->regs + 0x10)
  52 #define NFC_V1_V2_WRPROT                (host->regs + 0x12)
  53 #define NFC_V1_UNLOCKSTART_BLKADDR      (host->regs + 0x14)
  54 #define NFC_V1_UNLOCKEND_BLKADDR        (host->regs + 0x16)
  55 #define NFC_V21_UNLOCKSTART_BLKADDR0    (host->regs + 0x20)
  56 #define NFC_V21_UNLOCKSTART_BLKADDR1    (host->regs + 0x24)
  57 #define NFC_V21_UNLOCKSTART_BLKADDR2    (host->regs + 0x28)
  58 #define NFC_V21_UNLOCKSTART_BLKADDR3    (host->regs + 0x2c)
  59 #define NFC_V21_UNLOCKEND_BLKADDR0      (host->regs + 0x22)
  60 #define NFC_V21_UNLOCKEND_BLKADDR1      (host->regs + 0x26)
  61 #define NFC_V21_UNLOCKEND_BLKADDR2      (host->regs + 0x2a)
  62 #define NFC_V21_UNLOCKEND_BLKADDR3      (host->regs + 0x2e)
  63 #define NFC_V1_V2_NF_WRPRST             (host->regs + 0x18)
  64 #define NFC_V1_V2_CONFIG1               (host->regs + 0x1a)
  65 #define NFC_V1_V2_CONFIG2               (host->regs + 0x1c)
  66
  67 #define NFC_V2_CONFIG1_ECC_MODE_4       (1 << 0)
  68 #define NFC_V1_V2_CONFIG1_SP_EN         (1 << 2)
  69 #define NFC_V1_V2_CONFIG1_ECC_EN        (1 << 3)
  70 #define NFC_V1_V2_CONFIG1_INT_MSK       (1 << 4)
  71 #define NFC_V1_V2_CONFIG1_BIG           (1 << 5)
  72 #define NFC_V1_V2_CONFIG1_RST           (1 << 6)
  73 #define NFC_V1_V2_CONFIG1_CE            (1 << 7)
  74 #define NFC_V2_CONFIG1_ONE_CYCLE        (1 << 8)
  75 #define NFC_V2_CONFIG1_PPB(x)           (((x) & 0x3) << 9)
  76 #define NFC_V2_CONFIG1_FP_INT           (1 << 11)
  77
  78 #define NFC_V1_V2_CONFIG2_INT           (1 << 15)
  79
  80 /*
  81  * Operation modes for the NFC. Valid for v1, v2 and v3
  82  * type controllers.
  83  */
  84 #define NFC_CMD                         (1 << 0)
  85 #define NFC_ADDR                        (1 << 1)
  86 #define NFC_INPUT                       (1 << 2)
  87 #define NFC_OUTPUT                      (1 << 3)
  88 #define NFC_ID                          (1 << 4)
  89 #define NFC_STATUS                      (1 << 5)
  90
  91 #define NFC_V3_FLASH_CMD                (host->regs_axi + 0x00)
  92 #define NFC_V3_FLASH_ADDR0              (host->regs_axi + 0x04)
  93
  94 #define NFC_V3_CONFIG1                  (host->regs_axi + 0x34)
  95 #define NFC_V3_CONFIG1_SP_EN            (1 << 0)
  96 #define NFC_V3_CONFIG1_RBA(x)           (((x) & 0x7 ) << 4)
  97
  98 #define NFC_V3_ECC_STATUS_RESULT        (host->regs_axi + 0x38)
  99
 100 #define NFC_V3_LAUNCH                   (host->regs_axi + 0x40)
 101
 102 #define NFC_V3_WRPROT                   (host->regs_ip + 0x0)
 103 #define NFC_V3_WRPROT_LOCK_TIGHT        (1 << 0)
 104 #define NFC_V3_WRPROT_LOCK              (1 << 1)
 105 #define NFC_V3_WRPROT_UNLOCK            (1 << 2)
 106 #define NFC_V3_WRPROT_BLS_UNLOCK        (2 << 6)
 107
 108 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0   (host->regs_ip + 0x04)
 109
 110 #define NFC_V3_CONFIG2                  (host->regs_ip + 0x24)
 111 #define NFC_V3_CONFIG2_PS_512                   (0 << 0)
 112 #define NFC_V3_CONFIG2_PS_2048                  (1 << 0)
 113 #define NFC_V3_CONFIG2_PS_4096                  (2 << 0)
 114 #define NFC_V3_CONFIG2_ONE_CYCLE                (1 << 2)
 115 #define NFC_V3_CONFIG2_ECC_EN                   (1 << 3)
 116 #define NFC_V3_CONFIG2_2CMD_PHASES              (1 << 4)
 117 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0          (1 << 5)
 118 #define NFC_V3_CONFIG2_ECC_MODE_8               (1 << 6)
 119 #define NFC_V3_CONFIG2_PPB(x, shift)            (((x) & 0x3) << shift)
 120 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x)       (((x) & 0x3) << 12)
 121 #define NFC_V3_CONFIG2_INT_MSK                  (1 << 15)
 122 #define NFC_V3_CONFIG2_ST_CMD(x)                (((x) & 0xff) << 24)
 123 #define NFC_V3_CONFIG2_SPAS(x)                  (((x) & 0xff) << 16)
 124
 125 #define NFC_V3_CONFIG3                          (host->regs_ip + 0x28)
 126 #define NFC_V3_CONFIG3_ADD_OP(x)                (((x) & 0x3) << 0)
 127 #define NFC_V3_CONFIG3_FW8                      (1 << 3)
 128 #define NFC_V3_CONFIG3_SBB(x)                   (((x) & 0x7) << 8)
 129 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x)        (((x) & 0x7) << 12)
 130 #define NFC_V3_CONFIG3_RBB_MODE                 (1 << 15)
 131 #define NFC_V3_CONFIG3_NO_SDMA                  (1 << 20)
 132
 133 #define NFC_V3_IPC                      (host->regs_ip + 0x2C)
 134 #define NFC_V3_IPC_CREQ                 (1 << 0)
 135 #define NFC_V3_IPC_INT                  (1 << 31)
 136
 137 #define NFC_V3_DELAY_LINE               (host->regs_ip + 0x34)
 138
 139 struct mxc_nand_host;
 140
 141 struct mxc_nand_devtype_data {
 142         void (*preset)(struct mtd_info *);
 143         void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
 144         void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
 145         void (*send_page)(struct mtd_info *, unsigned int);
 146         void (*send_read_id)(struct mxc_nand_host *);
 147         uint16_t (*get_dev_status)(struct mxc_nand_host *);
 148         int (*check_int)(struct mxc_nand_host *);
 149         void (*irq_control)(struct mxc_nand_host *, int);
 150         u32 (*get_ecc_status)(struct mxc_nand_host *);
 151         const struct mtd_ooblayout_ops *ooblayout;
 152         void (*select_chip)(struct mtd_info *mtd, int chip);
 153         int (*correct_data)(struct mtd_info *mtd, u_char *dat,
 154                         u_char *read_ecc, u_char *calc_ecc);
 155         int (*setup_data_interface)(struct mtd_info *mtd, int csline,
 156                                     const struct nand_data_interface *conf);
 157
 158         /*
 159          * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
 160          * (CONFIG1:INT_MSK is set). To handle this the driver uses
 161          * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
 162          */
 163         int irqpending_quirk;
 164         int needs_ip;
 165
 166         size_t regs_offset;
 167         size_t spare0_offset;
 168         size_t axi_offset;
 169
 170         int spare_len;
 171         int eccbytes;
 172         int eccsize;
 173         int ppb_shift;
 174 };
 175
 176 struct mxc_nand_host {
 177         struct nand_chip        nand;
 178         struct device           *dev;
 179
 180         void __iomem            *spare0;
 181         void __iomem            *main_area0;
 182
 183         void __iomem            *base;
 184         void __iomem            *regs;
 185         void __iomem            *regs_axi;
 186         void __iomem            *regs_ip;
 187         int                     status_request;
 188         struct clk              *clk;
 189         int                     clk_act;
 190         int                     irq;
 191         int                     eccsize;
 192         int                     used_oobsize;
 193         int                     active_cs;
 194
 195         struct completion       op_completion;
 196
 197         uint8_t                 *data_buf;
 198         unsigned int            buf_start;
 199
 200         const struct mxc_nand_devtype_data *devtype_data;
 201         struct mxc_nand_platform_data pdata;
 202 };
 203
 204 static const char * const part_probes[] = {
 205         "cmdlinepart", "RedBoot", "ofpart", NULL };
 206
 207 static void memcpy32_fromio(void *trg, const void __iomem  *src, size_t size)
 208 {
 209         int i;
 210         u32 *t = trg;
 211         const __iomem u32 *s = src;
 212
 213         for (i = 0; i < (size >> 2); i++)
 214                 *t++ = __raw_readl(s++);
 215 }
 216
 217 static void memcpy16_fromio(void *trg, const void __iomem  *src, size_t size)
 218 {
 219         int i;
 220         u16 *t = trg;
 221         const __iomem u16 *s = src;
 222
 223         /* We assume that src (IO) is always 32bit aligned */
 224         if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) {
 225                 memcpy32_fromio(trg, src, size);
 226                 return;
 227         }
 228
 229         for (i = 0; i < (size >> 1); i++)
 230                 *t++ = __raw_readw(s++);
 231 }
 232
 233 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
 234 {
 235         /* __iowrite32_copy use 32bit size values so divide by 4 */
 236         __iowrite32_copy(trg, src, size / 4);
 237 }
 238
 239 static void memcpy16_toio(void __iomem *trg, const void *src, int size)
 240 {
 241         int i;
 242         __iomem u16 *t = trg;
 243         const u16 *s = src;
 244
 245         /* We assume that trg (IO) is always 32bit aligned */
 246         if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) {
 247                 memcpy32_toio(trg, src, size);
 248                 return;
 249         }
 250
 251         for (i = 0; i < (size >> 1); i++)
 252                 __raw_writew(*s++, t++);
 253 }
 254
 255 static int check_int_v3(struct mxc_nand_host *host)
 256 {
 257         uint32_t tmp;
 258
 259         tmp = readl(NFC_V3_IPC);
 260         if (!(tmp & NFC_V3_IPC_INT))
 261                 return 0;
 262
 263         tmp &= ~NFC_V3_IPC_INT;
 264         writel(tmp, NFC_V3_IPC);
 265
 266         return 1;
 267 }
 268
 269 static int check_int_v1_v2(struct mxc_nand_host *host)
 270 {
 271         uint32_t tmp;
 272
 273         tmp = readw(NFC_V1_V2_CONFIG2);
 274         if (!(tmp & NFC_V1_V2_CONFIG2_INT))
 275                 return 0;
 276
 277         if (!host->devtype_data->irqpending_quirk)
 278                 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
 279
 280         return 1;
 281 }
 282
 283 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
 284 {
 285         uint16_t tmp;
 286
 287         tmp = readw(NFC_V1_V2_CONFIG1);
 288
 289         if (activate)
 290                 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
 291         else
 292                 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
 293
 294         writew(tmp, NFC_V1_V2_CONFIG1);
 295 }
 296
 297 static void irq_control_v3(struct mxc_nand_host *host, int activate)
 298 {
 299         uint32_t tmp;
 300
 301         tmp = readl(NFC_V3_CONFIG2);
 302
 303         if (activate)
 304                 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
 305         else
 306                 tmp |= NFC_V3_CONFIG2_INT_MSK;
 307
 308         writel(tmp, NFC_V3_CONFIG2);
 309 }
 310
 311 static void irq_control(struct mxc_nand_host *host, int activate)
 312 {
 313         if (host->devtype_data->irqpending_quirk) {
 314                 if (activate)
 315                         enable_irq(host->irq);
 316                 else
 317                         disable_irq_nosync(host->irq);
 318         } else {
 319                 host->devtype_data->irq_control(host, activate);
 320         }
 321 }
 322
 323 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
 324 {
 325         return readw(NFC_V1_V2_ECC_STATUS_RESULT);
 326 }
 327
 328 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
 329 {
 330         return readl(NFC_V1_V2_ECC_STATUS_RESULT);
 331 }
 332
 333 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
 334 {
 335         return readl(NFC_V3_ECC_STATUS_RESULT);
 336 }
 337
 338 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 339 {
 340         struct mxc_nand_host *host = dev_id;
 341
 342         if (!host->devtype_data->check_int(host))
 343                 return IRQ_NONE;
 344
 345         irq_control(host, 0);
 346
 347         complete(&host->op_completion);
 348
 349         return IRQ_HANDLED;
 350 }
 351
 352 /* This function polls the NANDFC to wait for the basic operation to
 353  * complete by checking the INT bit of config2 register.
 354  */
 355 static int wait_op_done(struct mxc_nand_host *host, int useirq)
 356 {
 357         int ret = 0;
 358
 359         /*
 360          * If operation is already complete, don't bother to setup an irq or a
 361          * loop.
 362          */
 363         if (host->devtype_data->check_int(host))
 364                 return 0;
 365
 366         if (useirq) {
 367                 unsigned long timeout;
 368
 369                 reinit_completion(&host->op_completion);
 370
 371                 irq_control(host, 1);
 372
 373                 timeout = wait_for_completion_timeout(&host->op_completion, HZ);
 374                 if (!timeout && !host->devtype_data->check_int(host)) {
 375                         dev_dbg(host->dev, "timeout waiting for irq\n");
 376                         ret = -ETIMEDOUT;
 377                 }
 378         } else {
 379                 int max_retries = 8000;
 380                 int done;
 381
 382                 do {
 383                         udelay(1);
 384
 385                         done = host->devtype_data->check_int(host);
 386                         if (done)
 387                                 break;
 388
 389                 } while (--max_retries);
 390
 391                 if (!done) {
 392                         dev_dbg(host->dev, "timeout polling for completion\n");
 393                         ret = -ETIMEDOUT;
 394                 }
 395         }
 396
 397         WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
 398
 399         return ret;
 400 }
 401
 402 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 403 {
 404         /* fill command */
 405         writel(cmd, NFC_V3_FLASH_CMD);
 406
 407         /* send out command */
 408         writel(NFC_CMD, NFC_V3_LAUNCH);
 409
 410         /* Wait for operation to complete */
 411         wait_op_done(host, useirq);
 412 }
 413
 414 /* This function issues the specified command to the NAND device and
 415  * waits for completion. */
 416 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 417 {
 418         pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
 419
 420         writew(cmd, NFC_V1_V2_FLASH_CMD);
 421         writew(NFC_CMD, NFC_V1_V2_CONFIG2);
 422
 423         if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
 424                 int max_retries = 100;
 425                 /* Reset completion is indicated by NFC_CONFIG2 */
 426                 /* being set to 0 */
 427                 while (max_retries-- > 0) {
 428                         if (readw(NFC_V1_V2_CONFIG2) == 0) {
 429                                 break;
 430                         }
 431                         udelay(1);
 432                 }
 433                 if (max_retries < 0)
 434                         pr_debug("%s: RESET failed\n", __func__);
 435         } else {
 436                 /* Wait for operation to complete */
 437                 wait_op_done(host, useirq);
 438         }
 439 }
 440
 441 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
 442 {
 443         /* fill address */
 444         writel(addr, NFC_V3_FLASH_ADDR0);
 445
 446         /* send out address */
 447         writel(NFC_ADDR, NFC_V3_LAUNCH);
 448
 449         wait_op_done(host, 0);
 450 }
 451
 452 /* This function sends an address (or partial address) to the
 453  * NAND device. The address is used to select the source/destination for
 454  * a NAND command. */
 455 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
 456 {
 457         pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
 458
 459         writew(addr, NFC_V1_V2_FLASH_ADDR);
 460         writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
 461
 462         /* Wait for operation to complete */
 463         wait_op_done(host, islast);
 464 }
 465
 466 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
 467 {
 468         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 469         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 470         uint32_t tmp;
 471
 472         tmp = readl(NFC_V3_CONFIG1);
 473         tmp &= ~(7 << 4);
 474         writel(tmp, NFC_V3_CONFIG1);
 475
 476         /* transfer data from NFC ram to nand */
 477         writel(ops, NFC_V3_LAUNCH);
 478
 479         wait_op_done(host, false);
 480 }
 481
 482 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
 483 {
 484         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 485         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 486
 487         /* NANDFC buffer 0 is used for page read/write */
 488         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 489
 490         writew(ops, NFC_V1_V2_CONFIG2);
 491
 492         /* Wait for operation to complete */
 493         wait_op_done(host, true);
 494 }
 495
 496 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
 497 {
 498         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 499         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 500         int bufs, i;
 501
 502         if (mtd->writesize > 512)
 503                 bufs = 4;
 504         else
 505                 bufs = 1;
 506
 507         for (i = 0; i < bufs; i++) {
 508
 509                 /* NANDFC buffer 0 is used for page read/write */
 510                 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
 511
 512                 writew(ops, NFC_V1_V2_CONFIG2);
 513
 514                 /* Wait for operation to complete */
 515                 wait_op_done(host, true);
 516         }
 517 }
 518
 519 static void send_read_id_v3(struct mxc_nand_host *host)
 520 {
 521         /* Read ID into main buffer */
 522         writel(NFC_ID, NFC_V3_LAUNCH);
 523
 524         wait_op_done(host, true);
 525
 526         memcpy32_fromio(host->data_buf, host->main_area0, 16);
 527 }
 528
 529 /* Request the NANDFC to perform a read of the NAND device ID. */
 530 static void send_read_id_v1_v2(struct mxc_nand_host *host)
 531 {
 532         /* NANDFC buffer 0 is used for device ID output */
 533         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 534
 535         writew(NFC_ID, NFC_V1_V2_CONFIG2);
 536
 537         /* Wait for operation to complete */
 538         wait_op_done(host, true);
 539
 540         memcpy32_fromio(host->data_buf, host->main_area0, 16);
 541 }
 542
 543 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
 544 {
 545         writew(NFC_STATUS, NFC_V3_LAUNCH);
 546         wait_op_done(host, true);
 547
 548         return readl(NFC_V3_CONFIG1) >> 16;
 549 }
 550
 551 /* This function requests the NANDFC to perform a read of the
 552  * NAND device status and returns the current status. */
 553 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
 554 {
 555         void __iomem *main_buf = host->main_area0;
 556         uint32_t store;
 557         uint16_t ret;
 558
 559         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 560
 561         /*
 562          * The device status is stored in main_area0. To
 563          * prevent corruption of the buffer save the value
 564          * and restore it afterwards.
 565          */
 566         store = readl(main_buf);
 567
 568         writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
 569         wait_op_done(host, true);
 570
 571         ret = readw(main_buf);
 572
 573         writel(store, main_buf);
 574
 575         return ret;
 576 }
 577
 578 /* This functions is used by upper layer to checks if device is ready */
 579 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 580 {
 581         /*
 582          * NFC handles R/B internally. Therefore, this function
 583          * always returns status as ready.
 584          */
 585         return 1;
 586 }
 587
 588 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 589 {
 590         /*
 591          * If HW ECC is enabled, we turn it on during init. There is
 592          * no need to enable again here.
 593          */
 594 }
 595
 596 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
 597                                  u_char *read_ecc, u_char *calc_ecc)
 598 {
 599         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 600         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 601
 602         /*
 603          * 1-Bit errors are automatically corrected in HW.  No need for
 604          * additional correction.  2-Bit errors cannot be corrected by
 605          * HW ECC, so we need to return failure
 606          */
 607         uint16_t ecc_status = get_ecc_status_v1(host);
 608
 609         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 610                 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 611                 return -EBADMSG;
 612         }
 613
 614         return 0;
 615 }
 616
 617 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
 618                                  u_char *read_ecc, u_char *calc_ecc)
 619 {
 620         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 621         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 622         u32 ecc_stat, err;
 623         int no_subpages = 1;
 624         int ret = 0;
 625         u8 ecc_bit_mask, err_limit;
 626
 627         ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
 628         err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
 629
 630         no_subpages = mtd->writesize >> 9;
 631
 632         ecc_stat = host->devtype_data->get_ecc_status(host);
 633
 634         do {
 635                 err = ecc_stat & ecc_bit_mask;
 636                 if (err > err_limit) {
 637                         printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
 638                         return -EBADMSG;
 639                 } else {
 640                         ret += err;
 641                 }
 642                 ecc_stat >>= 4;
 643         } while (--no_subpages);
 644
 645         pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
 646
 647         return ret;
 648 }
 649
 650 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 651                                   u_char *ecc_code)
 652 {
 653         return 0;
 654 }
 655
 656 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 657 {
 658         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 659         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 660         uint8_t ret;
 661
 662         /* Check for status request */
 663         if (host->status_request)
 664                 return host->devtype_data->get_dev_status(host) & 0xFF;
 665
 666         if (nand_chip->options & NAND_BUSWIDTH_16) {
 667                 /* only take the lower byte of each word */
 668                 ret = *(uint16_t *)(host->data_buf + host->buf_start);
 669
 670                 host->buf_start += 2;
 671         } else {
 672                 ret = *(uint8_t *)(host->data_buf + host->buf_start);
 673                 host->buf_start++;
 674         }
 675
 676         pr_debug("%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
 677         return ret;
 678 }
 679
 680 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 681 {
 682         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 683         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 684         uint16_t ret;
 685
 686         ret = *(uint16_t *)(host->data_buf + host->buf_start);
 687         host->buf_start += 2;
 688
 689         return ret;
 690 }
 691
 692 /* Write data of length len to buffer buf. The data to be
 693  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 694  * Operation by the NFC, the data is written to NAND Flash */
 695 static void mxc_nand_write_buf(struct mtd_info *mtd,
 696                                 const u_char *buf, int len)
 697 {
 698         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 699         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 700         u16 col = host->buf_start;
 701         int n = mtd->oobsize + mtd->writesize - col;
 702
 703         n = min(n, len);
 704
 705         memcpy(host->data_buf + col, buf, n);
 706
 707         host->buf_start += n;
 708 }
 709
 710 /* Read the data buffer from the NAND Flash. To read the data from NAND
 711  * Flash first the data output cycle is initiated by the NFC, which copies
 712  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 713  */
 714 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 715 {
 716         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 717         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 718         u16 col = host->buf_start;
 719         int n = mtd->oobsize + mtd->writesize - col;
 720
 721         n = min(n, len);
 722
 723         memcpy(buf, host->data_buf + col, n);
 724
 725         host->buf_start += n;
 726 }
 727
 728 /* This function is used by upper layer for select and
 729  * deselect of the NAND chip */
 730 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
 731 {
 732         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 733         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 734
 735         if (chip == -1) {
 736                 /* Disable the NFC clock */
 737                 if (host->clk_act) {
 738                         clk_disable_unprepare(host->clk);
 739                         host->clk_act = 0;
 740                 }
 741                 return;
 742         }
 743
 744         if (!host->clk_act) {
 745                 /* Enable the NFC clock */
 746                 clk_prepare_enable(host->clk);
 747                 host->clk_act = 1;
 748         }
 749 }
 750
 751 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
 752 {
 753         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 754         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 755
 756         if (chip == -1) {
 757                 /* Disable the NFC clock */
 758                 if (host->clk_act) {
 759                         clk_disable_unprepare(host->clk);
 760                         host->clk_act = 0;
 761                 }
 762                 return;
 763         }
 764
 765         if (!host->clk_act) {
 766                 /* Enable the NFC clock */
 767                 clk_prepare_enable(host->clk);
 768                 host->clk_act = 1;
 769         }
 770
 771         host->active_cs = chip;
 772         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 773 }
 774
 775 /*
 776  * The controller splits a page into data chunks of 512 bytes + partial oob.
 777  * There are writesize / 512 such chunks, the size of the partial oob parts is
 778  * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then
 779  * contains additionally the byte lost by rounding (if any).
 780  * This function handles the needed shuffling between host->data_buf (which
 781  * holds a page in natural order, i.e. writesize bytes data + oobsize bytes
 782  * spare) and the NFC buffer.
 783  */
 784 static void copy_spare(struct mtd_info *mtd, bool bfrom)
 785 {
 786         struct nand_chip *this = mtd_to_nand(mtd);
 787         struct mxc_nand_host *host = nand_get_controller_data(this);
 788         u16 i, oob_chunk_size;
 789         u16 num_chunks = mtd->writesize / 512;
 790
 791         u8 *d = host->data_buf + mtd->writesize;
 792         u8 __iomem *s = host->spare0;
 793         u16 sparebuf_size = host->devtype_data->spare_len;
 794
 795         /* size of oob chunk for all but possibly the last one */
 796         oob_chunk_size = (host->used_oobsize / num_chunks) & ~1;
 797
 798         if (bfrom) {
 799                 for (i = 0; i < num_chunks - 1; i++)
 800                         memcpy16_fromio(d + i * oob_chunk_size,
 801                                         s + i * sparebuf_size,
 802                                         oob_chunk_size);
 803
 804                 /* the last chunk */
 805                 memcpy16_fromio(d + i * oob_chunk_size,
 806                                 s + i * sparebuf_size,
 807                                 host->used_oobsize - i * oob_chunk_size);
 808         } else {
 809                 for (i = 0; i < num_chunks - 1; i++)
 810                         memcpy16_toio(&s[i * sparebuf_size],
 811                                       &d[i * oob_chunk_size],
 812                                       oob_chunk_size);
 813
 814                 /* the last chunk */
 815                 memcpy16_toio(&s[i * sparebuf_size],
 816                               &d[i * oob_chunk_size],
 817                               host->used_oobsize - i * oob_chunk_size);
 818         }
 819 }
 820
 821 /*
 822  * MXC NANDFC can only perform full page+spare or spare-only read/write.  When
 823  * the upper layers perform a read/write buf operation, the saved column address
 824  * is used to index into the full page. So usually this function is called with
 825  * column == 0 (unless no column cycle is needed indicated by column == -1)
 826  */
 827 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
 828 {
 829         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 830         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 831
 832         /* Write out column address, if necessary */
 833         if (column != -1) {
 834                 host->devtype_data->send_addr(host, column & 0xff,
 835                                               page_addr == -1);
 836                 if (mtd->writesize > 512)
 837                         /* another col addr cycle for 2k page */
 838                         host->devtype_data->send_addr(host,
 839                                                       (column >> 8) & 0xff,
 840                                                       false);
 841         }
 842
 843         /* Write out page address, if necessary */
 844         if (page_addr != -1) {
 845                 /* paddr_0 - p_addr_7 */
 846                 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
 847
 848                 if (mtd->writesize > 512) {
 849                         if (mtd->size >= 0x10000000) {
 850                                 /* paddr_8 - paddr_15 */
 851                                 host->devtype_data->send_addr(host,
 852                                                 (page_addr >> 8) & 0xff,
 853                                                 false);
 854                                 host->devtype_data->send_addr(host,
 855                                                 (page_addr >> 16) & 0xff,
 856                                                 true);
 857                         } else
 858                                 /* paddr_8 - paddr_15 */
 859                                 host->devtype_data->send_addr(host,
 860                                                 (page_addr >> 8) & 0xff, true);
 861                 } else {
 862                         /* One more address cycle for higher density devices */
 863                         if (mtd->size >= 0x4000000) {
 864                                 /* paddr_8 - paddr_15 */
 865                                 host->devtype_data->send_addr(host,
 866                                                 (page_addr >> 8) & 0xff,
 867                                                 false);
 868                                 host->devtype_data->send_addr(host,
 869                                                 (page_addr >> 16) & 0xff,
 870                                                 true);
 871                         } else
 872                                 /* paddr_8 - paddr_15 */
 873                                 host->devtype_data->send_addr(host,
 874                                                 (page_addr >> 8) & 0xff, true);
 875                 }
 876         }
 877 }
 878
 879 #define MXC_V1_ECCBYTES         5
 880
 881 static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section,
 882                                 struct mtd_oob_region *oobregion)
 883 {
 884         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 885
 886         if (section >= nand_chip->ecc.steps)
 887                 return -ERANGE;
 888
 889         oobregion->offset = (section * 16) + 6;
 890         oobregion->length = MXC_V1_ECCBYTES;
 891
 892         return 0;
 893 }
 894
 895 static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section,
 896                                  struct mtd_oob_region *oobregion)
 897 {
 898         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 899
 900         if (section > nand_chip->ecc.steps)
 901                 return -ERANGE;
 902
 903         if (!section) {
 904                 if (mtd->writesize <= 512) {
 905                         oobregion->offset = 0;
 906                         oobregion->length = 5;
 907                 } else {
 908                         oobregion->offset = 2;
 909                         oobregion->length = 4;
 910                 }
 911         } else {
 912                 oobregion->offset = ((section - 1) * 16) + MXC_V1_ECCBYTES + 6;
 913                 if (section < nand_chip->ecc.steps)
 914                         oobregion->length = (section * 16) + 6 -
 915                                             oobregion->offset;
 916                 else
 917                         oobregion->length = mtd->oobsize - oobregion->offset;
 918         }
 919
 920         return 0;
 921 }
 922
 923 static const struct mtd_ooblayout_ops mxc_v1_ooblayout_ops = {
 924         .ecc = mxc_v1_ooblayout_ecc,
 925         .free = mxc_v1_ooblayout_free,
 926 };
 927
 928 static int mxc_v2_ooblayout_ecc(struct mtd_info *mtd, int section,
 929                                 struct mtd_oob_region *oobregion)
 930 {
 931         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 932         int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
 933
 934         if (section >= nand_chip->ecc.steps)
 935                 return -ERANGE;
 936
 937         oobregion->offset = (section * stepsize) + 7;
 938         oobregion->length = nand_chip->ecc.bytes;
 939
 940         return 0;
 941 }
 942
 943 static int mxc_v2_ooblayout_free(struct mtd_info *mtd, int section,
 944                                  struct mtd_oob_region *oobregion)
 945 {
 946         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 947         int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
 948
 949         if (section >= nand_chip->ecc.steps)
 950                 return -ERANGE;
 951
 952         if (!section) {
 953                 if (mtd->writesize <= 512) {
 954                         oobregion->offset = 0;
 955                         oobregion->length = 5;
 956                 } else {
 957                         oobregion->offset = 2;
 958                         oobregion->length = 4;
 959                 }
 960         } else {
 961                 oobregion->offset = section * stepsize;
 962                 oobregion->length = 7;
 963         }
 964
 965         return 0;
 966 }
 967
 968 static const struct mtd_ooblayout_ops mxc_v2_ooblayout_ops = {
 969         .ecc = mxc_v2_ooblayout_ecc,
 970         .free = mxc_v2_ooblayout_free,
 971 };
 972
 973 /*
 974  * v2 and v3 type controllers can do 4bit or 8bit ecc depending
 975  * on how much oob the nand chip has. For 8bit ecc we need at least
 976  * 26 bytes of oob data per 512 byte block.
 977  */
 978 static int get_eccsize(struct mtd_info *mtd)
 979 {
 980         int oobbytes_per_512 = 0;
 981
 982         oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
 983
 984         if (oobbytes_per_512 < 26)
 985                 return 4;
 986         else
 987                 return 8;
 988 }
 989
 990 static void preset_v1(struct mtd_info *mtd)
 991 {
 992         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 993         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 994         uint16_t config1 = 0;
 995
 996         if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize)
 997                 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
 998
 999         if (!host->devtype_data->irqpending_quirk)
1000                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1001
1002         host->eccsize = 1;
1003
1004         writew(config1, NFC_V1_V2_CONFIG1);
1005         /* preset operation */
1006
1007         /* Unlock the internal RAM Buffer */
1008         writew(0x2, NFC_V1_V2_CONFIG);
1009
1010         /* Blocks to be unlocked */
1011         writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
1012         writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
1013
1014         /* Unlock Block Command for given address range */
1015         writew(0x4, NFC_V1_V2_WRPROT);
1016 }
1017
1018 static int mxc_nand_v2_setup_data_interface(struct mtd_info *mtd, int csline,
1019                                         const struct nand_data_interface *conf)
1020 {
1021         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1022         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1023         int tRC_min_ns, tRC_ps, ret;
1024         unsigned long rate, rate_round;
1025         const struct nand_sdr_timings *timings;
1026         u16 config1;
1027
1028         timings = nand_get_sdr_timings(conf);
1029         if (IS_ERR(timings))
1030                 return -ENOTSUPP;
1031
1032         config1 = readw(NFC_V1_V2_CONFIG1);
1033
1034         tRC_min_ns = timings->tRC_min / 1000;
1035         rate = 1000000000 / tRC_min_ns;
1036
1037         /*
1038          * For tRC < 30ns we have to use EDO mode. In this case the controller
1039          * does one access per clock cycle. Otherwise the controller does one
1040          * access in two clock cycles, thus we have to double the rate to the
1041          * controller.
1042          */
1043         if (tRC_min_ns < 30) {
1044                 rate_round = clk_round_rate(host->clk, rate);
1045                 config1 |= NFC_V2_CONFIG1_ONE_CYCLE;
1046                 tRC_ps = 1000000000 / (rate_round / 1000);
1047         } else {
1048                 rate *= 2;
1049                 rate_round = clk_round_rate(host->clk, rate);
1050                 config1 &= ~NFC_V2_CONFIG1_ONE_CYCLE;
1051                 tRC_ps = 1000000000 / (rate_round / 1000 / 2);
1052         }
1053
1054         /*
1055          * The timing values compared against are from the i.MX25 Automotive
1056          * datasheet, Table 50. NFC Timing Parameters
1057          */
1058         if (timings->tCLS_min > tRC_ps - 1000 ||
1059             timings->tCLH_min > tRC_ps - 2000 ||
1060             timings->tCS_min > tRC_ps - 1000 ||
1061             timings->tCH_min > tRC_ps - 2000 ||
1062             timings->tWP_min > tRC_ps - 1500 ||
1063             timings->tALS_min > tRC_ps ||
1064             timings->tALH_min > tRC_ps - 3000 ||
1065             timings->tDS_min > tRC_ps ||
1066             timings->tDH_min > tRC_ps - 5000 ||
1067             timings->tWC_min > 2 * tRC_ps ||
1068             timings->tWH_min > tRC_ps - 2500 ||
1069             timings->tRR_min > 6 * tRC_ps ||
1070             timings->tRP_min > 3 * tRC_ps / 2 ||
1071             timings->tRC_min > 2 * tRC_ps ||
1072             timings->tREH_min > (tRC_ps / 2) - 2500) {
1073                 dev_dbg(host->dev, "Timing out of bounds\n");
1074                 return -EINVAL;
1075         }
1076
1077         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1078                 return 0;
1079
1080         ret = clk_set_rate(host->clk, rate);
1081         if (ret)
1082                 return ret;
1083
1084         writew(config1, NFC_V1_V2_CONFIG1);
1085
1086         dev_dbg(host->dev, "Setting rate to %ldHz, %s mode\n", rate_round,
1087                 config1 & NFC_V2_CONFIG1_ONE_CYCLE ? "One cycle (EDO)" :
1088                 "normal");
1089
1090         return 0;
1091 }
1092
1093 static void preset_v2(struct mtd_info *mtd)
1094 {
1095         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1096         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1097         uint16_t config1 = 0;
1098
1099         config1 |= NFC_V2_CONFIG1_FP_INT;
1100
1101         if (!host->devtype_data->irqpending_quirk)
1102                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1103
1104         if (mtd->writesize) {
1105                 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
1106
1107                 if (nand_chip->ecc.mode == NAND_ECC_HW)
1108                         config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1109
1110                 host->eccsize = get_eccsize(mtd);
1111                 if (host->eccsize == 4)
1112                         config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
1113
1114                 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
1115         } else {
1116                 host->eccsize = 1;
1117         }
1118
1119         writew(config1, NFC_V1_V2_CONFIG1);
1120         /* preset operation */
1121
1122         /* spare area size in 16-bit half-words */
1123         writew(mtd->oobsize / 2, NFC_V21_RSLTSPARE_AREA);
1124
1125         /* Unlock the internal RAM Buffer */
1126         writew(0x2, NFC_V1_V2_CONFIG);
1127
1128         /* Blocks to be unlocked */
1129         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
1130         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
1131         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
1132         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
1133         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
1134         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
1135         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
1136         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
1137
1138         /* Unlock Block Command for given address range */
1139         writew(0x4, NFC_V1_V2_WRPROT);
1140 }
1141
1142 static void preset_v3(struct mtd_info *mtd)
1143 {
1144         struct nand_chip *chip = mtd_to_nand(mtd);
1145         struct mxc_nand_host *host = nand_get_controller_data(chip);
1146         uint32_t config2, config3;
1147         int i, addr_phases;
1148
1149         writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
1150         writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
1151
1152         /* Unlock the internal RAM Buffer */
1153         writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1154                         NFC_V3_WRPROT);
1155
1156         /* Blocks to be unlocked */
1157         for (i = 0; i < NAND_MAX_CHIPS; i++)
1158                 writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1159
1160         writel(0, NFC_V3_IPC);
1161
1162         config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1163                 NFC_V3_CONFIG2_2CMD_PHASES |
1164                 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1165                 NFC_V3_CONFIG2_ST_CMD(0x70) |
1166                 NFC_V3_CONFIG2_INT_MSK |
1167                 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1168
1169         addr_phases = fls(chip->pagemask) >> 3;
1170
1171         if (mtd->writesize == 2048) {
1172                 config2 |= NFC_V3_CONFIG2_PS_2048;
1173                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1174         } else if (mtd->writesize == 4096) {
1175                 config2 |= NFC_V3_CONFIG2_PS_4096;
1176                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1177         } else {
1178                 config2 |= NFC_V3_CONFIG2_PS_512;
1179                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1180         }
1181
1182         if (mtd->writesize) {
1183                 if (chip->ecc.mode == NAND_ECC_HW)
1184                         config2 |= NFC_V3_CONFIG2_ECC_EN;
1185
1186                 config2 |= NFC_V3_CONFIG2_PPB(
1187                                 ffs(mtd->erasesize / mtd->writesize) - 6,
1188                                 host->devtype_data->ppb_shift);
1189                 host->eccsize = get_eccsize(mtd);
1190                 if (host->eccsize == 8)
1191                         config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1192         }
1193
1194         writel(config2, NFC_V3_CONFIG2);
1195
1196         config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1197                         NFC_V3_CONFIG3_NO_SDMA |
1198                         NFC_V3_CONFIG3_RBB_MODE |
1199                         NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1200                         NFC_V3_CONFIG3_ADD_OP(0);
1201
1202         if (!(chip->options & NAND_BUSWIDTH_16))
1203                 config3 |= NFC_V3_CONFIG3_FW8;
1204
1205         writel(config3, NFC_V3_CONFIG3);
1206
1207         writel(0, NFC_V3_DELAY_LINE);
1208 }
1209
1210 /* Used by the upper layer to write command to NAND Flash for
1211  * different operations to be carried out on NAND Flash */
1212 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1213                                 int column, int page_addr)
1214 {
1215         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1216         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1217
1218         pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1219               command, column, page_addr);
1220
1221         /* Reset command state information */
1222         host->status_request = false;
1223
1224         /* Command pre-processing step */
1225         switch (command) {
1226         case NAND_CMD_RESET:
1227                 host->devtype_data->preset(mtd);
1228                 host->devtype_data->send_cmd(host, command, false);
1229                 break;
1230
1231         case NAND_CMD_STATUS:
1232                 host->buf_start = 0;
1233                 host->status_request = true;
1234
1235                 host->devtype_data->send_cmd(host, command, true);
1236                 WARN_ONCE(column != -1 || page_addr != -1,
1237                           "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1238                           command, column, page_addr);
1239                 mxc_do_addr_cycle(mtd, column, page_addr);
1240                 break;
1241
1242         case NAND_CMD_READ0:
1243         case NAND_CMD_READOOB:
1244                 if (command == NAND_CMD_READ0)
1245                         host->buf_start = column;
1246                 else
1247                         host->buf_start = column + mtd->writesize;
1248
1249                 command = NAND_CMD_READ0; /* only READ0 is valid */
1250
1251                 host->devtype_data->send_cmd(host, command, false);
1252                 WARN_ONCE(column < 0,
1253                           "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1254                           command, column, page_addr);
1255                 mxc_do_addr_cycle(mtd, 0, page_addr);
1256
1257                 if (mtd->writesize > 512)
1258                         host->devtype_data->send_cmd(host,
1259                                         NAND_CMD_READSTART, true);
1260
1261                 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1262
1263                 memcpy32_fromio(host->data_buf, host->main_area0,
1264                                 mtd->writesize);
1265                 copy_spare(mtd, true);
1266                 break;
1267
1268         case NAND_CMD_SEQIN:
1269                 if (column >= mtd->writesize)
1270                         /* call ourself to read a page */
1271                         mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1272
1273                 host->buf_start = column;
1274
1275                 host->devtype_data->send_cmd(host, command, false);
1276                 WARN_ONCE(column < -1,
1277                           "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1278                           command, column, page_addr);
1279                 mxc_do_addr_cycle(mtd, 0, page_addr);
1280                 break;
1281
1282         case NAND_CMD_PAGEPROG:
1283                 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1284                 copy_spare(mtd, false);
1285                 host->devtype_data->send_page(mtd, NFC_INPUT);
1286                 host->devtype_data->send_cmd(host, command, true);
1287                 WARN_ONCE(column != -1 || page_addr != -1,
1288                           "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1289                           command, column, page_addr);
1290                 mxc_do_addr_cycle(mtd, column, page_addr);
1291                 break;
1292
1293         case NAND_CMD_READID:
1294                 host->devtype_data->send_cmd(host, command, true);
1295                 mxc_do_addr_cycle(mtd, column, page_addr);
1296                 host->devtype_data->send_read_id(host);
1297                 host->buf_start = 0;
1298                 break;
1299
1300         case NAND_CMD_ERASE1:
1301         case NAND_CMD_ERASE2:
1302                 host->devtype_data->send_cmd(host, command, false);
1303                 WARN_ONCE(column != -1,
1304                           "Unexpected column value (cmd=%u, col=%d)\n",
1305                           command, column);
1306                 mxc_do_addr_cycle(mtd, column, page_addr);
1307
1308                 break;
1309         case NAND_CMD_PARAM:
1310                 host->devtype_data->send_cmd(host, command, false);
1311                 mxc_do_addr_cycle(mtd, column, page_addr);
1312                 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1313                 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1314                 host->buf_start = 0;
1315                 break;
1316         default:
1317                 WARN_ONCE(1, "Unimplemented command (cmd=%u)\n",
1318                           command);
1319                 break;
1320         }
1321 }
1322
1323 static int mxc_nand_onfi_set_features(struct mtd_info *mtd,
1324                                       struct nand_chip *chip, int addr,
1325                                       u8 *subfeature_param)
1326 {
1327         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1328         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1329         int i;
1330
1331         if (!chip->onfi_version ||
1332             !(le16_to_cpu(chip->onfi_params.opt_cmd)
1333               & ONFI_OPT_CMD_SET_GET_FEATURES))
1334                 return -EINVAL;
1335
1336         host->buf_start = 0;
1337
1338         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1339                 chip->write_byte(mtd, subfeature_param[i]);
1340
1341         memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1342         host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false);
1343         mxc_do_addr_cycle(mtd, addr, -1);
1344         host->devtype_data->send_page(mtd, NFC_INPUT);
1345
1346         return 0;
1347 }
1348
1349 static int mxc_nand_onfi_get_features(struct mtd_info *mtd,
1350                                       struct nand_chip *chip, int addr,
1351                                       u8 *subfeature_param)
1352 {
1353         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1354         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1355         int i;
1356
1357         if (!chip->onfi_version ||
1358             !(le16_to_cpu(chip->onfi_params.opt_cmd)
1359               & ONFI_OPT_CMD_SET_GET_FEATURES))
1360                 return -EINVAL;
1361
1362         host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false);
1363         mxc_do_addr_cycle(mtd, addr, -1);
1364         host->devtype_data->send_page(mtd, NFC_OUTPUT);
1365         memcpy32_fromio(host->data_buf, host->main_area0, 512);
1366         host->buf_start = 0;
1367
1368         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1369                 *subfeature_param++ = chip->read_byte(mtd);
1370
1371         return 0;
1372 }
1373
1374 /*
1375  * The generic flash bbt decriptors overlap with our ecc
1376  * hardware, so define some i.MX specific ones.
1377  */
1378 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1379 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1380
1381 static struct nand_bbt_descr bbt_main_descr = {
1382         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1383             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1384         .offs = 0,
1385         .len = 4,
1386         .veroffs = 4,
1387         .maxblocks = 4,
1388         .pattern = bbt_pattern,
1389 };
1390
1391 static struct nand_bbt_descr bbt_mirror_descr = {
1392         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1393             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1394         .offs = 0,
1395         .len = 4,
1396         .veroffs = 4,
1397         .maxblocks = 4,
1398         .pattern = mirror_pattern,
1399 };
1400
1401 /* v1 + irqpending_quirk: i.MX21 */
1402 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1403         .preset = preset_v1,
1404         .send_cmd = send_cmd_v1_v2,
1405         .send_addr = send_addr_v1_v2,
1406         .send_page = send_page_v1,
1407         .send_read_id = send_read_id_v1_v2,
1408         .get_dev_status = get_dev_status_v1_v2,
1409         .check_int = check_int_v1_v2,
1410         .irq_control = irq_control_v1_v2,
1411         .get_ecc_status = get_ecc_status_v1,
1412         .ooblayout = &mxc_v1_ooblayout_ops,
1413         .select_chip = mxc_nand_select_chip_v1_v3,
1414         .correct_data = mxc_nand_correct_data_v1,
1415         .irqpending_quirk = 1,
1416         .needs_ip = 0,
1417         .regs_offset = 0xe00,
1418         .spare0_offset = 0x800,
1419         .spare_len = 16,
1420         .eccbytes = 3,
1421         .eccsize = 1,
1422 };
1423
1424 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1425 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1426         .preset = preset_v1,
1427         .send_cmd = send_cmd_v1_v2,
1428         .send_addr = send_addr_v1_v2,
1429         .send_page = send_page_v1,
1430         .send_read_id = send_read_id_v1_v2,
1431         .get_dev_status = get_dev_status_v1_v2,
1432         .check_int = check_int_v1_v2,
1433         .irq_control = irq_control_v1_v2,
1434         .get_ecc_status = get_ecc_status_v1,
1435         .ooblayout = &mxc_v1_ooblayout_ops,
1436         .select_chip = mxc_nand_select_chip_v1_v3,
1437         .correct_data = mxc_nand_correct_data_v1,
1438         .irqpending_quirk = 0,
1439         .needs_ip = 0,
1440         .regs_offset = 0xe00,
1441         .spare0_offset = 0x800,
1442         .axi_offset = 0,
1443         .spare_len = 16,
1444         .eccbytes = 3,
1445         .eccsize = 1,
1446 };
1447
1448 /* v21: i.MX25, i.MX35 */
1449 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1450         .preset = preset_v2,
1451         .send_cmd = send_cmd_v1_v2,
1452         .send_addr = send_addr_v1_v2,
1453         .send_page = send_page_v2,
1454         .send_read_id = send_read_id_v1_v2,
1455         .get_dev_status = get_dev_status_v1_v2,
1456         .check_int = check_int_v1_v2,
1457         .irq_control = irq_control_v1_v2,
1458         .get_ecc_status = get_ecc_status_v2,
1459         .ooblayout = &mxc_v2_ooblayout_ops,
1460         .select_chip = mxc_nand_select_chip_v2,
1461         .correct_data = mxc_nand_correct_data_v2_v3,
1462         .setup_data_interface = mxc_nand_v2_setup_data_interface,
1463         .irqpending_quirk = 0,
1464         .needs_ip = 0,
1465         .regs_offset = 0x1e00,
1466         .spare0_offset = 0x1000,
1467         .axi_offset = 0,
1468         .spare_len = 64,
1469         .eccbytes = 9,
1470         .eccsize = 0,
1471 };
1472
1473 /* v3.2a: i.MX51 */
1474 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1475         .preset = preset_v3,
1476         .send_cmd = send_cmd_v3,
1477         .send_addr = send_addr_v3,
1478         .send_page = send_page_v3,
1479         .send_read_id = send_read_id_v3,
1480         .get_dev_status = get_dev_status_v3,
1481         .check_int = check_int_v3,
1482         .irq_control = irq_control_v3,
1483         .get_ecc_status = get_ecc_status_v3,
1484         .ooblayout = &mxc_v2_ooblayout_ops,
1485         .select_chip = mxc_nand_select_chip_v1_v3,
1486         .correct_data = mxc_nand_correct_data_v2_v3,
1487         .irqpending_quirk = 0,
1488         .needs_ip = 1,
1489         .regs_offset = 0,
1490         .spare0_offset = 0x1000,
1491         .axi_offset = 0x1e00,
1492         .spare_len = 64,
1493         .eccbytes = 0,
1494         .eccsize = 0,
1495         .ppb_shift = 7,
1496 };
1497
1498 /* v3.2b: i.MX53 */
1499 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1500         .preset = preset_v3,
1501         .send_cmd = send_cmd_v3,
1502         .send_addr = send_addr_v3,
1503         .send_page = send_page_v3,
1504         .send_read_id = send_read_id_v3,
1505         .get_dev_status = get_dev_status_v3,
1506         .check_int = check_int_v3,
1507         .irq_control = irq_control_v3,
1508         .get_ecc_status = get_ecc_status_v3,
1509         .ooblayout = &mxc_v2_ooblayout_ops,
1510         .select_chip = mxc_nand_select_chip_v1_v3,
1511         .correct_data = mxc_nand_correct_data_v2_v3,
1512         .irqpending_quirk = 0,
1513         .needs_ip = 1,
1514         .regs_offset = 0,
1515         .spare0_offset = 0x1000,
1516         .axi_offset = 0x1e00,
1517         .spare_len = 64,
1518         .eccbytes = 0,
1519         .eccsize = 0,
1520         .ppb_shift = 8,
1521 };
1522
1523 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1524 {
1525         return host->devtype_data == &imx21_nand_devtype_data;
1526 }
1527
1528 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1529 {
1530         return host->devtype_data == &imx27_nand_devtype_data;
1531 }
1532
1533 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1534 {
1535         return host->devtype_data == &imx25_nand_devtype_data;
1536 }
1537
1538 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1539 {
1540         return host->devtype_data == &imx51_nand_devtype_data;
1541 }
1542
1543 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1544 {
1545         return host->devtype_data == &imx53_nand_devtype_data;
1546 }
1547
1548 static const struct platform_device_id mxcnd_devtype[] = {
1549         {
1550                 .name = "imx21-nand",
1551                 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1552         }, {
1553                 .name = "imx27-nand",
1554                 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1555         }, {
1556                 .name = "imx25-nand",
1557                 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1558         }, {
1559                 .name = "imx51-nand",
1560                 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1561         }, {
1562                 .name = "imx53-nand",
1563                 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1564         }, {
1565                 /* sentinel */
1566         }
1567 };
1568 MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1569
1570 #ifdef CONFIG_OF
1571 static const struct of_device_id mxcnd_dt_ids[] = {
1572         {
1573                 .compatible = "fsl,imx21-nand",
1574                 .data = &imx21_nand_devtype_data,
1575         }, {
1576                 .compatible = "fsl,imx27-nand",
1577                 .data = &imx27_nand_devtype_data,
1578         }, {
1579                 .compatible = "fsl,imx25-nand",
1580                 .data = &imx25_nand_devtype_data,
1581         }, {
1582                 .compatible = "fsl,imx51-nand",
1583                 .data = &imx51_nand_devtype_data,
1584         }, {
1585                 .compatible = "fsl,imx53-nand",
1586                 .data = &imx53_nand_devtype_data,
1587         },
1588         { /* sentinel */ }
1589 };
1590 MODULE_DEVICE_TABLE(of, mxcnd_dt_ids);
1591
1592 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1593 {
1594         struct device_node *np = host->dev->of_node;
1595         const struct of_device_id *of_id =
1596                 of_match_device(mxcnd_dt_ids, host->dev);
1597
1598         if (!np)
1599                 return 1;
1600
1601         host->devtype_data = of_id->data;
1602
1603         return 0;
1604 }
1605 #else
1606 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1607 {
1608         return 1;
1609 }
1610 #endif
1611
1612 static int mxcnd_probe(struct platform_device *pdev)
1613 {
1614         struct nand_chip *this;
1615         struct mtd_info *mtd;
1616         struct mxc_nand_host *host;
1617         struct resource *res;
1618         int err = 0;
1619
1620         /* Allocate memory for MTD device structure and private data */
1621         host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1622                         GFP_KERNEL);
1623         if (!host)
1624                 return -ENOMEM;
1625
1626         /* allocate a temporary buffer for the nand_scan_ident() */
1627         host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1628         if (!host->data_buf)
1629                 return -ENOMEM;
1630
1631         host->dev = &pdev->dev;
1632         /* structures must be linked */
1633         this = &host->nand;
1634         mtd = nand_to_mtd(this);
1635         mtd->dev.parent = &pdev->dev;
1636         mtd->name = DRIVER_NAME;
1637
1638         /* 50 us command delay time */
1639         this->chip_delay = 5;
1640
1641         nand_set_controller_data(this, host);
1642         nand_set_flash_node(this, pdev->dev.of_node),
1643         this->dev_ready = mxc_nand_dev_ready;
1644         this->cmdfunc = mxc_nand_command;
1645         this->read_byte = mxc_nand_read_byte;
1646         this->read_word = mxc_nand_read_word;
1647         this->write_buf = mxc_nand_write_buf;
1648         this->read_buf = mxc_nand_read_buf;
1649         this->onfi_set_features = mxc_nand_onfi_set_features;
1650         this->onfi_get_features = mxc_nand_onfi_get_features;
1651
1652         host->clk = devm_clk_get(&pdev->dev, NULL);
1653         if (IS_ERR(host->clk))
1654                 return PTR_ERR(host->clk);
1655
1656         err = mxcnd_probe_dt(host);
1657         if (err > 0) {
1658                 struct mxc_nand_platform_data *pdata =
1659                                         dev_get_platdata(&pdev->dev);
1660                 if (pdata) {
1661                         host->pdata = *pdata;
1662                         host->devtype_data = (struct mxc_nand_devtype_data *)
1663                                                 pdev->id_entry->driver_data;
1664                 } else {
1665                         err = -ENODEV;
1666                 }
1667         }
1668         if (err < 0)
1669                 return err;
1670
1671         this->setup_data_interface = host->devtype_data->setup_data_interface;
1672
1673         if (host->devtype_data->needs_ip) {
1674                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1675                 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1676                 if (IS_ERR(host->regs_ip))
1677                         return PTR_ERR(host->regs_ip);
1678
1679                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1680         } else {
1681                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1682         }
1683
1684         host->base = devm_ioremap_resource(&pdev->dev, res);
1685         if (IS_ERR(host->base))
1686                 return PTR_ERR(host->base);
1687
1688         host->main_area0 = host->base;
1689
1690         if (host->devtype_data->regs_offset)
1691                 host->regs = host->base + host->devtype_data->regs_offset;
1692         host->spare0 = host->base + host->devtype_data->spare0_offset;
1693         if (host->devtype_data->axi_offset)
1694                 host->regs_axi = host->base + host->devtype_data->axi_offset;
1695
1696         this->ecc.bytes = host->devtype_data->eccbytes;
1697         host->eccsize = host->devtype_data->eccsize;
1698
1699         this->select_chip = host->devtype_data->select_chip;
1700         this->ecc.size = 512;
1701         mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
1702
1703         if (host->pdata.hw_ecc) {
1704                 this->ecc.mode = NAND_ECC_HW;
1705         } else {
1706                 this->ecc.mode = NAND_ECC_SOFT;
1707                 this->ecc.algo = NAND_ECC_HAMMING;
1708         }
1709
1710         /* NAND bus width determines access functions used by upper layer */
1711         if (host->pdata.width == 2)
1712                 this->options |= NAND_BUSWIDTH_16;
1713
1714         /* update flash based bbt */
1715         if (host->pdata.flash_bbt)
1716                 this->bbt_options |= NAND_BBT_USE_FLASH;
1717
1718         init_completion(&host->op_completion);
1719
1720         host->irq = platform_get_irq(pdev, 0);
1721         if (host->irq < 0)
1722                 return host->irq;
1723
1724         /*
1725          * Use host->devtype_data->irq_control() here instead of irq_control()
1726          * because we must not disable_irq_nosync without having requested the
1727          * irq.
1728          */
1729         host->devtype_data->irq_control(host, 0);
1730
1731         err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1732                         0, DRIVER_NAME, host);
1733         if (err)
1734                 return err;
1735
1736         err = clk_prepare_enable(host->clk);
1737         if (err)
1738                 return err;
1739         host->clk_act = 1;
1740
1741         /*
1742          * Now that we "own" the interrupt make sure the interrupt mask bit is
1743          * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1744          * on this machine.
1745          */
1746         if (host->devtype_data->irqpending_quirk) {
1747                 disable_irq_nosync(host->irq);
1748                 host->devtype_data->irq_control(host, 1);
1749         }
1750
1751         /* first scan to find the device and get the page size */
1752         err = nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL);
1753         if (err)
1754                 goto escan;
1755
1756         switch (this->ecc.mode) {
1757         case NAND_ECC_HW:
1758                 this->ecc.calculate = mxc_nand_calculate_ecc;
1759                 this->ecc.hwctl = mxc_nand_enable_hwecc;
1760                 this->ecc.correct = host->devtype_data->correct_data;
1761                 break;
1762
1763         case NAND_ECC_SOFT:
1764                 break;
1765
1766         default:
1767                 err = -EINVAL;
1768                 goto escan;
1769         }
1770
1771         if (this->bbt_options & NAND_BBT_USE_FLASH) {
1772                 this->bbt_td = &bbt_main_descr;
1773                 this->bbt_md = &bbt_mirror_descr;
1774         }
1775
1776         /* allocate the right size buffer now */
1777         devm_kfree(&pdev->dev, (void *)host->data_buf);
1778         host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize,
1779                                         GFP_KERNEL);
1780         if (!host->data_buf) {
1781                 err = -ENOMEM;
1782                 goto escan;
1783         }
1784
1785         /* Call preset again, with correct writesize this time */
1786         host->devtype_data->preset(mtd);
1787
1788         if (!this->ecc.bytes) {
1789                 if (host->eccsize == 8)
1790                         this->ecc.bytes = 18;
1791                 else if (host->eccsize == 4)
1792                         this->ecc.bytes = 9;
1793         }
1794
1795         /*
1796          * Experimentation shows that i.MX NFC can only handle up to 218 oob
1797          * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare()
1798          * into copying invalid data to/from the spare IO buffer, as this
1799          * might cause ECC data corruption when doing sub-page write to a
1800          * partially written page.
1801          */
1802         host->used_oobsize = min(mtd->oobsize, 218U);
1803
1804         if (this->ecc.mode == NAND_ECC_HW) {
1805                 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1806                         this->ecc.strength = 1;
1807                 else
1808                         this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1809         }
1810
1811         /* second phase scan */
1812         err = nand_scan_tail(mtd);
1813         if (err)
1814                 goto escan;
1815
1816         /* Register the partitions */
1817         mtd_device_parse_register(mtd, part_probes,
1818                         NULL,
1819                         host->pdata.parts,
1820                         host->pdata.nr_parts);
1821
1822         platform_set_drvdata(pdev, host);
1823
1824         return 0;
1825
1826 escan:
1827         if (host->clk_act)
1828                 clk_disable_unprepare(host->clk);
1829
1830         return err;
1831 }
1832
1833 static int mxcnd_remove(struct platform_device *pdev)
1834 {
1835         struct mxc_nand_host *host = platform_get_drvdata(pdev);
1836
1837         nand_release(&host->nand);
1838         if (host->clk_act)
1839                 clk_disable_unprepare(host->clk);
1840
1841         return 0;
1842 }
1843
1844 static struct platform_driver mxcnd_driver = {
1845         .driver = {
1846                    .name = DRIVER_NAME,
1847                    .of_match_table = of_match_ptr(mxcnd_dt_ids),
1848         },
1849         .id_table = mxcnd_devtype,
1850         .probe = mxcnd_probe,
1851         .remove = mxcnd_remove,
1852 };
1853 module_platform_driver(mxcnd_driver);
1854
1855 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1856 MODULE_DESCRIPTION("MXC NAND MTD driver");
1857 MODULE_LICENSE("GPL");