2 * MTK NAND Flash controller driver.
3 * Copyright (C) 2016 MediaTek Inc.
4 * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
5 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21 #include <linux/clk.h>
22 #include <linux/mtd/nand.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/module.h>
25 #include <linux/iopoll.h>
29 /* NAND controller register definition */
30 #define NFI_CNFG (0x00)
31 #define CNFG_AHB BIT(0)
32 #define CNFG_READ_EN BIT(1)
33 #define CNFG_DMA_BURST_EN BIT(2)
34 #define CNFG_BYTE_RW BIT(6)
35 #define CNFG_HW_ECC_EN BIT(8)
36 #define CNFG_AUTO_FMT_EN BIT(9)
37 #define CNFG_OP_CUST (6 << 12)
38 #define NFI_PAGEFMT (0x04)
39 #define PAGEFMT_FDM_ECC_SHIFT (12)
40 #define PAGEFMT_FDM_SHIFT (8)
41 #define PAGEFMT_SPARE_16 (0)
42 #define PAGEFMT_SPARE_26 (1)
43 #define PAGEFMT_SPARE_27 (2)
44 #define PAGEFMT_SPARE_28 (3)
45 #define PAGEFMT_SPARE_32 (4)
46 #define PAGEFMT_SPARE_36 (5)
47 #define PAGEFMT_SPARE_40 (6)
48 #define PAGEFMT_SPARE_44 (7)
49 #define PAGEFMT_SPARE_48 (8)
50 #define PAGEFMT_SPARE_49 (9)
51 #define PAGEFMT_SPARE_50 (0xa)
52 #define PAGEFMT_SPARE_51 (0xb)
53 #define PAGEFMT_SPARE_52 (0xc)
54 #define PAGEFMT_SPARE_62 (0xd)
55 #define PAGEFMT_SPARE_63 (0xe)
56 #define PAGEFMT_SPARE_64 (0xf)
57 #define PAGEFMT_SPARE_SHIFT (4)
58 #define PAGEFMT_SEC_SEL_512 BIT(2)
59 #define PAGEFMT_512_2K (0)
60 #define PAGEFMT_2K_4K (1)
61 #define PAGEFMT_4K_8K (2)
62 #define PAGEFMT_8K_16K (3)
64 #define NFI_CON (0x08)
65 #define CON_FIFO_FLUSH BIT(0)
66 #define CON_NFI_RST BIT(1)
67 #define CON_BRD BIT(8) /* burst read */
68 #define CON_BWR BIT(9) /* burst write */
69 #define CON_SEC_SHIFT (12)
70 /* Timming control register */
71 #define NFI_ACCCON (0x0C)
72 #define NFI_INTR_EN (0x10)
73 #define INTR_AHB_DONE_EN BIT(6)
74 #define NFI_INTR_STA (0x14)
75 #define NFI_CMD (0x20)
76 #define NFI_ADDRNOB (0x30)
77 #define NFI_COLADDR (0x34)
78 #define NFI_ROWADDR (0x38)
79 #define NFI_STRDATA (0x40)
82 #define NFI_CNRNB (0x44)
83 #define NFI_DATAW (0x50)
84 #define NFI_DATAR (0x54)
85 #define NFI_PIO_DIRDY (0x58)
86 #define PIO_DI_RDY (0x01)
87 #define NFI_STA (0x60)
88 #define STA_CMD BIT(0)
89 #define STA_ADDR BIT(1)
90 #define STA_BUSY BIT(8)
91 #define STA_EMP_PAGE BIT(12)
92 #define NFI_FSM_CUSTDATA (0xe << 16)
93 #define NFI_FSM_MASK (0xf << 16)
94 #define NFI_ADDRCNTR (0x70)
95 #define CNTR_MASK GENMASK(16, 12)
96 #define ADDRCNTR_SEC_SHIFT (12)
97 #define ADDRCNTR_SEC(val) \
98 (((val) & CNTR_MASK) >> ADDRCNTR_SEC_SHIFT)
99 #define NFI_STRADDR (0x80)
100 #define NFI_BYTELEN (0x84)
101 #define NFI_CSEL (0x90)
102 #define NFI_FDML(x) (0xA0 + (x) * sizeof(u32) * 2)
103 #define NFI_FDMM(x) (0xA4 + (x) * sizeof(u32) * 2)
104 #define NFI_FDM_MAX_SIZE (8)
105 #define NFI_FDM_MIN_SIZE (1)
106 #define NFI_MASTER_STA (0x224)
107 #define MASTER_STA_MASK (0x0FFF)
108 #define NFI_EMPTY_THRESH (0x23C)
110 #define MTK_NAME "mtk-nand"
111 #define KB(x) ((x) * 1024UL)
112 #define MB(x) (KB(x) * 1024UL)
114 #define MTK_TIMEOUT (500000)
115 #define MTK_RESET_TIMEOUT (1000000)
116 #define MTK_MAX_SECTOR (16)
117 #define MTK_NAND_MAX_NSELS (2)
119 struct mtk_nfc_bad_mark_ctl {
120 void (*bm_swap)(struct mtd_info *, u8 *buf, int raw);
126 * FDM: region used to store free OOB data
133 struct mtk_nfc_nand_chip {
134 struct list_head node;
135 struct nand_chip nand;
137 struct mtk_nfc_bad_mark_ctl bad_mark;
138 struct mtk_nfc_fdm fdm;
139 u32 spare_per_sector;
143 /* nothing after this field */
152 struct nand_hw_control controller;
153 struct mtk_ecc_config ecc_cfg;
154 struct mtk_nfc_clk clk;
160 struct completion done;
161 struct list_head chips;
166 static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand)
168 return container_of(nand, struct mtk_nfc_nand_chip, nand);
171 static inline u8 *data_ptr(struct nand_chip *chip, const u8 *p, int i)
173 return (u8 *)p + i * chip->ecc.size;
176 static inline u8 *oob_ptr(struct nand_chip *chip, int i)
178 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
181 /* map the sector's FDM data to free oob:
182 * the beginning of the oob area stores the FDM data of bad mark sectors
185 if (i < mtk_nand->bad_mark.sec)
186 poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size;
187 else if (i == mtk_nand->bad_mark.sec)
190 poi = chip->oob_poi + i * mtk_nand->fdm.reg_size;
195 static inline int mtk_data_len(struct nand_chip *chip)
197 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
199 return chip->ecc.size + mtk_nand->spare_per_sector;
202 static inline u8 *mtk_data_ptr(struct nand_chip *chip, int i)
204 struct mtk_nfc *nfc = nand_get_controller_data(chip);
206 return nfc->buffer + i * mtk_data_len(chip);
209 static inline u8 *mtk_oob_ptr(struct nand_chip *chip, int i)
211 struct mtk_nfc *nfc = nand_get_controller_data(chip);
213 return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size;
216 static inline void nfi_writel(struct mtk_nfc *nfc, u32 val, u32 reg)
218 writel(val, nfc->regs + reg);
221 static inline void nfi_writew(struct mtk_nfc *nfc, u16 val, u32 reg)
223 writew(val, nfc->regs + reg);
226 static inline void nfi_writeb(struct mtk_nfc *nfc, u8 val, u32 reg)
228 writeb(val, nfc->regs + reg);
231 static inline u32 nfi_readl(struct mtk_nfc *nfc, u32 reg)
233 return readl_relaxed(nfc->regs + reg);
236 static inline u16 nfi_readw(struct mtk_nfc *nfc, u32 reg)
238 return readw_relaxed(nfc->regs + reg);
241 static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg)
243 return readb_relaxed(nfc->regs + reg);
246 static void mtk_nfc_hw_reset(struct mtk_nfc *nfc)
248 struct device *dev = nfc->dev;
252 /* reset all registers and force the NFI master to terminate */
253 nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
255 /* wait for the master to finish the last transaction */
256 ret = readl_poll_timeout(nfc->regs + NFI_MASTER_STA, val,
257 !(val & MASTER_STA_MASK), 50,
260 dev_warn(dev, "master active in reset [0x%x] = 0x%x\n",
261 NFI_MASTER_STA, val);
263 /* ensure any status register affected by the NFI master is reset */
264 nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
265 nfi_writew(nfc, STAR_DE, NFI_STRDATA);
268 static int mtk_nfc_send_command(struct mtk_nfc *nfc, u8 command)
270 struct device *dev = nfc->dev;
274 nfi_writel(nfc, command, NFI_CMD);
276 ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val,
277 !(val & STA_CMD), 10, MTK_TIMEOUT);
279 dev_warn(dev, "nfi core timed out entering command mode\n");
286 static int mtk_nfc_send_address(struct mtk_nfc *nfc, int addr)
288 struct device *dev = nfc->dev;
292 nfi_writel(nfc, addr, NFI_COLADDR);
293 nfi_writel(nfc, 0, NFI_ROWADDR);
294 nfi_writew(nfc, 1, NFI_ADDRNOB);
296 ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val,
297 !(val & STA_ADDR), 10, MTK_TIMEOUT);
299 dev_warn(dev, "nfi core timed out entering address mode\n");
306 static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd)
308 struct nand_chip *chip = mtd_to_nand(mtd);
309 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
310 struct mtk_nfc *nfc = nand_get_controller_data(chip);
316 spare = mtk_nand->spare_per_sector;
318 switch (mtd->writesize) {
320 fmt = PAGEFMT_512_2K | PAGEFMT_SEC_SEL_512;
323 if (chip->ecc.size == 512)
324 fmt = PAGEFMT_2K_4K | PAGEFMT_SEC_SEL_512;
326 fmt = PAGEFMT_512_2K;
329 if (chip->ecc.size == 512)
330 fmt = PAGEFMT_4K_8K | PAGEFMT_SEC_SEL_512;
335 if (chip->ecc.size == 512)
336 fmt = PAGEFMT_8K_16K | PAGEFMT_SEC_SEL_512;
341 fmt = PAGEFMT_8K_16K;
344 dev_err(nfc->dev, "invalid page len: %d\n", mtd->writesize);
349 * the hardware will double the value for this eccsize, so we need to
352 if (chip->ecc.size == 1024)
357 fmt |= (PAGEFMT_SPARE_16 << PAGEFMT_SPARE_SHIFT);
360 fmt |= (PAGEFMT_SPARE_26 << PAGEFMT_SPARE_SHIFT);
363 fmt |= (PAGEFMT_SPARE_27 << PAGEFMT_SPARE_SHIFT);
366 fmt |= (PAGEFMT_SPARE_28 << PAGEFMT_SPARE_SHIFT);
369 fmt |= (PAGEFMT_SPARE_32 << PAGEFMT_SPARE_SHIFT);
372 fmt |= (PAGEFMT_SPARE_36 << PAGEFMT_SPARE_SHIFT);
375 fmt |= (PAGEFMT_SPARE_40 << PAGEFMT_SPARE_SHIFT);
378 fmt |= (PAGEFMT_SPARE_44 << PAGEFMT_SPARE_SHIFT);
381 fmt |= (PAGEFMT_SPARE_48 << PAGEFMT_SPARE_SHIFT);
384 fmt |= (PAGEFMT_SPARE_49 << PAGEFMT_SPARE_SHIFT);
387 fmt |= (PAGEFMT_SPARE_50 << PAGEFMT_SPARE_SHIFT);
390 fmt |= (PAGEFMT_SPARE_51 << PAGEFMT_SPARE_SHIFT);
393 fmt |= (PAGEFMT_SPARE_52 << PAGEFMT_SPARE_SHIFT);
396 fmt |= (PAGEFMT_SPARE_62 << PAGEFMT_SPARE_SHIFT);
399 fmt |= (PAGEFMT_SPARE_63 << PAGEFMT_SPARE_SHIFT);
402 fmt |= (PAGEFMT_SPARE_64 << PAGEFMT_SPARE_SHIFT);
405 dev_err(nfc->dev, "invalid spare per sector %d\n", spare);
409 fmt |= mtk_nand->fdm.reg_size << PAGEFMT_FDM_SHIFT;
410 fmt |= mtk_nand->fdm.ecc_size << PAGEFMT_FDM_ECC_SHIFT;
411 nfi_writew(nfc, fmt, NFI_PAGEFMT);
413 nfc->ecc_cfg.strength = chip->ecc.strength;
414 nfc->ecc_cfg.len = chip->ecc.size + mtk_nand->fdm.ecc_size;
419 static void mtk_nfc_select_chip(struct mtd_info *mtd, int chip)
421 struct nand_chip *nand = mtd_to_nand(mtd);
422 struct mtk_nfc *nfc = nand_get_controller_data(nand);
423 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(nand);
428 mtk_nfc_hw_runtime_config(mtd);
430 nfi_writel(nfc, mtk_nand->sels[chip], NFI_CSEL);
433 static int mtk_nfc_dev_ready(struct mtd_info *mtd)
435 struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
437 if (nfi_readl(nfc, NFI_STA) & STA_BUSY)
443 static void mtk_nfc_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
445 struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
447 if (ctrl & NAND_ALE) {
448 mtk_nfc_send_address(nfc, dat);
449 } else if (ctrl & NAND_CLE) {
450 mtk_nfc_hw_reset(nfc);
452 nfi_writew(nfc, CNFG_OP_CUST, NFI_CNFG);
453 mtk_nfc_send_command(nfc, dat);
457 static inline void mtk_nfc_wait_ioready(struct mtk_nfc *nfc)
462 rc = readb_poll_timeout_atomic(nfc->regs + NFI_PIO_DIRDY, val,
463 val & PIO_DI_RDY, 10, MTK_TIMEOUT);
465 dev_err(nfc->dev, "data not ready\n");
468 static inline u8 mtk_nfc_read_byte(struct mtd_info *mtd)
470 struct nand_chip *chip = mtd_to_nand(mtd);
471 struct mtk_nfc *nfc = nand_get_controller_data(chip);
474 /* after each byte read, the NFI_STA reg is reset by the hardware */
475 reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
476 if (reg != NFI_FSM_CUSTDATA) {
477 reg = nfi_readw(nfc, NFI_CNFG);
478 reg |= CNFG_BYTE_RW | CNFG_READ_EN;
479 nfi_writew(nfc, reg, NFI_CNFG);
482 * set to max sector to allow the HW to continue reading over
485 reg = (MTK_MAX_SECTOR << CON_SEC_SHIFT) | CON_BRD;
486 nfi_writel(nfc, reg, NFI_CON);
488 /* trigger to fetch data */
489 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
492 mtk_nfc_wait_ioready(nfc);
494 return nfi_readb(nfc, NFI_DATAR);
497 static void mtk_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
501 for (i = 0; i < len; i++)
502 buf[i] = mtk_nfc_read_byte(mtd);
505 static void mtk_nfc_write_byte(struct mtd_info *mtd, u8 byte)
507 struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
510 reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
512 if (reg != NFI_FSM_CUSTDATA) {
513 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW;
514 nfi_writew(nfc, reg, NFI_CNFG);
516 reg = MTK_MAX_SECTOR << CON_SEC_SHIFT | CON_BWR;
517 nfi_writel(nfc, reg, NFI_CON);
519 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
522 mtk_nfc_wait_ioready(nfc);
523 nfi_writeb(nfc, byte, NFI_DATAW);
526 static void mtk_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
530 for (i = 0; i < len; i++)
531 mtk_nfc_write_byte(mtd, buf[i]);
534 static int mtk_nfc_sector_encode(struct nand_chip *chip, u8 *data)
536 struct mtk_nfc *nfc = nand_get_controller_data(chip);
537 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
538 int size = chip->ecc.size + mtk_nand->fdm.reg_size;
540 nfc->ecc_cfg.mode = ECC_DMA_MODE;
541 nfc->ecc_cfg.op = ECC_ENCODE;
543 return mtk_ecc_encode(nfc->ecc, &nfc->ecc_cfg, data, size);
546 static void mtk_nfc_no_bad_mark_swap(struct mtd_info *a, u8 *b, int c)
551 static void mtk_nfc_bad_mark_swap(struct mtd_info *mtd, u8 *buf, int raw)
553 struct nand_chip *chip = mtd_to_nand(mtd);
554 struct mtk_nfc_nand_chip *nand = to_mtk_nand(chip);
555 u32 bad_pos = nand->bad_mark.pos;
558 bad_pos += nand->bad_mark.sec * mtk_data_len(chip);
560 bad_pos += nand->bad_mark.sec * chip->ecc.size;
562 swap(chip->oob_poi[0], buf[bad_pos]);
565 static int mtk_nfc_format_subpage(struct mtd_info *mtd, u32 offset,
566 u32 len, const u8 *buf)
568 struct nand_chip *chip = mtd_to_nand(mtd);
569 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
570 struct mtk_nfc *nfc = nand_get_controller_data(chip);
571 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
575 start = offset / chip->ecc.size;
576 end = DIV_ROUND_UP(offset + len, chip->ecc.size);
578 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
579 for (i = 0; i < chip->ecc.steps; i++) {
580 memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i),
583 if (start > i || i >= end)
586 if (i == mtk_nand->bad_mark.sec)
587 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
589 memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size);
591 /* program the CRC back to the OOB */
592 ret = mtk_nfc_sector_encode(chip, mtk_data_ptr(chip, i));
600 static void mtk_nfc_format_page(struct mtd_info *mtd, const u8 *buf)
602 struct nand_chip *chip = mtd_to_nand(mtd);
603 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
604 struct mtk_nfc *nfc = nand_get_controller_data(chip);
605 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
608 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
609 for (i = 0; i < chip->ecc.steps; i++) {
611 memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i),
614 if (i == mtk_nand->bad_mark.sec)
615 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
617 memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size);
621 static inline void mtk_nfc_read_fdm(struct nand_chip *chip, u32 start,
624 struct mtk_nfc *nfc = nand_get_controller_data(chip);
625 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
626 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
631 for (i = 0; i < sectors; i++) {
632 oobptr = oob_ptr(chip, start + i);
633 vall = nfi_readl(nfc, NFI_FDML(i));
634 valm = nfi_readl(nfc, NFI_FDMM(i));
636 for (j = 0; j < fdm->reg_size; j++)
637 oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8);
641 static inline void mtk_nfc_write_fdm(struct nand_chip *chip)
643 struct mtk_nfc *nfc = nand_get_controller_data(chip);
644 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
645 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
650 for (i = 0; i < chip->ecc.steps; i++) {
651 oobptr = oob_ptr(chip, i);
654 for (j = 0; j < 8; j++) {
656 vall |= (j < fdm->reg_size ? oobptr[j] : 0xff)
659 valm |= (j < fdm->reg_size ? oobptr[j] : 0xff)
662 nfi_writel(nfc, vall, NFI_FDML(i));
663 nfi_writel(nfc, valm, NFI_FDMM(i));
667 static int mtk_nfc_do_write_page(struct mtd_info *mtd, struct nand_chip *chip,
668 const u8 *buf, int page, int len)
670 struct mtk_nfc *nfc = nand_get_controller_data(chip);
671 struct device *dev = nfc->dev;
676 addr = dma_map_single(dev, (void *)buf, len, DMA_TO_DEVICE);
677 ret = dma_mapping_error(nfc->dev, addr);
679 dev_err(nfc->dev, "dma mapping error\n");
683 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AHB | CNFG_DMA_BURST_EN;
684 nfi_writew(nfc, reg, NFI_CNFG);
686 nfi_writel(nfc, chip->ecc.steps << CON_SEC_SHIFT, NFI_CON);
687 nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR);
688 nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
690 init_completion(&nfc->done);
692 reg = nfi_readl(nfc, NFI_CON) | CON_BWR;
693 nfi_writel(nfc, reg, NFI_CON);
694 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
696 ret = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500));
698 dev_err(dev, "program ahb done timeout\n");
699 nfi_writew(nfc, 0, NFI_INTR_EN);
704 ret = readl_poll_timeout_atomic(nfc->regs + NFI_ADDRCNTR, reg,
705 ADDRCNTR_SEC(reg) >= chip->ecc.steps,
708 dev_err(dev, "hwecc write timeout\n");
712 dma_unmap_single(nfc->dev, addr, len, DMA_TO_DEVICE);
713 nfi_writel(nfc, 0, NFI_CON);
718 static int mtk_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
719 const u8 *buf, int page, int raw)
721 struct mtk_nfc *nfc = nand_get_controller_data(chip);
722 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
729 /* OOB => FDM: from register, ECC: from HW */
730 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AUTO_FMT_EN;
731 nfi_writew(nfc, reg | CNFG_HW_ECC_EN, NFI_CNFG);
733 nfc->ecc_cfg.op = ECC_ENCODE;
734 nfc->ecc_cfg.mode = ECC_NFI_MODE;
735 ret = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg);
737 /* clear NFI config */
738 reg = nfi_readw(nfc, NFI_CNFG);
739 reg &= ~(CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
740 nfi_writew(nfc, reg, NFI_CNFG);
745 memcpy(nfc->buffer, buf, mtd->writesize);
746 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, raw);
747 bufpoi = nfc->buffer;
749 /* write OOB into the FDM registers (OOB area in MTK NAND) */
750 mtk_nfc_write_fdm(chip);
755 len = mtd->writesize + (raw ? mtd->oobsize : 0);
756 ret = mtk_nfc_do_write_page(mtd, chip, bufpoi, page, len);
759 mtk_ecc_disable(nfc->ecc);
764 static int mtk_nfc_write_page_hwecc(struct mtd_info *mtd,
765 struct nand_chip *chip, const u8 *buf,
766 int oob_on, int page)
768 return mtk_nfc_write_page(mtd, chip, buf, page, 0);
771 static int mtk_nfc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
772 const u8 *buf, int oob_on, int pg)
774 struct mtk_nfc *nfc = nand_get_controller_data(chip);
776 mtk_nfc_format_page(mtd, buf);
777 return mtk_nfc_write_page(mtd, chip, nfc->buffer, pg, 1);
780 static int mtk_nfc_write_subpage_hwecc(struct mtd_info *mtd,
781 struct nand_chip *chip, u32 offset,
782 u32 data_len, const u8 *buf,
783 int oob_on, int page)
785 struct mtk_nfc *nfc = nand_get_controller_data(chip);
788 ret = mtk_nfc_format_subpage(mtd, offset, data_len, buf);
792 /* use the data in the private buffer (now with FDM and CRC) */
793 return mtk_nfc_write_page(mtd, chip, nfc->buffer, page, 1);
796 static int mtk_nfc_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
801 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
803 ret = mtk_nfc_write_page_raw(mtd, chip, NULL, 1, page);
807 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
808 ret = chip->waitfunc(mtd, chip);
810 return ret & NAND_STATUS_FAIL ? -EIO : 0;
813 static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 start,
816 struct nand_chip *chip = mtd_to_nand(mtd);
817 struct mtk_nfc *nfc = nand_get_controller_data(chip);
818 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
819 struct mtk_ecc_stats stats;
820 u32 reg_size = mtk_nand->fdm.reg_size;
823 rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE;
825 memset(buf, 0xff, sectors * chip->ecc.size);
826 for (i = 0; i < sectors; i++)
827 memset(oob_ptr(chip, start + i), 0xff, reg_size);
831 mtk_ecc_get_stats(nfc->ecc, &stats, sectors);
832 mtd->ecc_stats.corrected += stats.corrected;
833 mtd->ecc_stats.failed += stats.failed;
835 return stats.bitflips;
838 static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
839 u32 data_offs, u32 readlen,
840 u8 *bufpoi, int page, int raw)
842 struct mtk_nfc *nfc = nand_get_controller_data(chip);
843 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
844 u32 spare = mtk_nand->spare_per_sector;
845 u32 column, sectors, start, end, reg;
852 start = data_offs / chip->ecc.size;
853 end = DIV_ROUND_UP(data_offs + readlen, chip->ecc.size);
855 sectors = end - start;
856 column = start * (chip->ecc.size + spare);
858 len = sectors * chip->ecc.size + (raw ? sectors * spare : 0);
859 buf = bufpoi + start * chip->ecc.size;
862 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, column, -1);
864 addr = dma_map_single(nfc->dev, buf, len, DMA_FROM_DEVICE);
865 rc = dma_mapping_error(nfc->dev, addr);
867 dev_err(nfc->dev, "dma mapping error\n");
872 reg = nfi_readw(nfc, NFI_CNFG);
873 reg |= CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_AHB;
875 reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN;
876 nfi_writew(nfc, reg, NFI_CNFG);
878 nfc->ecc_cfg.mode = ECC_NFI_MODE;
879 nfc->ecc_cfg.sectors = sectors;
880 nfc->ecc_cfg.op = ECC_DECODE;
881 rc = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg);
883 dev_err(nfc->dev, "ecc enable\n");
885 reg &= ~(CNFG_DMA_BURST_EN | CNFG_AHB | CNFG_READ_EN |
886 CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
887 nfi_writew(nfc, reg, NFI_CNFG);
888 dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
893 nfi_writew(nfc, reg, NFI_CNFG);
896 nfi_writel(nfc, sectors << CON_SEC_SHIFT, NFI_CON);
897 nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
898 nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR);
900 init_completion(&nfc->done);
901 reg = nfi_readl(nfc, NFI_CON) | CON_BRD;
902 nfi_writel(nfc, reg, NFI_CON);
903 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
905 rc = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500));
907 dev_warn(nfc->dev, "read ahb/dma done timeout\n");
909 rc = readl_poll_timeout_atomic(nfc->regs + NFI_BYTELEN, reg,
910 ADDRCNTR_SEC(reg) >= sectors, 10,
913 dev_err(nfc->dev, "subpage done timeout\n");
916 rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE);
917 bitflips = rc < 0 ? -ETIMEDOUT :
918 mtk_nfc_update_ecc_stats(mtd, buf, start, sectors);
919 mtk_nfc_read_fdm(chip, start, sectors);
922 dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
927 mtk_ecc_disable(nfc->ecc);
929 if (clamp(mtk_nand->bad_mark.sec, start, end) == mtk_nand->bad_mark.sec)
930 mtk_nand->bad_mark.bm_swap(mtd, bufpoi, raw);
932 nfi_writel(nfc, 0, NFI_CON);
937 static int mtk_nfc_read_subpage_hwecc(struct mtd_info *mtd,
938 struct nand_chip *chip, u32 off,
939 u32 len, u8 *p, int pg)
941 return mtk_nfc_read_subpage(mtd, chip, off, len, p, pg, 0);
944 static int mtk_nfc_read_page_hwecc(struct mtd_info *mtd,
945 struct nand_chip *chip, u8 *p,
948 return mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, p, pg, 0);
951 static int mtk_nfc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
952 u8 *buf, int oob_on, int page)
954 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
955 struct mtk_nfc *nfc = nand_get_controller_data(chip);
956 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
959 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
960 ret = mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, nfc->buffer,
965 for (i = 0; i < chip->ecc.steps; i++) {
966 memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size);
968 if (i == mtk_nand->bad_mark.sec)
969 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
972 memcpy(data_ptr(chip, buf, i), mtk_data_ptr(chip, i),
979 static int mtk_nfc_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
982 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
984 return mtk_nfc_read_page_raw(mtd, chip, NULL, 1, page);
987 static inline void mtk_nfc_hw_init(struct mtk_nfc *nfc)
990 * ACCON: access timing control register
991 * -------------------------------------
992 * 31:28: minimum required time for CS post pulling down after accessing
994 * 27:22: minimum required time for CS pre pulling down before accessing
996 * 21:16: minimum required time from NCEB low to NREB low
997 * 15:12: minimum required time from NWEB high to NREB low.
998 * 11:08: write enable hold time
999 * 07:04: write wait states
1000 * 03:00: read wait states
1002 nfi_writel(nfc, 0x10804211, NFI_ACCCON);
1005 * CNRNB: nand ready/busy register
1006 * -------------------------------
1007 * 7:4: timeout register for polling the NAND busy/ready signal
1008 * 0 : poll the status of the busy/ready signal after [7:4]*16 cycles.
1010 nfi_writew(nfc, 0xf1, NFI_CNRNB);
1011 nfi_writew(nfc, PAGEFMT_8K_16K, NFI_PAGEFMT);
1013 mtk_nfc_hw_reset(nfc);
1015 nfi_readl(nfc, NFI_INTR_STA);
1016 nfi_writel(nfc, 0, NFI_INTR_EN);
1019 static irqreturn_t mtk_nfc_irq(int irq, void *id)
1021 struct mtk_nfc *nfc = id;
1024 sta = nfi_readw(nfc, NFI_INTR_STA);
1025 ien = nfi_readw(nfc, NFI_INTR_EN);
1030 nfi_writew(nfc, ~sta & ien, NFI_INTR_EN);
1031 complete(&nfc->done);
1036 static int mtk_nfc_enable_clk(struct device *dev, struct mtk_nfc_clk *clk)
1040 ret = clk_prepare_enable(clk->nfi_clk);
1042 dev_err(dev, "failed to enable nfi clk\n");
1046 ret = clk_prepare_enable(clk->pad_clk);
1048 dev_err(dev, "failed to enable pad clk\n");
1049 clk_disable_unprepare(clk->nfi_clk);
1056 static void mtk_nfc_disable_clk(struct mtk_nfc_clk *clk)
1058 clk_disable_unprepare(clk->nfi_clk);
1059 clk_disable_unprepare(clk->pad_clk);
1062 static int mtk_nfc_ooblayout_free(struct mtd_info *mtd, int section,
1063 struct mtd_oob_region *oob_region)
1065 struct nand_chip *chip = mtd_to_nand(mtd);
1066 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1067 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
1070 eccsteps = mtd->writesize / chip->ecc.size;
1072 if (section >= eccsteps)
1075 oob_region->length = fdm->reg_size - fdm->ecc_size;
1076 oob_region->offset = section * fdm->reg_size + fdm->ecc_size;
1081 static int mtk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
1082 struct mtd_oob_region *oob_region)
1084 struct nand_chip *chip = mtd_to_nand(mtd);
1085 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1091 eccsteps = mtd->writesize / chip->ecc.size;
1092 oob_region->offset = mtk_nand->fdm.reg_size * eccsteps;
1093 oob_region->length = mtd->oobsize - oob_region->offset;
1098 static const struct mtd_ooblayout_ops mtk_nfc_ooblayout_ops = {
1099 .free = mtk_nfc_ooblayout_free,
1100 .ecc = mtk_nfc_ooblayout_ecc,
1103 static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd)
1105 struct nand_chip *nand = mtd_to_nand(mtd);
1106 struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand);
1109 ecc_bytes = DIV_ROUND_UP(nand->ecc.strength * ECC_PARITY_BITS, 8);
1111 fdm->reg_size = chip->spare_per_sector - ecc_bytes;
1112 if (fdm->reg_size > NFI_FDM_MAX_SIZE)
1113 fdm->reg_size = NFI_FDM_MAX_SIZE;
1115 /* bad block mark storage */
1119 static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl,
1120 struct mtd_info *mtd)
1122 struct nand_chip *nand = mtd_to_nand(mtd);
1124 if (mtd->writesize == 512) {
1125 bm_ctl->bm_swap = mtk_nfc_no_bad_mark_swap;
1127 bm_ctl->bm_swap = mtk_nfc_bad_mark_swap;
1128 bm_ctl->sec = mtd->writesize / mtk_data_len(nand);
1129 bm_ctl->pos = mtd->writesize % mtk_data_len(nand);
1133 static void mtk_nfc_set_spare_per_sector(u32 *sps, struct mtd_info *mtd)
1135 struct nand_chip *nand = mtd_to_nand(mtd);
1136 u32 spare[] = {16, 26, 27, 28, 32, 36, 40, 44,
1137 48, 49, 50, 51, 52, 62, 63, 64};
1140 eccsteps = mtd->writesize / nand->ecc.size;
1141 *sps = mtd->oobsize / eccsteps;
1143 if (nand->ecc.size == 1024)
1146 for (i = 0; i < ARRAY_SIZE(spare); i++) {
1147 if (*sps <= spare[i]) {
1150 else if (*sps != spare[i])
1151 *sps = spare[i - 1];
1156 if (i >= ARRAY_SIZE(spare))
1157 *sps = spare[ARRAY_SIZE(spare) - 1];
1159 if (nand->ecc.size == 1024)
1163 static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
1165 struct nand_chip *nand = mtd_to_nand(mtd);
1169 /* support only ecc hw mode */
1170 if (nand->ecc.mode != NAND_ECC_HW) {
1171 dev_err(dev, "ecc.mode not supported\n");
1175 /* if optional dt settings not present */
1176 if (!nand->ecc.size || !nand->ecc.strength) {
1177 /* use datasheet requirements */
1178 nand->ecc.strength = nand->ecc_strength_ds;
1179 nand->ecc.size = nand->ecc_step_ds;
1182 * align eccstrength and eccsize
1183 * this controller only supports 512 and 1024 sizes
1185 if (nand->ecc.size < 1024) {
1186 if (mtd->writesize > 512) {
1187 nand->ecc.size = 1024;
1188 nand->ecc.strength <<= 1;
1190 nand->ecc.size = 512;
1193 nand->ecc.size = 1024;
1196 mtk_nfc_set_spare_per_sector(&spare, mtd);
1198 /* calculate oob bytes except ecc parity data */
1199 free = ((nand->ecc.strength * ECC_PARITY_BITS) + 7) >> 3;
1200 free = spare - free;
1203 * enhance ecc strength if oob left is bigger than max FDM size
1204 * or reduce ecc strength if oob size is not enough for ecc
1207 if (free > NFI_FDM_MAX_SIZE) {
1208 spare -= NFI_FDM_MAX_SIZE;
1209 nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS;
1210 } else if (free < 0) {
1211 spare -= NFI_FDM_MIN_SIZE;
1212 nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS;
1216 mtk_ecc_adjust_strength(&nand->ecc.strength);
1218 dev_info(dev, "eccsize %d eccstrength %d\n",
1219 nand->ecc.size, nand->ecc.strength);
1224 static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc,
1225 struct device_node *np)
1227 struct mtk_nfc_nand_chip *chip;
1228 struct nand_chip *nand;
1229 struct mtd_info *mtd;
1235 if (!of_get_property(np, "reg", &nsels))
1238 nsels /= sizeof(u32);
1239 if (!nsels || nsels > MTK_NAND_MAX_NSELS) {
1240 dev_err(dev, "invalid reg property size %d\n", nsels);
1244 chip = devm_kzalloc(dev, sizeof(*chip) + nsels * sizeof(u8),
1249 chip->nsels = nsels;
1250 for (i = 0; i < nsels; i++) {
1251 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1253 dev_err(dev, "reg property failure : %d\n", ret);
1256 chip->sels[i] = tmp;
1260 nand->controller = &nfc->controller;
1262 nand_set_flash_node(nand, np);
1263 nand_set_controller_data(nand, nfc);
1265 nand->options |= NAND_USE_BOUNCE_BUFFER | NAND_SUBPAGE_READ;
1266 nand->dev_ready = mtk_nfc_dev_ready;
1267 nand->select_chip = mtk_nfc_select_chip;
1268 nand->write_byte = mtk_nfc_write_byte;
1269 nand->write_buf = mtk_nfc_write_buf;
1270 nand->read_byte = mtk_nfc_read_byte;
1271 nand->read_buf = mtk_nfc_read_buf;
1272 nand->cmd_ctrl = mtk_nfc_cmd_ctrl;
1274 /* set default mode in case dt entry is missing */
1275 nand->ecc.mode = NAND_ECC_HW;
1277 nand->ecc.write_subpage = mtk_nfc_write_subpage_hwecc;
1278 nand->ecc.write_page_raw = mtk_nfc_write_page_raw;
1279 nand->ecc.write_page = mtk_nfc_write_page_hwecc;
1280 nand->ecc.write_oob_raw = mtk_nfc_write_oob_std;
1281 nand->ecc.write_oob = mtk_nfc_write_oob_std;
1283 nand->ecc.read_subpage = mtk_nfc_read_subpage_hwecc;
1284 nand->ecc.read_page_raw = mtk_nfc_read_page_raw;
1285 nand->ecc.read_page = mtk_nfc_read_page_hwecc;
1286 nand->ecc.read_oob_raw = mtk_nfc_read_oob_std;
1287 nand->ecc.read_oob = mtk_nfc_read_oob_std;
1289 mtd = nand_to_mtd(nand);
1290 mtd->owner = THIS_MODULE;
1291 mtd->dev.parent = dev;
1292 mtd->name = MTK_NAME;
1293 mtd_set_ooblayout(mtd, &mtk_nfc_ooblayout_ops);
1295 mtk_nfc_hw_init(nfc);
1297 ret = nand_scan_ident(mtd, nsels, NULL);
1301 /* store bbt magic in page, cause OOB is not protected */
1302 if (nand->bbt_options & NAND_BBT_USE_FLASH)
1303 nand->bbt_options |= NAND_BBT_NO_OOB;
1305 ret = mtk_nfc_ecc_init(dev, mtd);
1309 if (nand->options & NAND_BUSWIDTH_16) {
1310 dev_err(dev, "16bits buswidth not supported");
1314 mtk_nfc_set_spare_per_sector(&chip->spare_per_sector, mtd);
1315 mtk_nfc_set_fdm(&chip->fdm, mtd);
1316 mtk_nfc_set_bad_mark_ctl(&chip->bad_mark, mtd);
1318 len = mtd->writesize + mtd->oobsize;
1319 nfc->buffer = devm_kzalloc(dev, len, GFP_KERNEL);
1323 ret = nand_scan_tail(mtd);
1327 ret = mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
1329 dev_err(dev, "mtd parse partition error\n");
1334 list_add_tail(&chip->node, &nfc->chips);
1339 static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
1341 struct device_node *np = dev->of_node;
1342 struct device_node *nand_np;
1345 for_each_child_of_node(np, nand_np) {
1346 ret = mtk_nfc_nand_chip_init(dev, nfc, nand_np);
1348 of_node_put(nand_np);
1356 static int mtk_nfc_probe(struct platform_device *pdev)
1358 struct device *dev = &pdev->dev;
1359 struct device_node *np = dev->of_node;
1360 struct mtk_nfc *nfc;
1361 struct resource *res;
1364 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1368 spin_lock_init(&nfc->controller.lock);
1369 init_waitqueue_head(&nfc->controller.wq);
1370 INIT_LIST_HEAD(&nfc->chips);
1372 /* probe defer if not ready */
1373 nfc->ecc = of_mtk_ecc_get(np);
1374 if (IS_ERR(nfc->ecc))
1375 return PTR_ERR(nfc->ecc);
1381 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1382 nfc->regs = devm_ioremap_resource(dev, res);
1383 if (IS_ERR(nfc->regs)) {
1384 ret = PTR_ERR(nfc->regs);
1385 dev_err(dev, "no nfi base\n");
1389 nfc->clk.nfi_clk = devm_clk_get(dev, "nfi_clk");
1390 if (IS_ERR(nfc->clk.nfi_clk)) {
1391 dev_err(dev, "no clk\n");
1392 ret = PTR_ERR(nfc->clk.nfi_clk);
1396 nfc->clk.pad_clk = devm_clk_get(dev, "pad_clk");
1397 if (IS_ERR(nfc->clk.pad_clk)) {
1398 dev_err(dev, "no pad clk\n");
1399 ret = PTR_ERR(nfc->clk.pad_clk);
1403 ret = mtk_nfc_enable_clk(dev, &nfc->clk);
1407 irq = platform_get_irq(pdev, 0);
1409 dev_err(dev, "no nfi irq resource\n");
1414 ret = devm_request_irq(dev, irq, mtk_nfc_irq, 0x0, "mtk-nand", nfc);
1416 dev_err(dev, "failed to request nfi irq\n");
1420 ret = dma_set_mask(dev, DMA_BIT_MASK(32));
1422 dev_err(dev, "failed to set dma mask\n");
1426 platform_set_drvdata(pdev, nfc);
1428 ret = mtk_nfc_nand_chips_init(dev, nfc);
1430 dev_err(dev, "failed to init nand chips\n");
1437 mtk_nfc_disable_clk(&nfc->clk);
1440 mtk_ecc_release(nfc->ecc);
1445 static int mtk_nfc_remove(struct platform_device *pdev)
1447 struct mtk_nfc *nfc = platform_get_drvdata(pdev);
1448 struct mtk_nfc_nand_chip *chip;
1450 while (!list_empty(&nfc->chips)) {
1451 chip = list_first_entry(&nfc->chips, struct mtk_nfc_nand_chip,
1453 nand_release(&chip->nand);
1454 list_del(&chip->node);
1457 mtk_ecc_release(nfc->ecc);
1458 mtk_nfc_disable_clk(&nfc->clk);
1463 #ifdef CONFIG_PM_SLEEP
1464 static int mtk_nfc_suspend(struct device *dev)
1466 struct mtk_nfc *nfc = dev_get_drvdata(dev);
1468 mtk_nfc_disable_clk(&nfc->clk);
1473 static int mtk_nfc_resume(struct device *dev)
1475 struct mtk_nfc *nfc = dev_get_drvdata(dev);
1476 struct mtk_nfc_nand_chip *chip;
1477 struct nand_chip *nand;
1478 struct mtd_info *mtd;
1484 ret = mtk_nfc_enable_clk(dev, &nfc->clk);
1488 mtk_nfc_hw_init(nfc);
1490 /* reset NAND chip if VCC was powered off */
1491 list_for_each_entry(chip, &nfc->chips, node) {
1493 mtd = nand_to_mtd(nand);
1494 for (i = 0; i < chip->nsels; i++) {
1495 nand->select_chip(mtd, i);
1496 nand->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1503 static SIMPLE_DEV_PM_OPS(mtk_nfc_pm_ops, mtk_nfc_suspend, mtk_nfc_resume);
1506 static const struct of_device_id mtk_nfc_id_table[] = {
1507 { .compatible = "mediatek,mt2701-nfc" },
1510 MODULE_DEVICE_TABLE(of, mtk_nfc_id_table);
1512 static struct platform_driver mtk_nfc_driver = {
1513 .probe = mtk_nfc_probe,
1514 .remove = mtk_nfc_remove,
1517 .of_match_table = mtk_nfc_id_table,
1518 #ifdef CONFIG_PM_SLEEP
1519 .pm = &mtk_nfc_pm_ops,
1524 module_platform_driver(mtk_nfc_driver);
1526 MODULE_LICENSE("GPL");
1527 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
1528 MODULE_DESCRIPTION("MTK Nand Flash Controller Driver");