2 * MTK ECC controller driver.
3 * Copyright (C) 2016 MediaTek Inc.
4 * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
5 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/interrupt.h>
20 #include <linux/clk.h>
21 #include <linux/module.h>
22 #include <linux/iopoll.h>
24 #include <linux/of_platform.h>
25 #include <linux/mutex.h>
29 #define ECC_IDLE_MASK BIT(0)
30 #define ECC_IRQ_EN BIT(0)
31 #define ECC_PG_IRQ_SEL BIT(1)
32 #define ECC_OP_ENABLE (1)
33 #define ECC_OP_DISABLE (0)
35 #define ECC_ENCCON (0x00)
36 #define ECC_ENCCNFG (0x04)
37 #define ECC_MODE_SHIFT (5)
38 #define ECC_MS_SHIFT (16)
39 #define ECC_ENCDIADDR (0x08)
40 #define ECC_ENCIDLE (0x0C)
41 #define ECC_ENCIRQ_EN (0x80)
42 #define ECC_ENCIRQ_STA (0x84)
43 #define ECC_DECCON (0x100)
44 #define ECC_DECCNFG (0x104)
45 #define DEC_EMPTY_EN BIT(31)
46 #define DEC_CNFG_CORRECT (0x3 << 12)
47 #define ECC_DECIDLE (0x10C)
48 #define ECC_DECENUM0 (0x114)
49 #define ECC_DECDONE (0x124)
50 #define ECC_DECIRQ_EN (0x200)
51 #define ECC_DECIRQ_STA (0x204)
53 #define ECC_TIMEOUT (500000)
55 #define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
56 #define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
57 #define ECC_IRQ_REG(op) ((op) == ECC_ENCODE ? \
58 ECC_ENCIRQ_EN : ECC_DECIRQ_EN)
62 const u8 *ecc_strength;
64 u32 encode_parity_reg0;
70 const struct mtk_ecc_caps *caps;
74 struct completion done;
81 /* ecc strength that each IP supports */
82 static const u8 ecc_strength_mt2701[] = {
83 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
84 40, 44, 48, 52, 56, 60
87 static const u8 ecc_strength_mt2712[] = {
88 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
89 40, 44, 48, 52, 56, 60, 68, 72, 80
92 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
93 enum mtk_ecc_operation op)
95 struct device *dev = ecc->dev;
99 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
103 dev_warn(dev, "%s NOT idle\n",
104 op == ECC_ENCODE ? "encoder" : "decoder");
107 static irqreturn_t mtk_ecc_irq(int irq, void *id)
109 struct mtk_ecc *ecc = id;
110 enum mtk_ecc_operation op;
113 dec = readw(ecc->regs + ECC_DECIRQ_STA) & ECC_IRQ_EN;
116 dec = readw(ecc->regs + ECC_DECDONE);
117 if (dec & ecc->sectors) {
119 * Clear decode IRQ status once again to ensure that
120 * there will be no extra IRQ.
122 readw(ecc->regs + ECC_DECIRQ_STA);
124 complete(&ecc->done);
129 enc = readl(ecc->regs + ECC_ENCIRQ_STA) & ECC_IRQ_EN;
132 complete(&ecc->done);
141 static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
143 u32 ecc_bit, dec_sz, enc_sz;
146 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
147 if (ecc->caps->ecc_strength[i] == config->strength)
151 if (i == ecc->caps->num_ecc_strength) {
152 dev_err(ecc->dev, "invalid ecc strength %d\n",
159 if (config->op == ECC_ENCODE) {
160 /* configure ECC encoder (in bits) */
161 enc_sz = config->len << 3;
163 reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
164 reg |= (enc_sz << ECC_MS_SHIFT);
165 writel(reg, ecc->regs + ECC_ENCCNFG);
167 if (config->mode != ECC_NFI_MODE)
168 writel(lower_32_bits(config->addr),
169 ecc->regs + ECC_ENCDIADDR);
172 /* configure ECC decoder (in bits) */
173 dec_sz = (config->len << 3) +
174 config->strength * ECC_PARITY_BITS;
176 reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
177 reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
179 writel(reg, ecc->regs + ECC_DECCNFG);
182 ecc->sectors = 1 << (config->sectors - 1);
188 void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
194 stats->corrected = 0;
197 for (i = 0; i < sectors; i++) {
198 offset = (i >> 2) << 2;
199 err = readl(ecc->regs + ECC_DECENUM0 + offset);
200 err = err >> ((i % 4) * 8);
201 err &= ecc->caps->err_mask;
202 if (err == ecc->caps->err_mask) {
203 /* uncorrectable errors */
208 stats->corrected += err;
209 bitflips = max_t(u32, bitflips, err);
212 stats->bitflips = bitflips;
214 EXPORT_SYMBOL(mtk_ecc_get_stats);
216 void mtk_ecc_release(struct mtk_ecc *ecc)
218 clk_disable_unprepare(ecc->clk);
219 put_device(ecc->dev);
221 EXPORT_SYMBOL(mtk_ecc_release);
223 static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
225 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
226 writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
228 mtk_ecc_wait_idle(ecc, ECC_DECODE);
229 writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
232 static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
234 struct platform_device *pdev;
237 pdev = of_find_device_by_node(np);
238 if (!pdev || !platform_get_drvdata(pdev))
239 return ERR_PTR(-EPROBE_DEFER);
241 get_device(&pdev->dev);
242 ecc = platform_get_drvdata(pdev);
243 clk_prepare_enable(ecc->clk);
244 mtk_ecc_hw_init(ecc);
249 struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
251 struct mtk_ecc *ecc = NULL;
252 struct device_node *np;
254 np = of_parse_phandle(of_node, "ecc-engine", 0);
256 ecc = mtk_ecc_get(np);
262 EXPORT_SYMBOL(of_mtk_ecc_get);
264 int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
266 enum mtk_ecc_operation op = config->op;
270 ret = mutex_lock_interruptible(&ecc->lock);
272 dev_err(ecc->dev, "interrupted when attempting to lock\n");
276 mtk_ecc_wait_idle(ecc, op);
278 ret = mtk_ecc_config(ecc, config);
280 mutex_unlock(&ecc->lock);
284 if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
285 init_completion(&ecc->done);
286 reg_val = ECC_IRQ_EN;
288 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
289 * means this chip can only generate one ecc irq during page
290 * read / write. If is 0, generate one ecc irq each ecc step.
292 if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
293 reg_val |= ECC_PG_IRQ_SEL;
294 writew(reg_val, ecc->regs + ECC_IRQ_REG(op));
297 writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
301 EXPORT_SYMBOL(mtk_ecc_enable);
303 void mtk_ecc_disable(struct mtk_ecc *ecc)
305 enum mtk_ecc_operation op = ECC_ENCODE;
307 /* find out the running operation */
308 if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
312 mtk_ecc_wait_idle(ecc, op);
313 if (op == ECC_DECODE)
315 * Clear decode IRQ status in case there is a timeout to wait
318 readw(ecc->regs + ECC_DECIRQ_STA);
319 writew(0, ecc->regs + ECC_IRQ_REG(op));
320 writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
322 mutex_unlock(&ecc->lock);
324 EXPORT_SYMBOL(mtk_ecc_disable);
326 int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
330 ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
332 dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
333 (op == ECC_ENCODE) ? "encoder" : "decoder");
339 EXPORT_SYMBOL(mtk_ecc_wait_done);
341 int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
348 addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
349 ret = dma_mapping_error(ecc->dev, addr);
351 dev_err(ecc->dev, "dma mapping error\n");
355 config->op = ECC_ENCODE;
357 ret = mtk_ecc_enable(ecc, config);
359 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
363 ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
367 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
369 /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
370 len = (config->strength * ECC_PARITY_BITS + 7) >> 3;
372 /* write the parity bytes generated by the ECC back to temp buffer */
373 __ioread32_copy(ecc->eccdata,
374 ecc->regs + ecc->caps->encode_parity_reg0,
377 /* copy into possibly unaligned OOB region with actual length */
378 memcpy(data + bytes, ecc->eccdata, len);
381 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
382 mtk_ecc_disable(ecc);
386 EXPORT_SYMBOL(mtk_ecc_encode);
388 void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
390 const u8 *ecc_strength = ecc->caps->ecc_strength;
393 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
394 if (*p <= ecc_strength[i]) {
396 *p = ecc_strength[i];
397 else if (*p != ecc_strength[i])
398 *p = ecc_strength[i - 1];
403 *p = ecc_strength[ecc->caps->num_ecc_strength - 1];
405 EXPORT_SYMBOL(mtk_ecc_adjust_strength);
407 static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
409 .ecc_strength = ecc_strength_mt2701,
410 .num_ecc_strength = 20,
411 .encode_parity_reg0 = 0x10,
415 static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
417 .ecc_strength = ecc_strength_mt2712,
418 .num_ecc_strength = 23,
419 .encode_parity_reg0 = 0x300,
423 static const struct of_device_id mtk_ecc_dt_match[] = {
425 .compatible = "mediatek,mt2701-ecc",
426 .data = &mtk_ecc_caps_mt2701,
428 .compatible = "mediatek,mt2712-ecc",
429 .data = &mtk_ecc_caps_mt2712,
434 static int mtk_ecc_probe(struct platform_device *pdev)
436 struct device *dev = &pdev->dev;
438 struct resource *res;
439 const struct of_device_id *of_ecc_id = NULL;
440 u32 max_eccdata_size;
443 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
447 of_ecc_id = of_match_device(mtk_ecc_dt_match, &pdev->dev);
451 ecc->caps = of_ecc_id->data;
453 max_eccdata_size = ecc->caps->num_ecc_strength - 1;
454 max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
455 max_eccdata_size = (max_eccdata_size * ECC_PARITY_BITS + 7) >> 3;
456 max_eccdata_size = round_up(max_eccdata_size, 4);
457 ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
461 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
462 ecc->regs = devm_ioremap_resource(dev, res);
463 if (IS_ERR(ecc->regs)) {
464 dev_err(dev, "failed to map regs: %ld\n", PTR_ERR(ecc->regs));
465 return PTR_ERR(ecc->regs);
468 ecc->clk = devm_clk_get(dev, NULL);
469 if (IS_ERR(ecc->clk)) {
470 dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
471 return PTR_ERR(ecc->clk);
474 irq = platform_get_irq(pdev, 0);
476 dev_err(dev, "failed to get irq: %d\n", irq);
480 ret = dma_set_mask(dev, DMA_BIT_MASK(32));
482 dev_err(dev, "failed to set DMA mask\n");
486 ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
488 dev_err(dev, "failed to request irq\n");
493 mutex_init(&ecc->lock);
494 platform_set_drvdata(pdev, ecc);
495 dev_info(dev, "probed\n");
500 #ifdef CONFIG_PM_SLEEP
501 static int mtk_ecc_suspend(struct device *dev)
503 struct mtk_ecc *ecc = dev_get_drvdata(dev);
505 clk_disable_unprepare(ecc->clk);
510 static int mtk_ecc_resume(struct device *dev)
512 struct mtk_ecc *ecc = dev_get_drvdata(dev);
515 ret = clk_prepare_enable(ecc->clk);
517 dev_err(dev, "failed to enable clk\n");
524 static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
527 MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
529 static struct platform_driver mtk_ecc_driver = {
530 .probe = mtk_ecc_probe,
533 .of_match_table = of_match_ptr(mtk_ecc_dt_match),
534 #ifdef CONFIG_PM_SLEEP
535 .pm = &mtk_ecc_pm_ops,
540 module_platform_driver(mtk_ecc_driver);
542 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
543 MODULE_DESCRIPTION("MTK Nand ECC Driver");
544 MODULE_LICENSE("GPL");