2 * Freescale Integrated Flash Controller NAND driver
4 * Copyright 2011-2012 Freescale Semiconductor, Inc
6 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/of_address.h>
27 #include <linux/slab.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/rawnand.h>
30 #include <linux/mtd/partitions.h>
31 #include <linux/mtd/nand_ecc.h>
32 #include <linux/fsl_ifc.h>
34 #define ERR_BYTE 0xFF /* Value returned for read
35 bytes when read failed */
36 #define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait
37 for IFC NAND Machine */
41 /* mtd information per set */
43 struct nand_chip chip;
44 struct fsl_ifc_ctrl *ctrl;
47 int bank; /* Chip select bank number */
48 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
49 u8 __iomem *vbase; /* Chip select base virtual address */
52 /* overview of the fsl ifc controller */
53 struct fsl_ifc_nand_ctrl {
54 struct nand_hw_control controller;
55 struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
57 void __iomem *addr; /* Address of assigned IFC buffer */
58 unsigned int page; /* Last page written to / read from */
59 unsigned int read_bytes;/* Number of bytes read during command */
60 unsigned int column; /* Saved column from SEQIN */
61 unsigned int index; /* Pointer to next byte to 'read' */
62 unsigned int oob; /* Non zero if operating on OOB data */
63 unsigned int eccread; /* Non zero for a full-page ECC read */
64 unsigned int counter; /* counter for the initializations */
65 unsigned int max_bitflips; /* Saved during READ0 cmd */
68 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
71 * Generic flash bbt descriptors
73 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
74 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
76 static struct nand_bbt_descr bbt_main_descr = {
77 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
78 NAND_BBT_2BIT | NAND_BBT_VERSION,
79 .offs = 2, /* 0 on 8-bit small page */
83 .pattern = bbt_pattern,
86 static struct nand_bbt_descr bbt_mirror_descr = {
87 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
88 NAND_BBT_2BIT | NAND_BBT_VERSION,
89 .offs = 2, /* 0 on 8-bit small page */
93 .pattern = mirror_pattern,
96 static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section,
97 struct mtd_oob_region *oobregion)
99 struct nand_chip *chip = mtd_to_nand(mtd);
104 oobregion->offset = 8;
105 oobregion->length = chip->ecc.total;
110 static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section,
111 struct mtd_oob_region *oobregion)
113 struct nand_chip *chip = mtd_to_nand(mtd);
118 if (mtd->writesize == 512 &&
119 !(chip->options & NAND_BUSWIDTH_16)) {
121 oobregion->offset = 0;
122 oobregion->length = 5;
124 oobregion->offset = 6;
125 oobregion->length = 2;
132 oobregion->offset = 2;
133 oobregion->length = 6;
135 oobregion->offset = chip->ecc.total + 8;
136 oobregion->length = mtd->oobsize - oobregion->offset;
142 static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = {
143 .ecc = fsl_ifc_ooblayout_ecc,
144 .free = fsl_ifc_ooblayout_free,
148 * Set up the IFC hardware block and page address fields, and the ifc nand
149 * structure addr field to point to the correct IFC buffer in memory
151 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
153 struct nand_chip *chip = mtd_to_nand(mtd);
154 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
155 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
156 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
159 ifc_nand_ctrl->page = page_addr;
160 /* Program ROW0/COL0 */
161 ifc_out32(page_addr, &ifc->ifc_nand.row0);
162 ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
164 buf_num = page_addr & priv->bufnum_mask;
166 ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
167 ifc_nand_ctrl->index = column;
169 /* for OOB data point to the second half of the buffer */
171 ifc_nand_ctrl->index += mtd->writesize;
174 /* returns nonzero if entire page is blank */
175 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
176 u32 eccstat, unsigned int bufnum)
178 return (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
182 * execute IFC NAND command and wait for it to complete
184 static void fsl_ifc_run_command(struct mtd_info *mtd)
186 struct nand_chip *chip = mtd_to_nand(mtd);
187 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
188 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
189 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
190 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
194 /* set the chip select for NAND Transaction */
195 ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
196 &ifc->ifc_nand.nand_csel);
199 "%s: fir0=%08x fcr0=%08x\n",
201 ifc_in32(&ifc->ifc_nand.nand_fir0),
202 ifc_in32(&ifc->ifc_nand.nand_fcr0));
206 /* start read/write seq */
207 ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
209 /* wait for command complete flag or timeout */
210 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
211 msecs_to_jiffies(IFC_TIMEOUT_MSECS));
213 /* ctrl->nand_stat will be updated from IRQ context */
214 if (!ctrl->nand_stat)
215 dev_err(priv->dev, "Controller is not responding\n");
216 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
217 dev_err(priv->dev, "NAND Flash Timeout Error\n");
218 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
219 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
221 nctrl->max_bitflips = 0;
223 if (nctrl->eccread) {
225 int bufnum = nctrl->page & priv->bufnum_mask;
226 int sector_start = bufnum * chip->ecc.steps;
227 int sector_end = sector_start + chip->ecc.steps - 1;
228 __be32 *eccstat_regs;
230 eccstat_regs = ifc->ifc_nand.nand_eccstat;
231 eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
233 for (i = sector_start; i <= sector_end; i++) {
234 if (i != sector_start && !(i % 4))
235 eccstat = ifc_in32(&eccstat_regs[i / 4]);
237 errors = check_read_ecc(mtd, ctrl, eccstat, i);
241 * Uncorrectable error.
242 * We'll check for blank pages later.
244 * We disable ECCER reporting due to...
245 * erratum IFC-A002770 -- so report it now if we
246 * see an uncorrectable error in ECCSTAT.
248 ctrl->nand_stat |= IFC_NAND_EVTER_STAT_ECCER;
252 mtd->ecc_stats.corrected += errors;
253 nctrl->max_bitflips = max_t(unsigned int,
262 static void fsl_ifc_do_read(struct nand_chip *chip,
264 struct mtd_info *mtd)
266 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
267 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
268 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
270 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
271 if (mtd->writesize > 512) {
272 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
273 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
274 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
275 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
276 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
277 &ifc->ifc_nand.nand_fir0);
278 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
280 ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
281 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
282 &ifc->ifc_nand.nand_fcr0);
284 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
285 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
286 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
287 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
288 &ifc->ifc_nand.nand_fir0);
289 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
292 ifc_out32(NAND_CMD_READOOB <<
293 IFC_NAND_FCR0_CMD0_SHIFT,
294 &ifc->ifc_nand.nand_fcr0);
296 ifc_out32(NAND_CMD_READ0 <<
297 IFC_NAND_FCR0_CMD0_SHIFT,
298 &ifc->ifc_nand.nand_fcr0);
302 /* cmdfunc send commands to the IFC NAND Machine */
303 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
304 int column, int page_addr) {
305 struct nand_chip *chip = mtd_to_nand(mtd);
306 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
307 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
308 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
310 /* clear the read buffer */
311 ifc_nand_ctrl->read_bytes = 0;
312 if (command != NAND_CMD_PAGEPROG)
313 ifc_nand_ctrl->index = 0;
316 /* READ0 read the entire buffer to use hardware ECC. */
318 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
319 set_addr(mtd, 0, page_addr, 0);
321 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
322 ifc_nand_ctrl->index += column;
324 if (chip->ecc.mode == NAND_ECC_HW)
325 ifc_nand_ctrl->eccread = 1;
327 fsl_ifc_do_read(chip, 0, mtd);
328 fsl_ifc_run_command(mtd);
331 /* READOOB reads only the OOB because no ECC is performed. */
332 case NAND_CMD_READOOB:
333 ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
334 set_addr(mtd, column, page_addr, 1);
336 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
338 fsl_ifc_do_read(chip, 1, mtd);
339 fsl_ifc_run_command(mtd);
343 case NAND_CMD_READID:
344 case NAND_CMD_PARAM: {
346 * For READID, read 8 bytes that are currently used.
347 * For PARAM, read all 3 copies of 256-bytes pages.
350 int timing = IFC_FIR_OP_RB;
351 if (command == NAND_CMD_PARAM) {
352 timing = IFC_FIR_OP_RBCD;
356 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
357 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
358 (timing << IFC_NAND_FIR0_OP2_SHIFT),
359 &ifc->ifc_nand.nand_fir0);
360 ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
361 &ifc->ifc_nand.nand_fcr0);
362 ifc_out32(column, &ifc->ifc_nand.row3);
364 ifc_out32(len, &ifc->ifc_nand.nand_fbcr);
365 ifc_nand_ctrl->read_bytes = len;
367 set_addr(mtd, 0, 0, 0);
368 fsl_ifc_run_command(mtd);
372 /* ERASE1 stores the block and page address */
373 case NAND_CMD_ERASE1:
374 set_addr(mtd, 0, page_addr, 0);
377 /* ERASE2 uses the block and page address from ERASE1 */
378 case NAND_CMD_ERASE2:
379 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
380 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
381 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
382 &ifc->ifc_nand.nand_fir0);
384 ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
385 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
386 &ifc->ifc_nand.nand_fcr0);
388 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
389 ifc_nand_ctrl->read_bytes = 0;
390 fsl_ifc_run_command(mtd);
393 /* SEQIN sets up the addr buffer and all registers except the length */
394 case NAND_CMD_SEQIN: {
396 ifc_nand_ctrl->column = column;
397 ifc_nand_ctrl->oob = 0;
399 if (mtd->writesize > 512) {
401 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
402 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
403 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
406 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
407 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
408 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
409 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
410 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
411 &ifc->ifc_nand.nand_fir0);
413 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
414 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) |
415 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
416 &ifc->ifc_nand.nand_fir1);
418 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
419 IFC_NAND_FCR0_CMD1_SHIFT) |
421 IFC_NAND_FCR0_CMD2_SHIFT) |
423 IFC_NAND_FCR0_CMD3_SHIFT));
426 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
427 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
428 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
429 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
430 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
431 &ifc->ifc_nand.nand_fir0);
433 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
434 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
435 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) |
436 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
437 &ifc->ifc_nand.nand_fir1);
439 if (column >= mtd->writesize)
441 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
444 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
447 if (column >= mtd->writesize) {
448 /* OOB area --> READOOB */
449 column -= mtd->writesize;
450 ifc_nand_ctrl->oob = 1;
452 ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
453 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
457 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
458 case NAND_CMD_PAGEPROG: {
459 if (ifc_nand_ctrl->oob) {
460 ifc_out32(ifc_nand_ctrl->index -
461 ifc_nand_ctrl->column,
462 &ifc->ifc_nand.nand_fbcr);
464 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
467 fsl_ifc_run_command(mtd);
471 case NAND_CMD_STATUS: {
474 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
475 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
476 &ifc->ifc_nand.nand_fir0);
477 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
478 &ifc->ifc_nand.nand_fcr0);
479 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
480 set_addr(mtd, 0, 0, 0);
481 ifc_nand_ctrl->read_bytes = 1;
483 fsl_ifc_run_command(mtd);
486 * The chip always seems to report that it is
487 * write-protected, even when it is not.
489 addr = ifc_nand_ctrl->addr;
490 if (chip->options & NAND_BUSWIDTH_16)
491 ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr);
493 ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr);
498 ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
499 &ifc->ifc_nand.nand_fir0);
500 ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
501 &ifc->ifc_nand.nand_fcr0);
502 fsl_ifc_run_command(mtd);
506 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
511 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
513 /* The hardware does not seem to support multiple
519 * Write buf to the IFC NAND Controller Data Buffer
521 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
523 struct nand_chip *chip = mtd_to_nand(mtd);
524 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
525 unsigned int bufsize = mtd->writesize + mtd->oobsize;
528 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
532 if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
534 "%s: beyond end of buffer (%d requested, %u available)\n",
535 __func__, len, bufsize - ifc_nand_ctrl->index);
536 len = bufsize - ifc_nand_ctrl->index;
539 memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
540 ifc_nand_ctrl->index += len;
544 * Read a byte from either the IFC hardware buffer
545 * read function for 8-bit buswidth
547 static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
549 struct nand_chip *chip = mtd_to_nand(mtd);
550 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
554 * If there are still bytes in the IFC buffer, then use the
557 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
558 offset = ifc_nand_ctrl->index++;
559 return ifc_in8(ifc_nand_ctrl->addr + offset);
562 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
567 * Read two bytes from the IFC hardware buffer
568 * read function for 16-bit buswith
570 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
572 struct nand_chip *chip = mtd_to_nand(mtd);
573 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
577 * If there are still bytes in the IFC buffer, then use the
580 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
581 data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
582 ifc_nand_ctrl->index += 2;
583 return (uint8_t) data;
586 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
591 * Read from the IFC Controller Data Buffer
593 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
595 struct nand_chip *chip = mtd_to_nand(mtd);
596 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
600 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
604 avail = min((unsigned int)len,
605 ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
606 memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
607 ifc_nand_ctrl->index += avail;
611 "%s: beyond end of buffer (%d requested, %d available)\n",
612 __func__, len, avail);
616 * This function is called after Program and Erase Operations to
617 * check for success or failure.
619 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
621 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
622 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
623 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
627 /* Use READ_STATUS command, but wait for the device to be ready */
628 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
629 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
630 &ifc->ifc_nand.nand_fir0);
631 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
632 &ifc->ifc_nand.nand_fcr0);
633 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
634 set_addr(mtd, 0, 0, 0);
635 ifc_nand_ctrl->read_bytes = 1;
637 fsl_ifc_run_command(mtd);
639 nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
640 status = nand_fsr >> 24;
642 * The chip always seems to report that it is
643 * write-protected, even when it is not.
645 return status | NAND_STATUS_WP;
649 * The controller does not check for bitflips in erased pages,
650 * therefore software must check instead.
652 static int check_erased_page(struct nand_chip *chip, u8 *buf)
654 struct mtd_info *mtd = nand_to_mtd(chip);
655 u8 *ecc = chip->oob_poi;
656 const int ecc_size = chip->ecc.bytes;
657 const int pkt_size = chip->ecc.size;
658 int i, res, bitflips = 0;
659 struct mtd_oob_region oobregion = { };
661 mtd_ooblayout_ecc(mtd, 0, &oobregion);
662 ecc += oobregion.offset;
664 for (i = 0; i < chip->ecc.steps; ++i) {
665 res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
669 mtd->ecc_stats.failed++;
671 mtd->ecc_stats.corrected += res;
673 bitflips = max(res, bitflips);
681 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
682 uint8_t *buf, int oob_required, int page)
684 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
685 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
686 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
688 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
690 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
692 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) {
694 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
696 return check_erased_page(chip, buf);
699 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
700 mtd->ecc_stats.failed++;
702 return nctrl->max_bitflips;
705 /* ECC will be calculated automatically, and errors will be detected in
708 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
709 const uint8_t *buf, int oob_required, int page)
711 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
712 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
717 static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
719 struct nand_chip *chip = mtd_to_nand(mtd);
720 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
722 dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
724 dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
726 dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
728 dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
730 dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
732 dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
734 dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
736 dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
737 chip->phys_erase_shift);
738 dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
740 dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
742 dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
744 dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
746 dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__,
748 dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
749 dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
750 dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
752 dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
754 dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
760 static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
762 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
763 struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
764 struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
765 uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
766 uint32_t cs = priv->bank;
768 /* Save CSOR and CSOR_ext */
769 csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
770 csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
772 /* chage PageSize 8K and SpareSize 1K*/
773 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
774 ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor);
775 ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext);
778 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
779 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
780 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
781 &ifc_runtime->ifc_nand.nand_fir0);
782 ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
783 &ifc_runtime->ifc_nand.nand_fcr0);
784 ifc_out32(0x0, &ifc_runtime->ifc_nand.row3);
786 ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr);
788 /* Program ROW0/COL0 */
789 ifc_out32(0x0, &ifc_runtime->ifc_nand.row0);
790 ifc_out32(0x0, &ifc_runtime->ifc_nand.col0);
792 /* set the chip select for NAND Transaction */
793 ifc_out32(cs << IFC_NAND_CSEL_SHIFT,
794 &ifc_runtime->ifc_nand.nand_csel);
797 ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT,
798 &ifc_runtime->ifc_nand.nandseq_strt);
800 /* wait for command complete flag or timeout */
801 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
802 msecs_to_jiffies(IFC_TIMEOUT_MSECS));
804 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
805 printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
807 /* Restore CSOR and CSOR_ext */
808 ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
809 ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
812 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
814 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
815 struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
816 struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
817 struct nand_chip *chip = &priv->chip;
818 struct mtd_info *mtd = nand_to_mtd(&priv->chip);
821 /* Fill in fsl_ifc_mtd structure */
822 mtd->dev.parent = priv->dev;
823 nand_set_flash_node(chip, priv->dev->of_node);
825 /* fill in nand_chip structure */
826 /* set up function call table */
827 if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
829 chip->read_byte = fsl_ifc_read_byte16;
831 chip->read_byte = fsl_ifc_read_byte;
833 chip->write_buf = fsl_ifc_write_buf;
834 chip->read_buf = fsl_ifc_read_buf;
835 chip->select_chip = fsl_ifc_select_chip;
836 chip->cmdfunc = fsl_ifc_cmdfunc;
837 chip->waitfunc = fsl_ifc_wait;
838 chip->onfi_set_features = nand_onfi_get_set_features_notsupp;
839 chip->onfi_get_features = nand_onfi_get_set_features_notsupp;
841 chip->bbt_td = &bbt_main_descr;
842 chip->bbt_md = &bbt_mirror_descr;
844 ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
846 /* set up nand options */
847 chip->bbt_options = NAND_BBT_USE_FLASH;
848 chip->options = NAND_NO_SUBPAGE_WRITE;
850 if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
851 & CSPR_PORT_SIZE_16) {
852 chip->read_byte = fsl_ifc_read_byte16;
853 chip->options |= NAND_BUSWIDTH_16;
855 chip->read_byte = fsl_ifc_read_byte;
858 chip->controller = &ifc_nand_ctrl->controller;
859 nand_set_controller_data(chip, priv);
861 chip->ecc.read_page = fsl_ifc_read_page;
862 chip->ecc.write_page = fsl_ifc_write_page;
864 csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
866 switch (csor & CSOR_NAND_PGS_MASK) {
867 case CSOR_NAND_PGS_512:
868 if (!(chip->options & NAND_BUSWIDTH_16)) {
869 /* Avoid conflict with bad block marker */
870 bbt_main_descr.offs = 0;
871 bbt_mirror_descr.offs = 0;
874 priv->bufnum_mask = 15;
877 case CSOR_NAND_PGS_2K:
878 priv->bufnum_mask = 3;
881 case CSOR_NAND_PGS_4K:
882 priv->bufnum_mask = 1;
885 case CSOR_NAND_PGS_8K:
886 priv->bufnum_mask = 0;
890 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
894 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
895 if (csor & CSOR_NAND_ECC_DEC_EN) {
896 chip->ecc.mode = NAND_ECC_HW;
897 mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
899 /* Hardware generates ECC per 512 Bytes */
900 chip->ecc.size = 512;
901 if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
903 chip->ecc.strength = 4;
905 chip->ecc.bytes = 16;
906 chip->ecc.strength = 8;
909 chip->ecc.mode = NAND_ECC_SOFT;
910 chip->ecc.algo = NAND_ECC_HAMMING;
913 if (ctrl->version >= FSL_IFC_VERSION_1_1_0)
914 fsl_ifc_sram_init(priv);
917 * As IFC version 2.0.0 has 16KB of internal SRAM as compared to older
918 * versions which had 8KB. Hence bufnum mask needs to be updated.
920 if (ctrl->version >= FSL_IFC_VERSION_2_0_0)
921 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
926 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
928 struct mtd_info *mtd = nand_to_mtd(&priv->chip);
930 nand_release(&priv->chip);
935 iounmap(priv->vbase);
937 ifc_nand_ctrl->chips[priv->bank] = NULL;
942 static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank,
945 u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);
947 if (!(cspr & CSPR_V))
949 if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
952 return (cspr & CSPR_BA) == convert_ifc_address(addr);
955 static DEFINE_MUTEX(fsl_ifc_nand_mutex);
957 static int fsl_ifc_nand_probe(struct platform_device *dev)
959 struct fsl_ifc_runtime __iomem *ifc;
960 struct fsl_ifc_mtd *priv;
962 static const char *part_probe_types[]
963 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
966 struct device_node *node = dev->dev.of_node;
967 struct mtd_info *mtd;
969 if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs)
971 ifc = fsl_ifc_ctrl_dev->rregs;
973 /* get, allocate and map the memory resource */
974 ret = of_address_to_resource(node, 0, &res);
976 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
980 /* find which chip select it is connected to */
981 for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
982 if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))
986 if (bank >= fsl_ifc_ctrl_dev->banks) {
987 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
992 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
996 mutex_lock(&fsl_ifc_nand_mutex);
997 if (!fsl_ifc_ctrl_dev->nand) {
998 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
999 if (!ifc_nand_ctrl) {
1000 mutex_unlock(&fsl_ifc_nand_mutex);
1004 ifc_nand_ctrl->read_bytes = 0;
1005 ifc_nand_ctrl->index = 0;
1006 ifc_nand_ctrl->addr = NULL;
1007 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
1009 nand_hw_control_init(&ifc_nand_ctrl->controller);
1011 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
1013 mutex_unlock(&fsl_ifc_nand_mutex);
1015 ifc_nand_ctrl->chips[bank] = priv;
1017 priv->ctrl = fsl_ifc_ctrl_dev;
1018 priv->dev = &dev->dev;
1020 priv->vbase = ioremap(res.start, resource_size(&res));
1022 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1027 dev_set_drvdata(priv->dev, priv);
1029 ifc_out32(IFC_NAND_EVTER_EN_OPC_EN |
1030 IFC_NAND_EVTER_EN_FTOER_EN |
1031 IFC_NAND_EVTER_EN_WPER_EN,
1032 &ifc->ifc_nand.nand_evter_en);
1034 /* enable NAND Machine Interrupts */
1035 ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN |
1036 IFC_NAND_EVTER_INTR_FTOERIR_EN |
1037 IFC_NAND_EVTER_INTR_WPERIR_EN,
1038 &ifc->ifc_nand.nand_evter_intr_en);
1040 mtd = nand_to_mtd(&priv->chip);
1041 mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1047 ret = fsl_ifc_chip_init(priv);
1051 ret = nand_scan_ident(mtd, 1, NULL);
1055 ret = fsl_ifc_chip_init_tail(mtd);
1059 ret = nand_scan_tail(mtd);
1063 /* First look for RedBoot table or partitions on the command
1064 * line, these take precedence over device tree information */
1065 mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
1067 dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1068 (unsigned long long)res.start, priv->bank);
1072 fsl_ifc_chip_remove(priv);
1076 static int fsl_ifc_nand_remove(struct platform_device *dev)
1078 struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1080 fsl_ifc_chip_remove(priv);
1082 mutex_lock(&fsl_ifc_nand_mutex);
1083 ifc_nand_ctrl->counter--;
1084 if (!ifc_nand_ctrl->counter) {
1085 fsl_ifc_ctrl_dev->nand = NULL;
1086 kfree(ifc_nand_ctrl);
1088 mutex_unlock(&fsl_ifc_nand_mutex);
1093 static const struct of_device_id fsl_ifc_nand_match[] = {
1095 .compatible = "fsl,ifc-nand",
1099 MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match);
1101 static struct platform_driver fsl_ifc_nand_driver = {
1103 .name = "fsl,ifc-nand",
1104 .of_match_table = fsl_ifc_nand_match,
1106 .probe = fsl_ifc_nand_probe,
1107 .remove = fsl_ifc_nand_remove,
1110 module_platform_driver(fsl_ifc_nand_driver);
1112 MODULE_LICENSE("GPL");
1113 MODULE_AUTHOR("Freescale");
1114 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");