drivers/mtd/nand/brcmnand/brcmnand.c

   1 /*
   2  * Copyright © 2010-2015 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/version.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/err.h>
  21 #include <linux/completion.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/ioport.h>
  26 #include <linux/bug.h>
  27 #include <linux/kernel.h>
  28 #include <linux/bitops.h>
  29 #include <linux/mm.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/partitions.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mtd.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/slab.h>
  37 #include <linux/list.h>
  38 #include <linux/log2.h>
  39
  40 #include "brcmnand.h"
  41
  42 /*
  43  * This flag controls if WP stays on between erase/write commands to mitigate
  44  * flash corruption due to power glitches. Values:
  45  * 0: NAND_WP is not used or not available
  46  * 1: NAND_WP is set by default, cleared for erase/write operations
  47  * 2: NAND_WP is always cleared
  48  */
  49 static int wp_on = 1;
  50 module_param(wp_on, int, 0444);
  51
  52 /***********************************************************************
  53  * Definitions
  54  ***********************************************************************/
  55
  56 #define DRV_NAME                        "brcmnand"
  57
  58 #define CMD_NULL                        0x00
  59 #define CMD_PAGE_READ                   0x01
  60 #define CMD_SPARE_AREA_READ             0x02
  61 #define CMD_STATUS_READ                 0x03
  62 #define CMD_PROGRAM_PAGE                0x04
  63 #define CMD_PROGRAM_SPARE_AREA          0x05
  64 #define CMD_COPY_BACK                   0x06
  65 #define CMD_DEVICE_ID_READ              0x07
  66 #define CMD_BLOCK_ERASE                 0x08
  67 #define CMD_FLASH_RESET                 0x09
  68 #define CMD_BLOCKS_LOCK                 0x0a
  69 #define CMD_BLOCKS_LOCK_DOWN            0x0b
  70 #define CMD_BLOCKS_UNLOCK               0x0c
  71 #define CMD_READ_BLOCKS_LOCK_STATUS     0x0d
  72 #define CMD_PARAMETER_READ              0x0e
  73 #define CMD_PARAMETER_CHANGE_COL        0x0f
  74 #define CMD_LOW_LEVEL_OP                0x10
  75
  76 struct brcm_nand_dma_desc {
  77         u32 next_desc;
  78         u32 next_desc_ext;
  79         u32 cmd_irq;
  80         u32 dram_addr;
  81         u32 dram_addr_ext;
  82         u32 tfr_len;
  83         u32 total_len;
  84         u32 flash_addr;
  85         u32 flash_addr_ext;
  86         u32 cs;
  87         u32 pad2[5];
  88         u32 status_valid;
  89 } __packed;
  90
  91 /* Bitfields for brcm_nand_dma_desc::status_valid */
  92 #define FLASH_DMA_ECC_ERROR     (1 << 8)
  93 #define FLASH_DMA_CORR_ERROR    (1 << 9)
  94
  95 /* 512B flash cache in the NAND controller HW */
  96 #define FC_SHIFT                9U
  97 #define FC_BYTES                512U
  98 #define FC_WORDS                (FC_BYTES >> 2)
  99
 100 #define BRCMNAND_MIN_PAGESIZE   512
 101 #define BRCMNAND_MIN_BLOCKSIZE  (8 * 1024)
 102 #define BRCMNAND_MIN_DEVSIZE    (4ULL * 1024 * 1024)
 103
 104 /* Controller feature flags */
 105 enum {
 106         BRCMNAND_HAS_1K_SECTORS                 = BIT(0),
 107         BRCMNAND_HAS_PREFETCH                   = BIT(1),
 108         BRCMNAND_HAS_CACHE_MODE                 = BIT(2),
 109         BRCMNAND_HAS_WP                         = BIT(3),
 110 };
 111
 112 struct brcmnand_controller {
 113         struct device           *dev;
 114         struct nand_hw_control  controller;
 115         void __iomem            *nand_base;
 116         void __iomem            *nand_fc; /* flash cache */
 117         void __iomem            *flash_dma_base;
 118         unsigned int            irq;
 119         unsigned int            dma_irq;
 120         int                     nand_version;
 121
 122         /* Some SoCs provide custom interrupt status register(s) */
 123         struct brcmnand_soc     *soc;
 124
 125         int                     cmd_pending;
 126         bool                    dma_pending;
 127         struct completion       done;
 128         struct completion       dma_done;
 129
 130         /* List of NAND hosts (one for each chip-select) */
 131         struct list_head host_list;
 132
 133         struct brcm_nand_dma_desc *dma_desc;
 134         dma_addr_t              dma_pa;
 135
 136         /* in-memory cache of the FLASH_CACHE, used only for some commands */
 137         u32                     flash_cache[FC_WORDS];
 138
 139         /* Controller revision details */
 140         const u16               *reg_offsets;
 141         unsigned int            reg_spacing; /* between CS1, CS2, ... regs */
 142         const u8                *cs_offsets; /* within each chip-select */
 143         const u8                *cs0_offsets; /* within CS0, if different */
 144         unsigned int            max_block_size;
 145         const unsigned int      *block_sizes;
 146         unsigned int            max_page_size;
 147         const unsigned int      *page_sizes;
 148         unsigned int            max_oob;
 149         u32                     features;
 150
 151         /* for low-power standby/resume only */
 152         u32                     nand_cs_nand_select;
 153         u32                     nand_cs_nand_xor;
 154         u32                     corr_stat_threshold;
 155         u32                     flash_dma_mode;
 156 };
 157
 158 struct brcmnand_cfg {
 159         u64                     device_size;
 160         unsigned int            block_size;
 161         unsigned int            page_size;
 162         unsigned int            spare_area_size;
 163         unsigned int            device_width;
 164         unsigned int            col_adr_bytes;
 165         unsigned int            blk_adr_bytes;
 166         unsigned int            ful_adr_bytes;
 167         unsigned int            sector_size_1k;
 168         unsigned int            ecc_level;
 169         /* use for low-power standby/resume only */
 170         u32                     acc_control;
 171         u32                     config;
 172         u32                     config_ext;
 173         u32                     timing_1;
 174         u32                     timing_2;
 175 };
 176
 177 struct brcmnand_host {
 178         struct list_head        node;
 179         struct device_node      *of_node;
 180
 181         struct nand_chip        chip;
 182         struct mtd_info         mtd;
 183         struct platform_device  *pdev;
 184         int                     cs;
 185
 186         unsigned int            last_cmd;
 187         unsigned int            last_byte;
 188         u64                     last_addr;
 189         struct brcmnand_cfg     hwcfg;
 190         struct brcmnand_controller *ctrl;
 191 };
 192
 193 enum brcmnand_reg {
 194         BRCMNAND_CMD_START = 0,
 195         BRCMNAND_CMD_EXT_ADDRESS,
 196         BRCMNAND_CMD_ADDRESS,
 197         BRCMNAND_INTFC_STATUS,
 198         BRCMNAND_CS_SELECT,
 199         BRCMNAND_CS_XOR,
 200         BRCMNAND_LL_OP,
 201         BRCMNAND_CS0_BASE,
 202         BRCMNAND_CS1_BASE,              /* CS1 regs, if non-contiguous */
 203         BRCMNAND_CORR_THRESHOLD,
 204         BRCMNAND_CORR_THRESHOLD_EXT,
 205         BRCMNAND_UNCORR_COUNT,
 206         BRCMNAND_CORR_COUNT,
 207         BRCMNAND_CORR_EXT_ADDR,
 208         BRCMNAND_CORR_ADDR,
 209         BRCMNAND_UNCORR_EXT_ADDR,
 210         BRCMNAND_UNCORR_ADDR,
 211         BRCMNAND_SEMAPHORE,
 212         BRCMNAND_ID,
 213         BRCMNAND_ID_EXT,
 214         BRCMNAND_LL_RDATA,
 215         BRCMNAND_OOB_READ_BASE,
 216         BRCMNAND_OOB_READ_10_BASE,      /* offset 0x10, if non-contiguous */
 217         BRCMNAND_OOB_WRITE_BASE,
 218         BRCMNAND_OOB_WRITE_10_BASE,     /* offset 0x10, if non-contiguous */
 219         BRCMNAND_FC_BASE,
 220 };
 221
 222 /* BRCMNAND v4.0 */
 223 static const u16 brcmnand_regs_v40[] = {
 224         [BRCMNAND_CMD_START]            =  0x04,
 225         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 226         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 227         [BRCMNAND_INTFC_STATUS]         =  0x6c,
 228         [BRCMNAND_CS_SELECT]            =  0x14,
 229         [BRCMNAND_CS_XOR]               =  0x18,
 230         [BRCMNAND_LL_OP]                = 0x178,
 231         [BRCMNAND_CS0_BASE]             =  0x40,
 232         [BRCMNAND_CS1_BASE]             =  0xd0,
 233         [BRCMNAND_CORR_THRESHOLD]       =  0x84,
 234         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
 235         [BRCMNAND_UNCORR_COUNT]         =     0,
 236         [BRCMNAND_CORR_COUNT]           =     0,
 237         [BRCMNAND_CORR_EXT_ADDR]        =  0x70,
 238         [BRCMNAND_CORR_ADDR]            =  0x74,
 239         [BRCMNAND_UNCORR_EXT_ADDR]      =  0x78,
 240         [BRCMNAND_UNCORR_ADDR]          =  0x7c,
 241         [BRCMNAND_SEMAPHORE]            =  0x58,
 242         [BRCMNAND_ID]                   =  0x60,
 243         [BRCMNAND_ID_EXT]               =  0x64,
 244         [BRCMNAND_LL_RDATA]             = 0x17c,
 245         [BRCMNAND_OOB_READ_BASE]        =  0x20,
 246         [BRCMNAND_OOB_READ_10_BASE]     = 0x130,
 247         [BRCMNAND_OOB_WRITE_BASE]       =  0x30,
 248         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 249         [BRCMNAND_FC_BASE]              = 0x200,
 250 };
 251
 252 /* BRCMNAND v5.0 */
 253 static const u16 brcmnand_regs_v50[] = {
 254         [BRCMNAND_CMD_START]            =  0x04,
 255         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 256         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 257         [BRCMNAND_INTFC_STATUS]         =  0x6c,
 258         [BRCMNAND_CS_SELECT]            =  0x14,
 259         [BRCMNAND_CS_XOR]               =  0x18,
 260         [BRCMNAND_LL_OP]                = 0x178,
 261         [BRCMNAND_CS0_BASE]             =  0x40,
 262         [BRCMNAND_CS1_BASE]             =  0xd0,
 263         [BRCMNAND_CORR_THRESHOLD]       =  0x84,
 264         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
 265         [BRCMNAND_UNCORR_COUNT]         =     0,
 266         [BRCMNAND_CORR_COUNT]           =     0,
 267         [BRCMNAND_CORR_EXT_ADDR]        =  0x70,
 268         [BRCMNAND_CORR_ADDR]            =  0x74,
 269         [BRCMNAND_UNCORR_EXT_ADDR]      =  0x78,
 270         [BRCMNAND_UNCORR_ADDR]          =  0x7c,
 271         [BRCMNAND_SEMAPHORE]            =  0x58,
 272         [BRCMNAND_ID]                   =  0x60,
 273         [BRCMNAND_ID_EXT]               =  0x64,
 274         [BRCMNAND_LL_RDATA]             = 0x17c,
 275         [BRCMNAND_OOB_READ_BASE]        =  0x20,
 276         [BRCMNAND_OOB_READ_10_BASE]     = 0x130,
 277         [BRCMNAND_OOB_WRITE_BASE]       =  0x30,
 278         [BRCMNAND_OOB_WRITE_10_BASE]    = 0x140,
 279         [BRCMNAND_FC_BASE]              = 0x200,
 280 };
 281
 282 /* BRCMNAND v6.0 - v7.1 */
 283 static const u16 brcmnand_regs_v60[] = {
 284         [BRCMNAND_CMD_START]            =  0x04,
 285         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 286         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 287         [BRCMNAND_INTFC_STATUS]         =  0x14,
 288         [BRCMNAND_CS_SELECT]            =  0x18,
 289         [BRCMNAND_CS_XOR]               =  0x1c,
 290         [BRCMNAND_LL_OP]                =  0x20,
 291         [BRCMNAND_CS0_BASE]             =  0x50,
 292         [BRCMNAND_CS1_BASE]             =     0,
 293         [BRCMNAND_CORR_THRESHOLD]       =  0xc0,
 294         [BRCMNAND_CORR_THRESHOLD_EXT]   =  0xc4,
 295         [BRCMNAND_UNCORR_COUNT]         =  0xfc,
 296         [BRCMNAND_CORR_COUNT]           = 0x100,
 297         [BRCMNAND_CORR_EXT_ADDR]        = 0x10c,
 298         [BRCMNAND_CORR_ADDR]            = 0x110,
 299         [BRCMNAND_UNCORR_EXT_ADDR]      = 0x114,
 300         [BRCMNAND_UNCORR_ADDR]          = 0x118,
 301         [BRCMNAND_SEMAPHORE]            = 0x150,
 302         [BRCMNAND_ID]                   = 0x194,
 303         [BRCMNAND_ID_EXT]               = 0x198,
 304         [BRCMNAND_LL_RDATA]             = 0x19c,
 305         [BRCMNAND_OOB_READ_BASE]        = 0x200,
 306         [BRCMNAND_OOB_READ_10_BASE]     =     0,
 307         [BRCMNAND_OOB_WRITE_BASE]       = 0x280,
 308         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 309         [BRCMNAND_FC_BASE]              = 0x400,
 310 };
 311
 312 /* BRCMNAND v7.1 */
 313 static const u16 brcmnand_regs_v71[] = {
 314         [BRCMNAND_CMD_START]            =  0x04,
 315         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 316         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 317         [BRCMNAND_INTFC_STATUS]         =  0x14,
 318         [BRCMNAND_CS_SELECT]            =  0x18,
 319         [BRCMNAND_CS_XOR]               =  0x1c,
 320         [BRCMNAND_LL_OP]                =  0x20,
 321         [BRCMNAND_CS0_BASE]             =  0x50,
 322         [BRCMNAND_CS1_BASE]             =     0,
 323         [BRCMNAND_CORR_THRESHOLD]       =  0xdc,
 324         [BRCMNAND_CORR_THRESHOLD_EXT]   =  0xe0,
 325         [BRCMNAND_UNCORR_COUNT]         =  0xfc,
 326         [BRCMNAND_CORR_COUNT]           = 0x100,
 327         [BRCMNAND_CORR_EXT_ADDR]        = 0x10c,
 328         [BRCMNAND_CORR_ADDR]            = 0x110,
 329         [BRCMNAND_UNCORR_EXT_ADDR]      = 0x114,
 330         [BRCMNAND_UNCORR_ADDR]          = 0x118,
 331         [BRCMNAND_SEMAPHORE]            = 0x150,
 332         [BRCMNAND_ID]                   = 0x194,
 333         [BRCMNAND_ID_EXT]               = 0x198,
 334         [BRCMNAND_LL_RDATA]             = 0x19c,
 335         [BRCMNAND_OOB_READ_BASE]        = 0x200,
 336         [BRCMNAND_OOB_READ_10_BASE]     =     0,
 337         [BRCMNAND_OOB_WRITE_BASE]       = 0x280,
 338         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 339         [BRCMNAND_FC_BASE]              = 0x400,
 340 };
 341
 342 enum brcmnand_cs_reg {
 343         BRCMNAND_CS_CFG_EXT = 0,
 344         BRCMNAND_CS_CFG,
 345         BRCMNAND_CS_ACC_CONTROL,
 346         BRCMNAND_CS_TIMING1,
 347         BRCMNAND_CS_TIMING2,
 348 };
 349
 350 /* Per chip-select offsets for v7.1 */
 351 static const u8 brcmnand_cs_offsets_v71[] = {
 352         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 353         [BRCMNAND_CS_CFG_EXT]           = 0x04,
 354         [BRCMNAND_CS_CFG]               = 0x08,
 355         [BRCMNAND_CS_TIMING1]           = 0x0c,
 356         [BRCMNAND_CS_TIMING2]           = 0x10,
 357 };
 358
 359 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
 360 static const u8 brcmnand_cs_offsets[] = {
 361         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 362         [BRCMNAND_CS_CFG_EXT]           = 0x04,
 363         [BRCMNAND_CS_CFG]               = 0x04,
 364         [BRCMNAND_CS_TIMING1]           = 0x08,
 365         [BRCMNAND_CS_TIMING2]           = 0x0c,
 366 };
 367
 368 /* Per chip-select offset for <= v5.0 on CS0 only */
 369 static const u8 brcmnand_cs_offsets_cs0[] = {
 370         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 371         [BRCMNAND_CS_CFG_EXT]           = 0x08,
 372         [BRCMNAND_CS_CFG]               = 0x08,
 373         [BRCMNAND_CS_TIMING1]           = 0x10,
 374         [BRCMNAND_CS_TIMING2]           = 0x14,
 375 };
 376
 377 /*
 378  * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
 379  * one config register, but once the bitfields overflowed, newer controllers
 380  * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
 381  */
 382 enum {
 383         CFG_BLK_ADR_BYTES_SHIFT         = 8,
 384         CFG_COL_ADR_BYTES_SHIFT         = 12,
 385         CFG_FUL_ADR_BYTES_SHIFT         = 16,
 386         CFG_BUS_WIDTH_SHIFT             = 23,
 387         CFG_BUS_WIDTH                   = BIT(CFG_BUS_WIDTH_SHIFT),
 388         CFG_DEVICE_SIZE_SHIFT           = 24,
 389
 390         /* Only for pre-v7.1 (with no CFG_EXT register) */
 391         CFG_PAGE_SIZE_SHIFT             = 20,
 392         CFG_BLK_SIZE_SHIFT              = 28,
 393
 394         /* Only for v7.1+ (with CFG_EXT register) */
 395         CFG_EXT_PAGE_SIZE_SHIFT         = 0,
 396         CFG_EXT_BLK_SIZE_SHIFT          = 4,
 397 };
 398
 399 /* BRCMNAND_INTFC_STATUS */
 400 enum {
 401         INTFC_FLASH_STATUS              = GENMASK(7, 0),
 402
 403         INTFC_ERASED                    = BIT(27),
 404         INTFC_OOB_VALID                 = BIT(28),
 405         INTFC_CACHE_VALID               = BIT(29),
 406         INTFC_FLASH_READY               = BIT(30),
 407         INTFC_CTLR_READY                = BIT(31),
 408 };
 409
 410 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
 411 {
 412         return brcmnand_readl(ctrl->nand_base + offs);
 413 }
 414
 415 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
 416                                  u32 val)
 417 {
 418         brcmnand_writel(val, ctrl->nand_base + offs);
 419 }
 420
 421 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
 422 {
 423         static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
 424         static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
 425         static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
 426
 427         ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
 428
 429         /* Only support v4.0+? */
 430         if (ctrl->nand_version < 0x0400) {
 431                 dev_err(ctrl->dev, "version %#x not supported\n",
 432                         ctrl->nand_version);
 433                 return -ENODEV;
 434         }
 435
 436         /* Register offsets */
 437         if (ctrl->nand_version >= 0x0701)
 438                 ctrl->reg_offsets = brcmnand_regs_v71;
 439         else if (ctrl->nand_version >= 0x0600)
 440                 ctrl->reg_offsets = brcmnand_regs_v60;
 441         else if (ctrl->nand_version >= 0x0500)
 442                 ctrl->reg_offsets = brcmnand_regs_v50;
 443         else if (ctrl->nand_version >= 0x0400)
 444                 ctrl->reg_offsets = brcmnand_regs_v40;
 445
 446         /* Chip-select stride */
 447         if (ctrl->nand_version >= 0x0701)
 448                 ctrl->reg_spacing = 0x14;
 449         else
 450                 ctrl->reg_spacing = 0x10;
 451
 452         /* Per chip-select registers */
 453         if (ctrl->nand_version >= 0x0701) {
 454                 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
 455         } else {
 456                 ctrl->cs_offsets = brcmnand_cs_offsets;
 457
 458                 /* v3.3-5.0 have a different CS0 offset layout */
 459                 if (ctrl->nand_version >= 0x0303 &&
 460                     ctrl->nand_version <= 0x0500)
 461                         ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
 462         }
 463
 464         /* Page / block sizes */
 465         if (ctrl->nand_version >= 0x0701) {
 466                 /* >= v7.1 use nice power-of-2 values! */
 467                 ctrl->max_page_size = 16 * 1024;
 468                 ctrl->max_block_size = 2 * 1024 * 1024;
 469         } else {
 470                 ctrl->page_sizes = page_sizes;
 471                 if (ctrl->nand_version >= 0x0600)
 472                         ctrl->block_sizes = block_sizes_v6;
 473                 else
 474                         ctrl->block_sizes = block_sizes_v4;
 475
 476                 if (ctrl->nand_version < 0x0400) {
 477                         ctrl->max_page_size = 4096;
 478                         ctrl->max_block_size = 512 * 1024;
 479                 }
 480         }
 481
 482         /* Maximum spare area sector size (per 512B) */
 483         if (ctrl->nand_version >= 0x0600)
 484                 ctrl->max_oob = 64;
 485         else if (ctrl->nand_version >= 0x0500)
 486                 ctrl->max_oob = 32;
 487         else
 488                 ctrl->max_oob = 16;
 489
 490         /* v6.0 and newer (except v6.1) have prefetch support */
 491         if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
 492                 ctrl->features |= BRCMNAND_HAS_PREFETCH;
 493
 494         /*
 495          * v6.x has cache mode, but it's implemented differently. Ignore it for
 496          * now.
 497          */
 498         if (ctrl->nand_version >= 0x0700)
 499                 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
 500
 501         if (ctrl->nand_version >= 0x0500)
 502                 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
 503
 504         if (ctrl->nand_version >= 0x0700)
 505                 ctrl->features |= BRCMNAND_HAS_WP;
 506         else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
 507                 ctrl->features |= BRCMNAND_HAS_WP;
 508
 509         return 0;
 510 }
 511
 512 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
 513                 enum brcmnand_reg reg)
 514 {
 515         u16 offs = ctrl->reg_offsets[reg];
 516
 517         if (offs)
 518                 return nand_readreg(ctrl, offs);
 519         else
 520                 return 0;
 521 }
 522
 523 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
 524                                       enum brcmnand_reg reg, u32 val)
 525 {
 526         u16 offs = ctrl->reg_offsets[reg];
 527
 528         if (offs)
 529                 nand_writereg(ctrl, offs, val);
 530 }
 531
 532 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
 533                                     enum brcmnand_reg reg, u32 mask, unsigned
 534                                     int shift, u32 val)
 535 {
 536         u32 tmp = brcmnand_read_reg(ctrl, reg);
 537
 538         tmp &= ~mask;
 539         tmp |= val << shift;
 540         brcmnand_write_reg(ctrl, reg, tmp);
 541 }
 542
 543 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
 544 {
 545         return __raw_readl(ctrl->nand_fc + word * 4);
 546 }
 547
 548 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
 549                                      int word, u32 val)
 550 {
 551         __raw_writel(val, ctrl->nand_fc + word * 4);
 552 }
 553
 554 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
 555                                      enum brcmnand_cs_reg reg)
 556 {
 557         u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
 558         u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
 559         u8 cs_offs;
 560
 561         if (cs == 0 && ctrl->cs0_offsets)
 562                 cs_offs = ctrl->cs0_offsets[reg];
 563         else
 564                 cs_offs = ctrl->cs_offsets[reg];
 565
 566         if (cs && offs_cs1)
 567                 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
 568
 569         return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
 570 }
 571
 572 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
 573 {
 574         if (ctrl->nand_version < 0x0600)
 575                 return 1;
 576         return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
 577 }
 578
 579 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
 580 {
 581         struct brcmnand_controller *ctrl = host->ctrl;
 582         unsigned int shift = 0, bits;
 583         enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
 584         int cs = host->cs;
 585
 586         if (ctrl->nand_version >= 0x0600)
 587                 bits = 6;
 588         else if (ctrl->nand_version >= 0x0500)
 589                 bits = 5;
 590         else
 591                 bits = 4;
 592
 593         if (ctrl->nand_version >= 0x0600) {
 594                 if (cs >= 5)
 595                         reg = BRCMNAND_CORR_THRESHOLD_EXT;
 596                 shift = (cs % 5) * bits;
 597         }
 598         brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
 599 }
 600
 601 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
 602 {
 603         if (ctrl->nand_version < 0x0700)
 604                 return 24;
 605         return 0;
 606 }
 607
 608 /***********************************************************************
 609  * NAND ACC CONTROL bitfield
 610  *
 611  * Some bits have remained constant throughout hardware revision, while
 612  * others have shifted around.
 613  ***********************************************************************/
 614
 615 /* Constant for all versions (where supported) */
 616 enum {
 617         /* See BRCMNAND_HAS_CACHE_MODE */
 618         ACC_CONTROL_CACHE_MODE                          = BIT(22),
 619
 620         /* See BRCMNAND_HAS_PREFETCH */
 621         ACC_CONTROL_PREFETCH                            = BIT(23),
 622
 623         ACC_CONTROL_PAGE_HIT                            = BIT(24),
 624         ACC_CONTROL_WR_PREEMPT                          = BIT(25),
 625         ACC_CONTROL_PARTIAL_PAGE                        = BIT(26),
 626         ACC_CONTROL_RD_ERASED                           = BIT(27),
 627         ACC_CONTROL_FAST_PGM_RDIN                       = BIT(28),
 628         ACC_CONTROL_WR_ECC                              = BIT(30),
 629         ACC_CONTROL_RD_ECC                              = BIT(31),
 630 };
 631
 632 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
 633 {
 634         if (ctrl->nand_version >= 0x0600)
 635                 return GENMASK(6, 0);
 636         else
 637                 return GENMASK(5, 0);
 638 }
 639
 640 #define NAND_ACC_CONTROL_ECC_SHIFT      16
 641
 642 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
 643 {
 644         u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
 645
 646         return mask << NAND_ACC_CONTROL_ECC_SHIFT;
 647 }
 648
 649 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
 650 {
 651         struct brcmnand_controller *ctrl = host->ctrl;
 652         u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
 653         u32 acc_control = nand_readreg(ctrl, offs);
 654         u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
 655
 656         if (en) {
 657                 acc_control |= ecc_flags; /* enable RD/WR ECC */
 658                 acc_control |= host->hwcfg.ecc_level
 659                                << NAND_ACC_CONTROL_ECC_SHIFT;
 660         } else {
 661                 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
 662                 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
 663         }
 664
 665         nand_writereg(ctrl, offs, acc_control);
 666 }
 667
 668 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
 669 {
 670         if (ctrl->nand_version >= 0x0600)
 671                 return 7;
 672         else if (ctrl->nand_version >= 0x0500)
 673                 return 6;
 674         else
 675                 return -1;
 676 }
 677
 678 static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
 679 {
 680         struct brcmnand_controller *ctrl = host->ctrl;
 681         int shift = brcmnand_sector_1k_shift(ctrl);
 682         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
 683                                                   BRCMNAND_CS_ACC_CONTROL);
 684
 685         if (shift < 0)
 686                 return 0;
 687
 688         return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
 689 }
 690
 691 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
 692 {
 693         struct brcmnand_controller *ctrl = host->ctrl;
 694         int shift = brcmnand_sector_1k_shift(ctrl);
 695         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
 696                                                   BRCMNAND_CS_ACC_CONTROL);
 697         u32 tmp;
 698
 699         if (shift < 0)
 700                 return;
 701
 702         tmp = nand_readreg(ctrl, acc_control_offs);
 703         tmp &= ~(1 << shift);
 704         tmp |= (!!val) << shift;
 705         nand_writereg(ctrl, acc_control_offs, tmp);
 706 }
 707
 708 /***********************************************************************
 709  * CS_NAND_SELECT
 710  ***********************************************************************/
 711
 712 enum {
 713         CS_SELECT_NAND_WP                       = BIT(29),
 714         CS_SELECT_AUTO_DEVICE_ID_CFG            = BIT(30),
 715 };
 716
 717 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
 718 {
 719         u32 val = en ? CS_SELECT_NAND_WP : 0;
 720
 721         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
 722 }
 723
 724 /***********************************************************************
 725  * Flash DMA
 726  ***********************************************************************/
 727
 728 enum flash_dma_reg {
 729         FLASH_DMA_REVISION              = 0x00,
 730         FLASH_DMA_FIRST_DESC            = 0x04,
 731         FLASH_DMA_FIRST_DESC_EXT        = 0x08,
 732         FLASH_DMA_CTRL                  = 0x0c,
 733         FLASH_DMA_MODE                  = 0x10,
 734         FLASH_DMA_STATUS                = 0x14,
 735         FLASH_DMA_INTERRUPT_DESC        = 0x18,
 736         FLASH_DMA_INTERRUPT_DESC_EXT    = 0x1c,
 737         FLASH_DMA_ERROR_STATUS          = 0x20,
 738         FLASH_DMA_CURRENT_DESC          = 0x24,
 739         FLASH_DMA_CURRENT_DESC_EXT      = 0x28,
 740 };
 741
 742 static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
 743 {
 744         return ctrl->flash_dma_base;
 745 }
 746
 747 static inline bool flash_dma_buf_ok(const void *buf)
 748 {
 749         return buf && !is_vmalloc_addr(buf) &&
 750                 likely(IS_ALIGNED((uintptr_t)buf, 4));
 751 }
 752
 753 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
 754                                     u32 val)
 755 {
 756         brcmnand_writel(val, ctrl->flash_dma_base + offs);
 757 }
 758
 759 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
 760 {
 761         return brcmnand_readl(ctrl->flash_dma_base + offs);
 762 }
 763
 764 /* Low-level operation types: command, address, write, or read */
 765 enum brcmnand_llop_type {
 766         LL_OP_CMD,
 767         LL_OP_ADDR,
 768         LL_OP_WR,
 769         LL_OP_RD,
 770 };
 771
 772 /***********************************************************************
 773  * Internal support functions
 774  ***********************************************************************/
 775
 776 static inline bool is_hamming_ecc(struct brcmnand_cfg *cfg)
 777 {
 778         return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
 779                 cfg->ecc_level == 15;
 780 }
 781
 782 /*
 783  * Returns a nand_ecclayout strucutre for the given layout/configuration.
 784  * Returns NULL on failure.
 785  */
 786 static struct nand_ecclayout *brcmnand_create_layout(int ecc_level,
 787                                                      struct brcmnand_host *host)
 788 {
 789         struct brcmnand_cfg *cfg = &host->hwcfg;
 790         int i, j;
 791         struct nand_ecclayout *layout;
 792         int req;
 793         int sectors;
 794         int sas;
 795         int idx1, idx2;
 796
 797         layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
 798         if (!layout)
 799                 return NULL;
 800
 801         sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 802         sas = cfg->spare_area_size << cfg->sector_size_1k;
 803
 804         /* Hamming */
 805         if (is_hamming_ecc(cfg)) {
 806                 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
 807                         /* First sector of each page may have BBI */
 808                         if (i == 0) {
 809                                 layout->oobfree[idx2].offset = i * sas + 1;
 810                                 /* Small-page NAND use byte 6 for BBI */
 811                                 if (cfg->page_size == 512)
 812                                         layout->oobfree[idx2].offset--;
 813                                 layout->oobfree[idx2].length = 5;
 814                         } else {
 815                                 layout->oobfree[idx2].offset = i * sas;
 816                                 layout->oobfree[idx2].length = 6;
 817                         }
 818                         idx2++;
 819                         layout->eccpos[idx1++] = i * sas + 6;
 820                         layout->eccpos[idx1++] = i * sas + 7;
 821                         layout->eccpos[idx1++] = i * sas + 8;
 822                         layout->oobfree[idx2].offset = i * sas + 9;
 823                         layout->oobfree[idx2].length = 7;
 824                         idx2++;
 825                         /* Leave zero-terminated entry for OOBFREE */
 826                         if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
 827                                     idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
 828                                 break;
 829                 }
 830                 goto out;
 831         }
 832
 833         /*
 834          * CONTROLLER_VERSION:
 835          *   < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
 836          *  >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
 837          * But we will just be conservative.
 838          */
 839         req = DIV_ROUND_UP(ecc_level * 14, 8);
 840         if (req >= sas) {
 841                 dev_err(&host->pdev->dev,
 842                         "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
 843                         req, sas);
 844                 return NULL;
 845         }
 846
 847         layout->eccbytes = req * sectors;
 848         for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
 849                 for (j = sas - req; j < sas && idx1 <
 850                                 MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
 851                         layout->eccpos[idx1] = i * sas + j;
 852
 853                 /* First sector of each page may have BBI */
 854                 if (i == 0) {
 855                         if (cfg->page_size == 512 && (sas - req >= 6)) {
 856                                 /* Small-page NAND use byte 6 for BBI */
 857                                 layout->oobfree[idx2].offset = 0;
 858                                 layout->oobfree[idx2].length = 5;
 859                                 idx2++;
 860                                 if (sas - req > 6) {
 861                                         layout->oobfree[idx2].offset = 6;
 862                                         layout->oobfree[idx2].length =
 863                                                 sas - req - 6;
 864                                         idx2++;
 865                                 }
 866                         } else if (sas > req + 1) {
 867                                 layout->oobfree[idx2].offset = i * sas + 1;
 868                                 layout->oobfree[idx2].length = sas - req - 1;
 869                                 idx2++;
 870                         }
 871                 } else if (sas > req) {
 872                         layout->oobfree[idx2].offset = i * sas;
 873                         layout->oobfree[idx2].length = sas - req;
 874                         idx2++;
 875                 }
 876                 /* Leave zero-terminated entry for OOBFREE */
 877                 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
 878                                 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
 879                         break;
 880         }
 881 out:
 882         /* Sum available OOB */
 883         for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE; i++)
 884                 layout->oobavail += layout->oobfree[i].length;
 885         return layout;
 886 }
 887
 888 static struct nand_ecclayout *brcmstb_choose_ecc_layout(
 889                 struct brcmnand_host *host)
 890 {
 891         struct nand_ecclayout *layout;
 892         struct brcmnand_cfg *p = &host->hwcfg;
 893         unsigned int ecc_level = p->ecc_level;
 894
 895         if (p->sector_size_1k)
 896                 ecc_level <<= 1;
 897
 898         layout = brcmnand_create_layout(ecc_level, host);
 899         if (!layout) {
 900                 dev_err(&host->pdev->dev,
 901                                 "no proper ecc_layout for this NAND cfg\n");
 902                 return NULL;
 903         }
 904
 905         return layout;
 906 }
 907
 908 static void brcmnand_wp(struct mtd_info *mtd, int wp)
 909 {
 910         struct nand_chip *chip = mtd->priv;
 911         struct brcmnand_host *host = chip->priv;
 912         struct brcmnand_controller *ctrl = host->ctrl;
 913
 914         if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
 915                 static int old_wp = -1;
 916
 917                 if (old_wp != wp) {
 918                         dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
 919                         old_wp = wp;
 920                 }
 921                 brcmnand_set_wp(ctrl, wp);
 922         }
 923 }
 924
 925 /* Helper functions for reading and writing OOB registers */
 926 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
 927 {
 928         u16 offset0, offset10, reg_offs;
 929
 930         offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
 931         offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
 932
 933         if (offs >= ctrl->max_oob)
 934                 return 0x77;
 935
 936         if (offs >= 16 && offset10)
 937                 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
 938         else
 939                 reg_offs = offset0 + (offs & ~0x03);
 940
 941         return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
 942 }
 943
 944 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
 945                                  u32 data)
 946 {
 947         u16 offset0, offset10, reg_offs;
 948
 949         offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
 950         offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
 951
 952         if (offs >= ctrl->max_oob)
 953                 return;
 954
 955         if (offs >= 16 && offset10)
 956                 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
 957         else
 958                 reg_offs = offset0 + (offs & ~0x03);
 959
 960         nand_writereg(ctrl, reg_offs, data);
 961 }
 962
 963 /*
 964  * read_oob_from_regs - read data from OOB registers
 965  * @ctrl: NAND controller
 966  * @i: sub-page sector index
 967  * @oob: buffer to read to
 968  * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
 969  * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
 970  */
 971 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
 972                               int sas, int sector_1k)
 973 {
 974         int tbytes = sas << sector_1k;
 975         int j;
 976
 977         /* Adjust OOB values for 1K sector size */
 978         if (sector_1k && (i & 0x01))
 979                 tbytes = max(0, tbytes - (int)ctrl->max_oob);
 980         tbytes = min_t(int, tbytes, ctrl->max_oob);
 981
 982         for (j = 0; j < tbytes; j++)
 983                 oob[j] = oob_reg_read(ctrl, j);
 984         return tbytes;
 985 }
 986
 987 /*
 988  * write_oob_to_regs - write data to OOB registers
 989  * @i: sub-page sector index
 990  * @oob: buffer to write from
 991  * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
 992  * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
 993  */
 994 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
 995                              const u8 *oob, int sas, int sector_1k)
 996 {
 997         int tbytes = sas << sector_1k;
 998         int j;
 999
1000         /* Adjust OOB values for 1K sector size */
1001         if (sector_1k && (i & 0x01))
1002                 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1003         tbytes = min_t(int, tbytes, ctrl->max_oob);
1004
1005         for (j = 0; j < tbytes; j += 4)
1006                 oob_reg_write(ctrl, j,
1007                                 (oob[j + 0] << 24) |
1008                                 (oob[j + 1] << 16) |
1009                                 (oob[j + 2] <<  8) |
1010                                 (oob[j + 3] <<  0));
1011         return tbytes;
1012 }
1013
1014 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1015 {
1016         struct brcmnand_controller *ctrl = data;
1017
1018         /* Discard all NAND_CTLRDY interrupts during DMA */
1019         if (ctrl->dma_pending)
1020                 return IRQ_HANDLED;
1021
1022         complete(&ctrl->done);
1023         return IRQ_HANDLED;
1024 }
1025
1026 /* Handle SoC-specific interrupt hardware */
1027 static irqreturn_t brcmnand_irq(int irq, void *data)
1028 {
1029         struct brcmnand_controller *ctrl = data;
1030
1031         if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1032                 return brcmnand_ctlrdy_irq(irq, data);
1033
1034         return IRQ_NONE;
1035 }
1036
1037 static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1038 {
1039         struct brcmnand_controller *ctrl = data;
1040
1041         complete(&ctrl->dma_done);
1042
1043         return IRQ_HANDLED;
1044 }
1045
1046 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1047 {
1048         struct brcmnand_controller *ctrl = host->ctrl;
1049         u32 intfc;
1050
1051         dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
1052                 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
1053         BUG_ON(ctrl->cmd_pending != 0);
1054         ctrl->cmd_pending = cmd;
1055
1056         intfc = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1057         BUG_ON(!(intfc & INTFC_CTLR_READY));
1058
1059         mb(); /* flush previous writes */
1060         brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1061                            cmd << brcmnand_cmd_shift(ctrl));
1062 }
1063
1064 /***********************************************************************
1065  * NAND MTD API: read/program/erase
1066  ***********************************************************************/
1067
1068 static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1069         unsigned int ctrl)
1070 {
1071         /* intentionally left blank */
1072 }
1073
1074 static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1075 {
1076         struct nand_chip *chip = mtd->priv;
1077         struct brcmnand_host *host = chip->priv;
1078         struct brcmnand_controller *ctrl = host->ctrl;
1079         unsigned long timeo = msecs_to_jiffies(100);
1080
1081         dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1082         if (ctrl->cmd_pending &&
1083                         wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1084                 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1085                                         >> brcmnand_cmd_shift(ctrl);
1086
1087                 dev_err_ratelimited(ctrl->dev,
1088                         "timeout waiting for command %#02x\n", cmd);
1089                 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1090                         brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1091         }
1092         ctrl->cmd_pending = 0;
1093         return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1094                                  INTFC_FLASH_STATUS;
1095 }
1096
1097 enum {
1098         LLOP_RE                         = BIT(16),
1099         LLOP_WE                         = BIT(17),
1100         LLOP_ALE                        = BIT(18),
1101         LLOP_CLE                        = BIT(19),
1102         LLOP_RETURN_IDLE                = BIT(31),
1103
1104         LLOP_DATA_MASK                  = GENMASK(15, 0),
1105 };
1106
1107 static int brcmnand_low_level_op(struct brcmnand_host *host,
1108                                  enum brcmnand_llop_type type, u32 data,
1109                                  bool last_op)
1110 {
1111         struct mtd_info *mtd = &host->mtd;
1112         struct nand_chip *chip = &host->chip;
1113         struct brcmnand_controller *ctrl = host->ctrl;
1114         u32 tmp;
1115
1116         tmp = data & LLOP_DATA_MASK;
1117         switch (type) {
1118         case LL_OP_CMD:
1119                 tmp |= LLOP_WE | LLOP_CLE;
1120                 break;
1121         case LL_OP_ADDR:
1122                 /* WE | ALE */
1123                 tmp |= LLOP_WE | LLOP_ALE;
1124                 break;
1125         case LL_OP_WR:
1126                 /* WE */
1127                 tmp |= LLOP_WE;
1128                 break;
1129         case LL_OP_RD:
1130                 /* RE */
1131                 tmp |= LLOP_RE;
1132                 break;
1133         }
1134         if (last_op)
1135                 /* RETURN_IDLE */
1136                 tmp |= LLOP_RETURN_IDLE;
1137
1138         dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1139
1140         brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1141         (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1142
1143         brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1144         return brcmnand_waitfunc(mtd, chip);
1145 }
1146
1147 static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1148                              int column, int page_addr)
1149 {
1150         struct nand_chip *chip = mtd->priv;
1151         struct brcmnand_host *host = chip->priv;
1152         struct brcmnand_controller *ctrl = host->ctrl;
1153         u64 addr = (u64)page_addr << chip->page_shift;
1154         int native_cmd = 0;
1155
1156         if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1157                         command == NAND_CMD_RNDOUT)
1158                 addr = (u64)column;
1159         /* Avoid propagating a negative, don't-care address */
1160         else if (page_addr < 0)
1161                 addr = 0;
1162
1163         dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1164                 (unsigned long long)addr);
1165
1166         host->last_cmd = command;
1167         host->last_byte = 0;
1168         host->last_addr = addr;
1169
1170         switch (command) {
1171         case NAND_CMD_RESET:
1172                 native_cmd = CMD_FLASH_RESET;
1173                 break;
1174         case NAND_CMD_STATUS:
1175                 native_cmd = CMD_STATUS_READ;
1176                 break;
1177         case NAND_CMD_READID:
1178                 native_cmd = CMD_DEVICE_ID_READ;
1179                 break;
1180         case NAND_CMD_READOOB:
1181                 native_cmd = CMD_SPARE_AREA_READ;
1182                 break;
1183         case NAND_CMD_ERASE1:
1184                 native_cmd = CMD_BLOCK_ERASE;
1185                 brcmnand_wp(mtd, 0);
1186                 break;
1187         case NAND_CMD_PARAM:
1188                 native_cmd = CMD_PARAMETER_READ;
1189                 break;
1190         case NAND_CMD_SET_FEATURES:
1191         case NAND_CMD_GET_FEATURES:
1192                 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1193                 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1194                 break;
1195         case NAND_CMD_RNDOUT:
1196                 native_cmd = CMD_PARAMETER_CHANGE_COL;
1197                 addr &= ~((u64)(FC_BYTES - 1));
1198                 /*
1199                  * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1200                  * NB: hwcfg.sector_size_1k may not be initialized yet
1201                  */
1202                 if (brcmnand_get_sector_size_1k(host)) {
1203                         host->hwcfg.sector_size_1k =
1204                                 brcmnand_get_sector_size_1k(host);
1205                         brcmnand_set_sector_size_1k(host, 0);
1206                 }
1207                 break;
1208         }
1209
1210         if (!native_cmd)
1211                 return;
1212
1213         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1214                 (host->cs << 16) | ((addr >> 32) & 0xffff));
1215         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1216         brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1217         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1218
1219         brcmnand_send_cmd(host, native_cmd);
1220         brcmnand_waitfunc(mtd, chip);
1221
1222         if (native_cmd == CMD_PARAMETER_READ ||
1223                         native_cmd == CMD_PARAMETER_CHANGE_COL) {
1224                 int i;
1225
1226                 brcmnand_soc_data_bus_prepare(ctrl->soc);
1227
1228                 /*
1229                  * Must cache the FLASH_CACHE now, since changes in
1230                  * SECTOR_SIZE_1K may invalidate it
1231                  */
1232                 for (i = 0; i < FC_WORDS; i++)
1233                         ctrl->flash_cache[i] = brcmnand_read_fc(ctrl, i);
1234
1235                 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1236
1237                 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1238                 if (host->hwcfg.sector_size_1k)
1239                         brcmnand_set_sector_size_1k(host,
1240                                                     host->hwcfg.sector_size_1k);
1241         }
1242
1243         /* Re-enable protection is necessary only after erase */
1244         if (command == NAND_CMD_ERASE1)
1245                 brcmnand_wp(mtd, 1);
1246 }
1247
1248 static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1249 {
1250         struct nand_chip *chip = mtd->priv;
1251         struct brcmnand_host *host = chip->priv;
1252         struct brcmnand_controller *ctrl = host->ctrl;
1253         uint8_t ret = 0;
1254         int addr, offs;
1255
1256         switch (host->last_cmd) {
1257         case NAND_CMD_READID:
1258                 if (host->last_byte < 4)
1259                         ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1260                                 (24 - (host->last_byte << 3));
1261                 else if (host->last_byte < 8)
1262                         ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1263                                 (56 - (host->last_byte << 3));
1264                 break;
1265
1266         case NAND_CMD_READOOB:
1267                 ret = oob_reg_read(ctrl, host->last_byte);
1268                 break;
1269
1270         case NAND_CMD_STATUS:
1271                 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1272                                         INTFC_FLASH_STATUS;
1273                 if (wp_on) /* hide WP status */
1274                         ret |= NAND_STATUS_WP;
1275                 break;
1276
1277         case NAND_CMD_PARAM:
1278         case NAND_CMD_RNDOUT:
1279                 addr = host->last_addr + host->last_byte;
1280                 offs = addr & (FC_BYTES - 1);
1281
1282                 /* At FC_BYTES boundary, switch to next column */
1283                 if (host->last_byte > 0 && offs == 0)
1284                         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
1285
1286                 ret = ctrl->flash_cache[offs >> 2] >>
1287                                         (24 - ((offs & 0x03) << 3));
1288                 break;
1289         case NAND_CMD_GET_FEATURES:
1290                 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1291                         ret = 0;
1292                 } else {
1293                         bool last = host->last_byte ==
1294                                 ONFI_SUBFEATURE_PARAM_LEN - 1;
1295                         brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1296                         ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1297                 }
1298         }
1299
1300         dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1301         host->last_byte++;
1302
1303         return ret;
1304 }
1305
1306 static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1307 {
1308         int i;
1309
1310         for (i = 0; i < len; i++, buf++)
1311                 *buf = brcmnand_read_byte(mtd);
1312 }
1313
1314 static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1315                                    int len)
1316 {
1317         int i;
1318         struct nand_chip *chip = mtd->priv;
1319         struct brcmnand_host *host = chip->priv;
1320
1321         switch (host->last_cmd) {
1322         case NAND_CMD_SET_FEATURES:
1323                 for (i = 0; i < len; i++)
1324                         brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1325                                                   (i + 1) == len);
1326                 break;
1327         default:
1328                 BUG();
1329                 break;
1330         }
1331 }
1332
1333 /**
1334  * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1335  * following ahead of time:
1336  *  - Is this descriptor the beginning or end of a linked list?
1337  *  - What is the (DMA) address of the next descriptor in the linked list?
1338  */
1339 static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1340                                   struct brcm_nand_dma_desc *desc, u64 addr,
1341                                   dma_addr_t buf, u32 len, u8 dma_cmd,
1342                                   bool begin, bool end,
1343                                   dma_addr_t next_desc)
1344 {
1345         memset(desc, 0, sizeof(*desc));
1346         /* Descriptors are written in native byte order (wordwise) */
1347         desc->next_desc = lower_32_bits(next_desc);
1348         desc->next_desc_ext = upper_32_bits(next_desc);
1349         desc->cmd_irq = (dma_cmd << 24) |
1350                 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1351                 (!!begin) | ((!!end) << 1); /* head, tail */
1352 #ifdef CONFIG_CPU_BIG_ENDIAN
1353         desc->cmd_irq |= 0x01 << 12;
1354 #endif
1355         desc->dram_addr = lower_32_bits(buf);
1356         desc->dram_addr_ext = upper_32_bits(buf);
1357         desc->tfr_len = len;
1358         desc->total_len = len;
1359         desc->flash_addr = lower_32_bits(addr);
1360         desc->flash_addr_ext = upper_32_bits(addr);
1361         desc->cs = host->cs;
1362         desc->status_valid = 0x01;
1363         return 0;
1364 }
1365
1366 /**
1367  * Kick the FLASH_DMA engine, with a given DMA descriptor
1368  */
1369 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1370 {
1371         struct brcmnand_controller *ctrl = host->ctrl;
1372         unsigned long timeo = msecs_to_jiffies(100);
1373
1374         flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1375         (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1376         flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1377         (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1378
1379         /* Start FLASH_DMA engine */
1380         ctrl->dma_pending = true;
1381         mb(); /* flush previous writes */
1382         flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1383
1384         if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1385                 dev_err(ctrl->dev,
1386                                 "timeout waiting for DMA; status %#x, error status %#x\n",
1387                                 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1388                                 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1389         }
1390         ctrl->dma_pending = false;
1391         flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1392 }
1393
1394 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1395                               u32 len, u8 dma_cmd)
1396 {
1397         struct brcmnand_controller *ctrl = host->ctrl;
1398         dma_addr_t buf_pa;
1399         int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1400
1401         buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1402         if (dma_mapping_error(ctrl->dev, buf_pa)) {
1403                 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1404                 return -ENOMEM;
1405         }
1406
1407         brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1408                                    dma_cmd, true, true, 0);
1409
1410         brcmnand_dma_run(host, ctrl->dma_pa);
1411
1412         dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1413
1414         if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1415                 return -EBADMSG;
1416         else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1417                 return -EUCLEAN;
1418
1419         return 0;
1420 }
1421
1422 /*
1423  * Assumes proper CS is already set
1424  */
1425 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1426                                 u64 addr, unsigned int trans, u32 *buf,
1427                                 u8 *oob, u64 *err_addr)
1428 {
1429         struct brcmnand_host *host = chip->priv;
1430         struct brcmnand_controller *ctrl = host->ctrl;
1431         int i, j, ret = 0;
1432
1433         /* Clear error addresses */
1434         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1435         brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
1436
1437         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1438                         (host->cs << 16) | ((addr >> 32) & 0xffff));
1439         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1440
1441         for (i = 0; i < trans; i++, addr += FC_BYTES) {
1442                 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1443                                    lower_32_bits(addr));
1444                 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1445                 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1446                 brcmnand_send_cmd(host, CMD_PAGE_READ);
1447                 brcmnand_waitfunc(mtd, chip);
1448
1449                 if (likely(buf)) {
1450                         brcmnand_soc_data_bus_prepare(ctrl->soc);
1451
1452                         for (j = 0; j < FC_WORDS; j++, buf++)
1453                                 *buf = brcmnand_read_fc(ctrl, j);
1454
1455                         brcmnand_soc_data_bus_unprepare(ctrl->soc);
1456                 }
1457
1458                 if (oob)
1459                         oob += read_oob_from_regs(ctrl, i, oob,
1460                                         mtd->oobsize / trans,
1461                                         host->hwcfg.sector_size_1k);
1462
1463                 if (!ret) {
1464                         *err_addr = brcmnand_read_reg(ctrl,
1465                                         BRCMNAND_UNCORR_ADDR) |
1466                                 ((u64)(brcmnand_read_reg(ctrl,
1467                                                 BRCMNAND_UNCORR_EXT_ADDR)
1468                                         & 0xffff) << 32);
1469                         if (*err_addr)
1470                                 ret = -EBADMSG;
1471                 }
1472
1473                 if (!ret) {
1474                         *err_addr = brcmnand_read_reg(ctrl,
1475                                         BRCMNAND_CORR_ADDR) |
1476                                 ((u64)(brcmnand_read_reg(ctrl,
1477                                                 BRCMNAND_CORR_EXT_ADDR)
1478                                         & 0xffff) << 32);
1479                         if (*err_addr)
1480                                 ret = -EUCLEAN;
1481                 }
1482         }
1483
1484         return ret;
1485 }
1486
1487 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1488                          u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1489 {
1490         struct brcmnand_host *host = chip->priv;
1491         struct brcmnand_controller *ctrl = host->ctrl;
1492         u64 err_addr = 0;
1493         int err;
1494
1495         dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1496
1497         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1498
1499         if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1500                 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1501                                              CMD_PAGE_READ);
1502                 if (err) {
1503                         if (mtd_is_bitflip_or_eccerr(err))
1504                                 err_addr = addr;
1505                         else
1506                                 return -EIO;
1507                 }
1508         } else {
1509                 if (oob)
1510                         memset(oob, 0x99, mtd->oobsize);
1511
1512                 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1513                                                oob, &err_addr);
1514         }
1515
1516         if (mtd_is_eccerr(err)) {
1517                 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1518                         (unsigned long long)err_addr);
1519                 mtd->ecc_stats.failed++;
1520                 /* NAND layer expects zero on ECC errors */
1521                 return 0;
1522         }
1523
1524         if (mtd_is_bitflip(err)) {
1525                 unsigned int corrected = brcmnand_count_corrected(ctrl);
1526
1527                 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1528                         (unsigned long long)err_addr);
1529                 mtd->ecc_stats.corrected += corrected;
1530                 /* Always exceed the software-imposed threshold */
1531                 return max(mtd->bitflip_threshold, corrected);
1532         }
1533
1534         return 0;
1535 }
1536
1537 static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1538                               uint8_t *buf, int oob_required, int page)
1539 {
1540         struct brcmnand_host *host = chip->priv;
1541         u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1542
1543         return brcmnand_read(mtd, chip, host->last_addr,
1544                         mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1545 }
1546
1547 static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1548                                   uint8_t *buf, int oob_required, int page)
1549 {
1550         struct brcmnand_host *host = chip->priv;
1551         u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1552         int ret;
1553
1554         brcmnand_set_ecc_enabled(host, 0);
1555         ret = brcmnand_read(mtd, chip, host->last_addr,
1556                         mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1557         brcmnand_set_ecc_enabled(host, 1);
1558         return ret;
1559 }
1560
1561 static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1562                              int page)
1563 {
1564         return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1565                         mtd->writesize >> FC_SHIFT,
1566                         NULL, (u8 *)chip->oob_poi);
1567 }
1568
1569 static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1570                                  int page)
1571 {
1572         struct brcmnand_host *host = chip->priv;
1573
1574         brcmnand_set_ecc_enabled(host, 0);
1575         brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1576                 mtd->writesize >> FC_SHIFT,
1577                 NULL, (u8 *)chip->oob_poi);
1578         brcmnand_set_ecc_enabled(host, 1);
1579         return 0;
1580 }
1581
1582 static int brcmnand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1583                                  uint32_t data_offs, uint32_t readlen,
1584                                  uint8_t *bufpoi, int page)
1585 {
1586         struct brcmnand_host *host = chip->priv;
1587
1588         return brcmnand_read(mtd, chip, host->last_addr + data_offs,
1589                         readlen >> FC_SHIFT, (u32 *)bufpoi, NULL);
1590 }
1591
1592 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1593                           u64 addr, const u32 *buf, u8 *oob)
1594 {
1595         struct brcmnand_host *host = chip->priv;
1596         struct brcmnand_controller *ctrl = host->ctrl;
1597         unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1598         int status, ret = 0;
1599
1600         dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1601
1602         if (unlikely((unsigned long)buf & 0x03)) {
1603                 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
1604                 buf = (u32 *)((unsigned long)buf & ~0x03);
1605         }
1606
1607         brcmnand_wp(mtd, 0);
1608
1609         for (i = 0; i < ctrl->max_oob; i += 4)
1610                 oob_reg_write(ctrl, i, 0xffffffff);
1611
1612         if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1613                 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1614                                         mtd->writesize, CMD_PROGRAM_PAGE))
1615                         ret = -EIO;
1616                 goto out;
1617         }
1618
1619         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1620                         (host->cs << 16) | ((addr >> 32) & 0xffff));
1621         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1622
1623         for (i = 0; i < trans; i++, addr += FC_BYTES) {
1624                 /* full address MUST be set before populating FC */
1625                 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1626                                    lower_32_bits(addr));
1627                 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1628
1629                 if (buf) {
1630                         brcmnand_soc_data_bus_prepare(ctrl->soc);
1631
1632                         for (j = 0; j < FC_WORDS; j++, buf++)
1633                                 brcmnand_write_fc(ctrl, j, *buf);
1634
1635                         brcmnand_soc_data_bus_unprepare(ctrl->soc);
1636                 } else if (oob) {
1637                         for (j = 0; j < FC_WORDS; j++)
1638                                 brcmnand_write_fc(ctrl, j, 0xffffffff);
1639                 }
1640
1641                 if (oob) {
1642                         oob += write_oob_to_regs(ctrl, i, oob,
1643                                         mtd->oobsize / trans,
1644                                         host->hwcfg.sector_size_1k);
1645                 }
1646
1647                 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1648                 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1649                 status = brcmnand_waitfunc(mtd, chip);
1650
1651                 if (status & NAND_STATUS_FAIL) {
1652                         dev_info(ctrl->dev, "program failed at %llx\n",
1653                                 (unsigned long long)addr);
1654                         ret = -EIO;
1655                         goto out;
1656                 }
1657         }
1658 out:
1659         brcmnand_wp(mtd, 1);
1660         return ret;
1661 }
1662
1663 static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1664                                const uint8_t *buf, int oob_required, int page)
1665 {
1666         struct brcmnand_host *host = chip->priv;
1667         void *oob = oob_required ? chip->oob_poi : NULL;
1668
1669         brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1670         return 0;
1671 }
1672
1673 static int brcmnand_write_page_raw(struct mtd_info *mtd,
1674                                    struct nand_chip *chip, const uint8_t *buf,
1675                                    int oob_required, int page)
1676 {
1677         struct brcmnand_host *host = chip->priv;
1678         void *oob = oob_required ? chip->oob_poi : NULL;
1679
1680         brcmnand_set_ecc_enabled(host, 0);
1681         brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1682         brcmnand_set_ecc_enabled(host, 1);
1683         return 0;
1684 }
1685
1686 static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1687                                   int page)
1688 {
1689         return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1690                                   NULL, chip->oob_poi);
1691 }
1692
1693 static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1694                                   int page)
1695 {
1696         struct brcmnand_host *host = chip->priv;
1697         int ret;
1698
1699         brcmnand_set_ecc_enabled(host, 0);
1700         ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1701                                  (u8 *)chip->oob_poi);
1702         brcmnand_set_ecc_enabled(host, 1);
1703
1704         return ret;
1705 }
1706
1707 /***********************************************************************
1708  * Per-CS setup (1 NAND device)
1709  ***********************************************************************/
1710
1711 static int brcmnand_set_cfg(struct brcmnand_host *host,
1712                             struct brcmnand_cfg *cfg)
1713 {
1714         struct brcmnand_controller *ctrl = host->ctrl;
1715         struct nand_chip *chip = &host->chip;
1716         u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1717         u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1718                         BRCMNAND_CS_CFG_EXT);
1719         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1720                         BRCMNAND_CS_ACC_CONTROL);
1721         u8 block_size = 0, page_size = 0, device_size = 0;
1722         u32 tmp;
1723
1724         if (ctrl->block_sizes) {
1725                 int i, found;
1726
1727                 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
1728                         if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
1729                                 block_size = i;
1730                                 found = 1;
1731                         }
1732                 if (!found) {
1733                         dev_warn(ctrl->dev, "invalid block size %u\n",
1734                                         cfg->block_size);
1735                         return -EINVAL;
1736                 }
1737         } else {
1738                 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
1739         }
1740
1741         if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
1742                                 cfg->block_size > ctrl->max_block_size)) {
1743                 dev_warn(ctrl->dev, "invalid block size %u\n",
1744                                 cfg->block_size);
1745                 block_size = 0;
1746         }
1747
1748         if (ctrl->page_sizes) {
1749                 int i, found;
1750
1751                 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
1752                         if (ctrl->page_sizes[i] == cfg->page_size) {
1753                                 page_size = i;
1754                                 found = 1;
1755                         }
1756                 if (!found) {
1757                         dev_warn(ctrl->dev, "invalid page size %u\n",
1758                                         cfg->page_size);
1759                         return -EINVAL;
1760                 }
1761         } else {
1762                 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
1763         }
1764
1765         if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
1766                                 cfg->page_size > ctrl->max_page_size)) {
1767                 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
1768                 return -EINVAL;
1769         }
1770
1771         if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
1772                 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
1773                         (unsigned long long)cfg->device_size);
1774                 return -EINVAL;
1775         }
1776         device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
1777
1778         tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
1779                 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
1780                 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
1781                 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
1782                 (device_size << CFG_DEVICE_SIZE_SHIFT);
1783         if (cfg_offs == cfg_ext_offs) {
1784                 tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
1785                        (block_size << CFG_BLK_SIZE_SHIFT);
1786                 nand_writereg(ctrl, cfg_offs, tmp);
1787         } else {
1788                 nand_writereg(ctrl, cfg_offs, tmp);
1789                 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
1790                       (block_size << CFG_EXT_BLK_SIZE_SHIFT);
1791                 nand_writereg(ctrl, cfg_ext_offs, tmp);
1792         }
1793
1794         tmp = nand_readreg(ctrl, acc_control_offs);
1795         tmp &= ~brcmnand_ecc_level_mask(ctrl);
1796         tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
1797         tmp &= ~brcmnand_spare_area_mask(ctrl);
1798         tmp |= cfg->spare_area_size;
1799         nand_writereg(ctrl, acc_control_offs, tmp);
1800
1801         brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
1802
1803         /* threshold = ceil(BCH-level * 0.75) */
1804         brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
1805
1806         return 0;
1807 }
1808
1809 static void brcmnand_print_cfg(char *buf, struct brcmnand_cfg *cfg)
1810 {
1811         buf += sprintf(buf,
1812                 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
1813                 (unsigned long long)cfg->device_size >> 20,
1814                 cfg->block_size >> 10,
1815                 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
1816                 cfg->page_size >= 1024 ? "KiB" : "B",
1817                 cfg->spare_area_size, cfg->device_width);
1818
1819         /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
1820         if (is_hamming_ecc(cfg))
1821                 sprintf(buf, ", Hamming ECC");
1822         else if (cfg->sector_size_1k)
1823                 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
1824         else
1825                 sprintf(buf, ", BCH-%u", cfg->ecc_level);
1826 }
1827
1828 /*
1829  * Minimum number of bytes to address a page. Calculated as:
1830  *     roundup(log2(size / page-size) / 8)
1831  *
1832  * NB: the following does not "round up" for non-power-of-2 'size'; but this is
1833  *     OK because many other things will break if 'size' is irregular...
1834  */
1835 static inline int get_blk_adr_bytes(u64 size, u32 writesize)
1836 {
1837         return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
1838 }
1839
1840 static int brcmnand_setup_dev(struct brcmnand_host *host)
1841 {
1842         struct mtd_info *mtd = &host->mtd;
1843         struct nand_chip *chip = &host->chip;
1844         struct brcmnand_controller *ctrl = host->ctrl;
1845         struct brcmnand_cfg *cfg = &host->hwcfg;
1846         char msg[128];
1847         u32 offs, tmp, oob_sector;
1848         int ret;
1849
1850         memset(cfg, 0, sizeof(*cfg));
1851
1852         ret = of_property_read_u32(chip->flash_node,
1853                                    "brcm,nand-oob-sector-size",
1854                                    &oob_sector);
1855         if (ret) {
1856                 /* Use detected size */
1857                 cfg->spare_area_size = mtd->oobsize /
1858                                         (mtd->writesize >> FC_SHIFT);
1859         } else {
1860                 cfg->spare_area_size = oob_sector;
1861         }
1862         if (cfg->spare_area_size > ctrl->max_oob)
1863                 cfg->spare_area_size = ctrl->max_oob;
1864         /*
1865          * Set oobsize to be consistent with controller's spare_area_size, as
1866          * the rest is inaccessible.
1867          */
1868         mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
1869
1870         cfg->device_size = mtd->size;
1871         cfg->block_size = mtd->erasesize;
1872         cfg->page_size = mtd->writesize;
1873         cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
1874         cfg->col_adr_bytes = 2;
1875         cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
1876
1877         switch (chip->ecc.size) {
1878         case 512:
1879                 if (chip->ecc.strength == 1) /* Hamming */
1880                         cfg->ecc_level = 15;
1881                 else
1882                         cfg->ecc_level = chip->ecc.strength;
1883                 cfg->sector_size_1k = 0;
1884                 break;
1885         case 1024:
1886                 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
1887                         dev_err(ctrl->dev, "1KB sectors not supported\n");
1888                         return -EINVAL;
1889                 }
1890                 if (chip->ecc.strength & 0x1) {
1891                         dev_err(ctrl->dev,
1892                                 "odd ECC not supported with 1KB sectors\n");
1893                         return -EINVAL;
1894                 }
1895
1896                 cfg->ecc_level = chip->ecc.strength >> 1;
1897                 cfg->sector_size_1k = 1;
1898                 break;
1899         default:
1900                 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
1901                         chip->ecc.size);
1902                 return -EINVAL;
1903         }
1904
1905         cfg->ful_adr_bytes = cfg->blk_adr_bytes;
1906         if (mtd->writesize > 512)
1907                 cfg->ful_adr_bytes += cfg->col_adr_bytes;
1908         else
1909                 cfg->ful_adr_bytes += 1;
1910
1911         ret = brcmnand_set_cfg(host, cfg);
1912         if (ret)
1913                 return ret;
1914
1915         brcmnand_set_ecc_enabled(host, 1);
1916
1917         brcmnand_print_cfg(msg, cfg);
1918         dev_info(ctrl->dev, "detected %s\n", msg);
1919
1920         /* Configure ACC_CONTROL */
1921         offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
1922         tmp = nand_readreg(ctrl, offs);
1923         tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
1924         tmp &= ~ACC_CONTROL_RD_ERASED;
1925         tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
1926         if (ctrl->features & BRCMNAND_HAS_PREFETCH)
1927                 tmp &= ~ACC_CONTROL_PREFETCH;
1928
1929         nand_writereg(ctrl, offs, tmp);
1930
1931         return 0;
1932 }
1933
1934 static int brcmnand_init_cs(struct brcmnand_host *host)
1935 {
1936         struct brcmnand_controller *ctrl = host->ctrl;
1937         struct device_node *dn = host->of_node;
1938         struct platform_device *pdev = host->pdev;
1939         struct mtd_info *mtd;
1940         struct nand_chip *chip;
1941         int ret;
1942         u16 cfg_offs;
1943         struct mtd_part_parser_data ppdata = { .of_node = dn };
1944
1945         ret = of_property_read_u32(dn, "reg", &host->cs);
1946         if (ret) {
1947                 dev_err(&pdev->dev, "can't get chip-select\n");
1948                 return -ENXIO;
1949         }
1950
1951         mtd = &host->mtd;
1952         chip = &host->chip;
1953
1954         chip->flash_node = dn;
1955         chip->priv = host;
1956         mtd->priv = chip;
1957         mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
1958                                    host->cs);
1959         mtd->owner = THIS_MODULE;
1960         mtd->dev.parent = &pdev->dev;
1961
1962         chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
1963         chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
1964
1965         chip->cmd_ctrl = brcmnand_cmd_ctrl;
1966         chip->cmdfunc = brcmnand_cmdfunc;
1967         chip->waitfunc = brcmnand_waitfunc;
1968         chip->read_byte = brcmnand_read_byte;
1969         chip->read_buf = brcmnand_read_buf;
1970         chip->write_buf = brcmnand_write_buf;
1971
1972         chip->ecc.mode = NAND_ECC_HW;
1973         chip->ecc.read_page = brcmnand_read_page;
1974         chip->ecc.read_subpage = brcmnand_read_subpage;
1975         chip->ecc.write_page = brcmnand_write_page;
1976         chip->ecc.read_page_raw = brcmnand_read_page_raw;
1977         chip->ecc.write_page_raw = brcmnand_write_page_raw;
1978         chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
1979         chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
1980         chip->ecc.read_oob = brcmnand_read_oob;
1981         chip->ecc.write_oob = brcmnand_write_oob;
1982
1983         chip->controller = &ctrl->controller;
1984
1985         /*
1986          * The bootloader might have configured 16bit mode but
1987          * NAND READID command only works in 8bit mode. We force
1988          * 8bit mode here to ensure that NAND READID commands works.
1989          */
1990         cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1991         nand_writereg(ctrl, cfg_offs,
1992                       nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
1993
1994         if (nand_scan_ident(mtd, 1, NULL))
1995                 return -ENXIO;
1996
1997         chip->options |= NAND_NO_SUBPAGE_WRITE;
1998         /*
1999          * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
2000          * to/from, and have nand_base pass us a bounce buffer instead, as
2001          * needed.
2002          */
2003         chip->options |= NAND_USE_BOUNCE_BUFFER;
2004
2005         if (of_get_nand_on_flash_bbt(dn))
2006                 chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
2007
2008         if (brcmnand_setup_dev(host))
2009                 return -ENXIO;
2010
2011         chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2012         /* only use our internal HW threshold */
2013         mtd->bitflip_threshold = 1;
2014
2015         chip->ecc.layout = brcmstb_choose_ecc_layout(host);
2016         if (!chip->ecc.layout)
2017                 return -ENXIO;
2018
2019         if (nand_scan_tail(mtd))
2020                 return -ENXIO;
2021
2022         return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
2023 }
2024
2025 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
2026                                             int restore)
2027 {
2028         struct brcmnand_controller *ctrl = host->ctrl;
2029         u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2030         u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2031                         BRCMNAND_CS_CFG_EXT);
2032         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2033                         BRCMNAND_CS_ACC_CONTROL);
2034         u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2035         u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2036
2037         if (restore) {
2038                 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2039                 if (cfg_offs != cfg_ext_offs)
2040                         nand_writereg(ctrl, cfg_ext_offs,
2041                                       host->hwcfg.config_ext);
2042                 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2043                 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2044                 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2045         } else {
2046                 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2047                 if (cfg_offs != cfg_ext_offs)
2048                         host->hwcfg.config_ext =
2049                                 nand_readreg(ctrl, cfg_ext_offs);
2050                 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2051                 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2052                 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2053         }
2054 }
2055
2056 static int brcmnand_suspend(struct device *dev)
2057 {
2058         struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2059         struct brcmnand_host *host;
2060
2061         list_for_each_entry(host, &ctrl->host_list, node)
2062                 brcmnand_save_restore_cs_config(host, 0);
2063
2064         ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2065         ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2066         ctrl->corr_stat_threshold =
2067                 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2068
2069         if (has_flash_dma(ctrl))
2070                 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2071
2072         return 0;
2073 }
2074
2075 static int brcmnand_resume(struct device *dev)
2076 {
2077         struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2078         struct brcmnand_host *host;
2079
2080         if (has_flash_dma(ctrl)) {
2081                 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2082                 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2083         }
2084
2085         brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2086         brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2087         brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2088                         ctrl->corr_stat_threshold);
2089         if (ctrl->soc) {
2090                 /* Clear/re-enable interrupt */
2091                 ctrl->soc->ctlrdy_ack(ctrl->soc);
2092                 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2093         }
2094
2095         list_for_each_entry(host, &ctrl->host_list, node) {
2096                 struct mtd_info *mtd = &host->mtd;
2097                 struct nand_chip *chip = mtd->priv;
2098
2099                 brcmnand_save_restore_cs_config(host, 1);
2100
2101                 /* Reset the chip, required by some chips after power-up */
2102                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2103         }
2104
2105         return 0;
2106 }
2107
2108 const struct dev_pm_ops brcmnand_pm_ops = {
2109         .suspend                = brcmnand_suspend,
2110         .resume                 = brcmnand_resume,
2111 };
2112 EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2113
2114 static const struct of_device_id brcmnand_of_match[] = {
2115         { .compatible = "brcm,brcmnand-v4.0" },
2116         { .compatible = "brcm,brcmnand-v5.0" },
2117         { .compatible = "brcm,brcmnand-v6.0" },
2118         { .compatible = "brcm,brcmnand-v6.1" },
2119         { .compatible = "brcm,brcmnand-v7.0" },
2120         { .compatible = "brcm,brcmnand-v7.1" },
2121         {},
2122 };
2123 MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2124
2125 /***********************************************************************
2126  * Platform driver setup (per controller)
2127  ***********************************************************************/
2128
2129 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2130 {
2131         struct device *dev = &pdev->dev;
2132         struct device_node *dn = dev->of_node, *child;
2133         struct brcmnand_controller *ctrl;
2134         struct resource *res;
2135         int ret;
2136
2137         /* We only support device-tree instantiation */
2138         if (!dn)
2139                 return -ENODEV;
2140
2141         if (!of_match_node(brcmnand_of_match, dn))
2142                 return -ENODEV;
2143
2144         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2145         if (!ctrl)
2146                 return -ENOMEM;
2147
2148         dev_set_drvdata(dev, ctrl);
2149         ctrl->dev = dev;
2150
2151         init_completion(&ctrl->done);
2152         init_completion(&ctrl->dma_done);
2153         spin_lock_init(&ctrl->controller.lock);
2154         init_waitqueue_head(&ctrl->controller.wq);
2155         INIT_LIST_HEAD(&ctrl->host_list);
2156
2157         /* NAND register range */
2158         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2159         ctrl->nand_base = devm_ioremap_resource(dev, res);
2160         if (IS_ERR(ctrl->nand_base))
2161                 return PTR_ERR(ctrl->nand_base);
2162
2163         /* Initialize NAND revision */
2164         ret = brcmnand_revision_init(ctrl);
2165         if (ret)
2166                 return ret;
2167
2168         /*
2169          * Most chips have this cache at a fixed offset within 'nand' block.
2170          * Some must specify this region separately.
2171          */
2172         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2173         if (res) {
2174                 ctrl->nand_fc = devm_ioremap_resource(dev, res);
2175                 if (IS_ERR(ctrl->nand_fc))
2176                         return PTR_ERR(ctrl->nand_fc);
2177         } else {
2178                 ctrl->nand_fc = ctrl->nand_base +
2179                                 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2180         }
2181
2182         /* FLASH_DMA */
2183         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2184         if (res) {
2185                 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2186                 if (IS_ERR(ctrl->flash_dma_base))
2187                         return PTR_ERR(ctrl->flash_dma_base);
2188
2189                 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2190                 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2191
2192                 /* Allocate descriptor(s) */
2193                 ctrl->dma_desc = dmam_alloc_coherent(dev,
2194                                                      sizeof(*ctrl->dma_desc),
2195                                                      &ctrl->dma_pa, GFP_KERNEL);
2196                 if (!ctrl->dma_desc)
2197                         return -ENOMEM;
2198
2199                 ctrl->dma_irq = platform_get_irq(pdev, 1);
2200                 if ((int)ctrl->dma_irq < 0) {
2201                         dev_err(dev, "missing FLASH_DMA IRQ\n");
2202                         return -ENODEV;
2203                 }
2204
2205                 ret = devm_request_irq(dev, ctrl->dma_irq,
2206                                 brcmnand_dma_irq, 0, DRV_NAME,
2207                                 ctrl);
2208                 if (ret < 0) {
2209                         dev_err(dev, "can't allocate IRQ %d: error %d\n",
2210                                         ctrl->dma_irq, ret);
2211                         return ret;
2212                 }
2213
2214                 dev_info(dev, "enabling FLASH_DMA\n");
2215         }
2216
2217         /* Disable automatic device ID config, direct addressing */
2218         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2219                          CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2220         /* Disable XOR addressing */
2221         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2222
2223         if (ctrl->features & BRCMNAND_HAS_WP) {
2224                 /* Permanently disable write protection */
2225                 if (wp_on == 2)
2226                         brcmnand_set_wp(ctrl, false);
2227         } else {
2228                 wp_on = 0;
2229         }
2230
2231         /* IRQ */
2232         ctrl->irq = platform_get_irq(pdev, 0);
2233         if ((int)ctrl->irq < 0) {
2234                 dev_err(dev, "no IRQ defined\n");
2235                 return -ENODEV;
2236         }
2237
2238         /*
2239          * Some SoCs integrate this controller (e.g., its interrupt bits) in
2240          * interesting ways
2241          */
2242         if (soc) {
2243                 ctrl->soc = soc;
2244
2245                 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2246                                        DRV_NAME, ctrl);
2247
2248                 /* Enable interrupt */
2249                 ctrl->soc->ctlrdy_ack(ctrl->soc);
2250                 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2251         } else {
2252                 /* Use standard interrupt infrastructure */
2253                 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2254                                        DRV_NAME, ctrl);
2255         }
2256         if (ret < 0) {
2257                 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2258                         ctrl->irq, ret);
2259                 return ret;
2260         }
2261
2262         for_each_available_child_of_node(dn, child) {
2263                 if (of_device_is_compatible(child, "brcm,nandcs")) {
2264                         struct brcmnand_host *host;
2265
2266                         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2267                         if (!host)
2268                                 return -ENOMEM;
2269                         host->pdev = pdev;
2270                         host->ctrl = ctrl;
2271                         host->of_node = child;
2272
2273                         ret = brcmnand_init_cs(host);
2274                         if (ret)
2275                                 continue; /* Try all chip-selects */
2276
2277                         list_add_tail(&host->node, &ctrl->host_list);
2278                 }
2279         }
2280
2281         /* No chip-selects could initialize properly */
2282         if (list_empty(&ctrl->host_list))
2283                 return -ENODEV;
2284
2285         return 0;
2286 }
2287 EXPORT_SYMBOL_GPL(brcmnand_probe);
2288
2289 int brcmnand_remove(struct platform_device *pdev)
2290 {
2291         struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2292         struct brcmnand_host *host;
2293
2294         list_for_each_entry(host, &ctrl->host_list, node)
2295                 nand_release(&host->mtd);
2296
2297         dev_set_drvdata(&pdev->dev, NULL);
2298
2299         return 0;
2300 }
2301 EXPORT_SYMBOL_GPL(brcmnand_remove);
2302
2303 MODULE_LICENSE("GPL v2");
2304 MODULE_AUTHOR("Kevin Cernekee");
2305 MODULE_AUTHOR("Brian Norris");
2306 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2307 MODULE_ALIAS("platform:brcmnand");