2 * Copyright © 2010-2015 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/version.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/platform_device.h>
20 #include <linux/err.h>
21 #include <linux/completion.h>
22 #include <linux/interrupt.h>
23 #include <linux/spinlock.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/ioport.h>
26 #include <linux/bug.h>
27 #include <linux/kernel.h>
28 #include <linux/bitops.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/partitions.h>
34 #include <linux/of_mtd.h>
35 #include <linux/of_platform.h>
36 #include <linux/slab.h>
37 #include <linux/list.h>
38 #include <linux/log2.h>
43 * This flag controls if WP stays on between erase/write commands to mitigate
44 * flash corruption due to power glitches. Values:
45 * 0: NAND_WP is not used or not available
46 * 1: NAND_WP is set by default, cleared for erase/write operations
47 * 2: NAND_WP is always cleared
50 module_param(wp_on, int, 0444);
52 /***********************************************************************
54 ***********************************************************************/
56 #define DRV_NAME "brcmnand"
59 #define CMD_PAGE_READ 0x01
60 #define CMD_SPARE_AREA_READ 0x02
61 #define CMD_STATUS_READ 0x03
62 #define CMD_PROGRAM_PAGE 0x04
63 #define CMD_PROGRAM_SPARE_AREA 0x05
64 #define CMD_COPY_BACK 0x06
65 #define CMD_DEVICE_ID_READ 0x07
66 #define CMD_BLOCK_ERASE 0x08
67 #define CMD_FLASH_RESET 0x09
68 #define CMD_BLOCKS_LOCK 0x0a
69 #define CMD_BLOCKS_LOCK_DOWN 0x0b
70 #define CMD_BLOCKS_UNLOCK 0x0c
71 #define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
72 #define CMD_PARAMETER_READ 0x0e
73 #define CMD_PARAMETER_CHANGE_COL 0x0f
74 #define CMD_LOW_LEVEL_OP 0x10
76 struct brcm_nand_dma_desc {
91 /* Bitfields for brcm_nand_dma_desc::status_valid */
92 #define FLASH_DMA_ECC_ERROR (1 << 8)
93 #define FLASH_DMA_CORR_ERROR (1 << 9)
95 /* 512B flash cache in the NAND controller HW */
98 #define FC_WORDS (FC_BYTES >> 2)
100 #define BRCMNAND_MIN_PAGESIZE 512
101 #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
102 #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
104 /* Controller feature flags */
106 BRCMNAND_HAS_1K_SECTORS = BIT(0),
107 BRCMNAND_HAS_PREFETCH = BIT(1),
108 BRCMNAND_HAS_CACHE_MODE = BIT(2),
109 BRCMNAND_HAS_WP = BIT(3),
112 struct brcmnand_controller {
114 struct nand_hw_control controller;
115 void __iomem *nand_base;
116 void __iomem *nand_fc; /* flash cache */
117 void __iomem *flash_dma_base;
119 unsigned int dma_irq;
122 /* Some SoCs provide custom interrupt status register(s) */
123 struct brcmnand_soc *soc;
127 struct completion done;
128 struct completion dma_done;
130 /* List of NAND hosts (one for each chip-select) */
131 struct list_head host_list;
133 struct brcm_nand_dma_desc *dma_desc;
136 /* in-memory cache of the FLASH_CACHE, used only for some commands */
137 u32 flash_cache[FC_WORDS];
139 /* Controller revision details */
140 const u16 *reg_offsets;
141 unsigned int reg_spacing; /* between CS1, CS2, ... regs */
142 const u8 *cs_offsets; /* within each chip-select */
143 const u8 *cs0_offsets; /* within CS0, if different */
144 unsigned int max_block_size;
145 const unsigned int *block_sizes;
146 unsigned int max_page_size;
147 const unsigned int *page_sizes;
148 unsigned int max_oob;
151 /* for low-power standby/resume only */
152 u32 nand_cs_nand_select;
153 u32 nand_cs_nand_xor;
154 u32 corr_stat_threshold;
158 struct brcmnand_cfg {
160 unsigned int block_size;
161 unsigned int page_size;
162 unsigned int spare_area_size;
163 unsigned int device_width;
164 unsigned int col_adr_bytes;
165 unsigned int blk_adr_bytes;
166 unsigned int ful_adr_bytes;
167 unsigned int sector_size_1k;
168 unsigned int ecc_level;
169 /* use for low-power standby/resume only */
177 struct brcmnand_host {
178 struct list_head node;
179 struct device_node *of_node;
181 struct nand_chip chip;
183 struct platform_device *pdev;
186 unsigned int last_cmd;
187 unsigned int last_byte;
189 struct brcmnand_cfg hwcfg;
190 struct brcmnand_controller *ctrl;
194 BRCMNAND_CMD_START = 0,
195 BRCMNAND_CMD_EXT_ADDRESS,
196 BRCMNAND_CMD_ADDRESS,
197 BRCMNAND_INTFC_STATUS,
202 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
203 BRCMNAND_CORR_THRESHOLD,
204 BRCMNAND_CORR_THRESHOLD_EXT,
205 BRCMNAND_UNCORR_COUNT,
207 BRCMNAND_CORR_EXT_ADDR,
209 BRCMNAND_UNCORR_EXT_ADDR,
210 BRCMNAND_UNCORR_ADDR,
215 BRCMNAND_OOB_READ_BASE,
216 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
217 BRCMNAND_OOB_WRITE_BASE,
218 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
223 static const u16 brcmnand_regs_v40[] = {
224 [BRCMNAND_CMD_START] = 0x04,
225 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
226 [BRCMNAND_CMD_ADDRESS] = 0x0c,
227 [BRCMNAND_INTFC_STATUS] = 0x6c,
228 [BRCMNAND_CS_SELECT] = 0x14,
229 [BRCMNAND_CS_XOR] = 0x18,
230 [BRCMNAND_LL_OP] = 0x178,
231 [BRCMNAND_CS0_BASE] = 0x40,
232 [BRCMNAND_CS1_BASE] = 0xd0,
233 [BRCMNAND_CORR_THRESHOLD] = 0x84,
234 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
235 [BRCMNAND_UNCORR_COUNT] = 0,
236 [BRCMNAND_CORR_COUNT] = 0,
237 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
238 [BRCMNAND_CORR_ADDR] = 0x74,
239 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
240 [BRCMNAND_UNCORR_ADDR] = 0x7c,
241 [BRCMNAND_SEMAPHORE] = 0x58,
242 [BRCMNAND_ID] = 0x60,
243 [BRCMNAND_ID_EXT] = 0x64,
244 [BRCMNAND_LL_RDATA] = 0x17c,
245 [BRCMNAND_OOB_READ_BASE] = 0x20,
246 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
247 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
248 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
249 [BRCMNAND_FC_BASE] = 0x200,
253 static const u16 brcmnand_regs_v50[] = {
254 [BRCMNAND_CMD_START] = 0x04,
255 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
256 [BRCMNAND_CMD_ADDRESS] = 0x0c,
257 [BRCMNAND_INTFC_STATUS] = 0x6c,
258 [BRCMNAND_CS_SELECT] = 0x14,
259 [BRCMNAND_CS_XOR] = 0x18,
260 [BRCMNAND_LL_OP] = 0x178,
261 [BRCMNAND_CS0_BASE] = 0x40,
262 [BRCMNAND_CS1_BASE] = 0xd0,
263 [BRCMNAND_CORR_THRESHOLD] = 0x84,
264 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
265 [BRCMNAND_UNCORR_COUNT] = 0,
266 [BRCMNAND_CORR_COUNT] = 0,
267 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
268 [BRCMNAND_CORR_ADDR] = 0x74,
269 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
270 [BRCMNAND_UNCORR_ADDR] = 0x7c,
271 [BRCMNAND_SEMAPHORE] = 0x58,
272 [BRCMNAND_ID] = 0x60,
273 [BRCMNAND_ID_EXT] = 0x64,
274 [BRCMNAND_LL_RDATA] = 0x17c,
275 [BRCMNAND_OOB_READ_BASE] = 0x20,
276 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
277 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
278 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140,
279 [BRCMNAND_FC_BASE] = 0x200,
282 /* BRCMNAND v6.0 - v7.1 */
283 static const u16 brcmnand_regs_v60[] = {
284 [BRCMNAND_CMD_START] = 0x04,
285 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
286 [BRCMNAND_CMD_ADDRESS] = 0x0c,
287 [BRCMNAND_INTFC_STATUS] = 0x14,
288 [BRCMNAND_CS_SELECT] = 0x18,
289 [BRCMNAND_CS_XOR] = 0x1c,
290 [BRCMNAND_LL_OP] = 0x20,
291 [BRCMNAND_CS0_BASE] = 0x50,
292 [BRCMNAND_CS1_BASE] = 0,
293 [BRCMNAND_CORR_THRESHOLD] = 0xc0,
294 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4,
295 [BRCMNAND_UNCORR_COUNT] = 0xfc,
296 [BRCMNAND_CORR_COUNT] = 0x100,
297 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
298 [BRCMNAND_CORR_ADDR] = 0x110,
299 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
300 [BRCMNAND_UNCORR_ADDR] = 0x118,
301 [BRCMNAND_SEMAPHORE] = 0x150,
302 [BRCMNAND_ID] = 0x194,
303 [BRCMNAND_ID_EXT] = 0x198,
304 [BRCMNAND_LL_RDATA] = 0x19c,
305 [BRCMNAND_OOB_READ_BASE] = 0x200,
306 [BRCMNAND_OOB_READ_10_BASE] = 0,
307 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
308 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
309 [BRCMNAND_FC_BASE] = 0x400,
313 static const u16 brcmnand_regs_v71[] = {
314 [BRCMNAND_CMD_START] = 0x04,
315 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
316 [BRCMNAND_CMD_ADDRESS] = 0x0c,
317 [BRCMNAND_INTFC_STATUS] = 0x14,
318 [BRCMNAND_CS_SELECT] = 0x18,
319 [BRCMNAND_CS_XOR] = 0x1c,
320 [BRCMNAND_LL_OP] = 0x20,
321 [BRCMNAND_CS0_BASE] = 0x50,
322 [BRCMNAND_CS1_BASE] = 0,
323 [BRCMNAND_CORR_THRESHOLD] = 0xdc,
324 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
325 [BRCMNAND_UNCORR_COUNT] = 0xfc,
326 [BRCMNAND_CORR_COUNT] = 0x100,
327 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
328 [BRCMNAND_CORR_ADDR] = 0x110,
329 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
330 [BRCMNAND_UNCORR_ADDR] = 0x118,
331 [BRCMNAND_SEMAPHORE] = 0x150,
332 [BRCMNAND_ID] = 0x194,
333 [BRCMNAND_ID_EXT] = 0x198,
334 [BRCMNAND_LL_RDATA] = 0x19c,
335 [BRCMNAND_OOB_READ_BASE] = 0x200,
336 [BRCMNAND_OOB_READ_10_BASE] = 0,
337 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
338 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
339 [BRCMNAND_FC_BASE] = 0x400,
342 enum brcmnand_cs_reg {
343 BRCMNAND_CS_CFG_EXT = 0,
345 BRCMNAND_CS_ACC_CONTROL,
350 /* Per chip-select offsets for v7.1 */
351 static const u8 brcmnand_cs_offsets_v71[] = {
352 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
353 [BRCMNAND_CS_CFG_EXT] = 0x04,
354 [BRCMNAND_CS_CFG] = 0x08,
355 [BRCMNAND_CS_TIMING1] = 0x0c,
356 [BRCMNAND_CS_TIMING2] = 0x10,
359 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
360 static const u8 brcmnand_cs_offsets[] = {
361 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
362 [BRCMNAND_CS_CFG_EXT] = 0x04,
363 [BRCMNAND_CS_CFG] = 0x04,
364 [BRCMNAND_CS_TIMING1] = 0x08,
365 [BRCMNAND_CS_TIMING2] = 0x0c,
368 /* Per chip-select offset for <= v5.0 on CS0 only */
369 static const u8 brcmnand_cs_offsets_cs0[] = {
370 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
371 [BRCMNAND_CS_CFG_EXT] = 0x08,
372 [BRCMNAND_CS_CFG] = 0x08,
373 [BRCMNAND_CS_TIMING1] = 0x10,
374 [BRCMNAND_CS_TIMING2] = 0x14,
378 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
379 * one config register, but once the bitfields overflowed, newer controllers
380 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
383 CFG_BLK_ADR_BYTES_SHIFT = 8,
384 CFG_COL_ADR_BYTES_SHIFT = 12,
385 CFG_FUL_ADR_BYTES_SHIFT = 16,
386 CFG_BUS_WIDTH_SHIFT = 23,
387 CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
388 CFG_DEVICE_SIZE_SHIFT = 24,
390 /* Only for pre-v7.1 (with no CFG_EXT register) */
391 CFG_PAGE_SIZE_SHIFT = 20,
392 CFG_BLK_SIZE_SHIFT = 28,
394 /* Only for v7.1+ (with CFG_EXT register) */
395 CFG_EXT_PAGE_SIZE_SHIFT = 0,
396 CFG_EXT_BLK_SIZE_SHIFT = 4,
399 /* BRCMNAND_INTFC_STATUS */
401 INTFC_FLASH_STATUS = GENMASK(7, 0),
403 INTFC_ERASED = BIT(27),
404 INTFC_OOB_VALID = BIT(28),
405 INTFC_CACHE_VALID = BIT(29),
406 INTFC_FLASH_READY = BIT(30),
407 INTFC_CTLR_READY = BIT(31),
410 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
412 return brcmnand_readl(ctrl->nand_base + offs);
415 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
418 brcmnand_writel(val, ctrl->nand_base + offs);
421 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
423 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
424 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
425 static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
427 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
429 /* Only support v4.0+? */
430 if (ctrl->nand_version < 0x0400) {
431 dev_err(ctrl->dev, "version %#x not supported\n",
436 /* Register offsets */
437 if (ctrl->nand_version >= 0x0701)
438 ctrl->reg_offsets = brcmnand_regs_v71;
439 else if (ctrl->nand_version >= 0x0600)
440 ctrl->reg_offsets = brcmnand_regs_v60;
441 else if (ctrl->nand_version >= 0x0500)
442 ctrl->reg_offsets = brcmnand_regs_v50;
443 else if (ctrl->nand_version >= 0x0400)
444 ctrl->reg_offsets = brcmnand_regs_v40;
446 /* Chip-select stride */
447 if (ctrl->nand_version >= 0x0701)
448 ctrl->reg_spacing = 0x14;
450 ctrl->reg_spacing = 0x10;
452 /* Per chip-select registers */
453 if (ctrl->nand_version >= 0x0701) {
454 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
456 ctrl->cs_offsets = brcmnand_cs_offsets;
458 /* v3.3-5.0 have a different CS0 offset layout */
459 if (ctrl->nand_version >= 0x0303 &&
460 ctrl->nand_version <= 0x0500)
461 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
464 /* Page / block sizes */
465 if (ctrl->nand_version >= 0x0701) {
466 /* >= v7.1 use nice power-of-2 values! */
467 ctrl->max_page_size = 16 * 1024;
468 ctrl->max_block_size = 2 * 1024 * 1024;
470 ctrl->page_sizes = page_sizes;
471 if (ctrl->nand_version >= 0x0600)
472 ctrl->block_sizes = block_sizes_v6;
474 ctrl->block_sizes = block_sizes_v4;
476 if (ctrl->nand_version < 0x0400) {
477 ctrl->max_page_size = 4096;
478 ctrl->max_block_size = 512 * 1024;
482 /* Maximum spare area sector size (per 512B) */
483 if (ctrl->nand_version >= 0x0600)
485 else if (ctrl->nand_version >= 0x0500)
490 /* v6.0 and newer (except v6.1) have prefetch support */
491 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
492 ctrl->features |= BRCMNAND_HAS_PREFETCH;
495 * v6.x has cache mode, but it's implemented differently. Ignore it for
498 if (ctrl->nand_version >= 0x0700)
499 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
501 if (ctrl->nand_version >= 0x0500)
502 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
504 if (ctrl->nand_version >= 0x0700)
505 ctrl->features |= BRCMNAND_HAS_WP;
506 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
507 ctrl->features |= BRCMNAND_HAS_WP;
512 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
513 enum brcmnand_reg reg)
515 u16 offs = ctrl->reg_offsets[reg];
518 return nand_readreg(ctrl, offs);
523 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
524 enum brcmnand_reg reg, u32 val)
526 u16 offs = ctrl->reg_offsets[reg];
529 nand_writereg(ctrl, offs, val);
532 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
533 enum brcmnand_reg reg, u32 mask, unsigned
536 u32 tmp = brcmnand_read_reg(ctrl, reg);
540 brcmnand_write_reg(ctrl, reg, tmp);
543 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
545 return __raw_readl(ctrl->nand_fc + word * 4);
548 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
551 __raw_writel(val, ctrl->nand_fc + word * 4);
554 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
555 enum brcmnand_cs_reg reg)
557 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
558 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
561 if (cs == 0 && ctrl->cs0_offsets)
562 cs_offs = ctrl->cs0_offsets[reg];
564 cs_offs = ctrl->cs_offsets[reg];
567 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
569 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
572 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
574 if (ctrl->nand_version < 0x0600)
576 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
579 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
581 struct brcmnand_controller *ctrl = host->ctrl;
582 unsigned int shift = 0, bits;
583 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
586 if (ctrl->nand_version >= 0x0600)
588 else if (ctrl->nand_version >= 0x0500)
593 if (ctrl->nand_version >= 0x0600) {
595 reg = BRCMNAND_CORR_THRESHOLD_EXT;
596 shift = (cs % 5) * bits;
598 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
601 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
603 if (ctrl->nand_version < 0x0700)
608 /***********************************************************************
609 * NAND ACC CONTROL bitfield
611 * Some bits have remained constant throughout hardware revision, while
612 * others have shifted around.
613 ***********************************************************************/
615 /* Constant for all versions (where supported) */
617 /* See BRCMNAND_HAS_CACHE_MODE */
618 ACC_CONTROL_CACHE_MODE = BIT(22),
620 /* See BRCMNAND_HAS_PREFETCH */
621 ACC_CONTROL_PREFETCH = BIT(23),
623 ACC_CONTROL_PAGE_HIT = BIT(24),
624 ACC_CONTROL_WR_PREEMPT = BIT(25),
625 ACC_CONTROL_PARTIAL_PAGE = BIT(26),
626 ACC_CONTROL_RD_ERASED = BIT(27),
627 ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
628 ACC_CONTROL_WR_ECC = BIT(30),
629 ACC_CONTROL_RD_ECC = BIT(31),
632 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
634 if (ctrl->nand_version >= 0x0600)
635 return GENMASK(6, 0);
637 return GENMASK(5, 0);
640 #define NAND_ACC_CONTROL_ECC_SHIFT 16
642 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
644 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
646 return mask << NAND_ACC_CONTROL_ECC_SHIFT;
649 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
651 struct brcmnand_controller *ctrl = host->ctrl;
652 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
653 u32 acc_control = nand_readreg(ctrl, offs);
654 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
657 acc_control |= ecc_flags; /* enable RD/WR ECC */
658 acc_control |= host->hwcfg.ecc_level
659 << NAND_ACC_CONTROL_ECC_SHIFT;
661 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
662 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
665 nand_writereg(ctrl, offs, acc_control);
668 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
670 if (ctrl->nand_version >= 0x0600)
672 else if (ctrl->nand_version >= 0x0500)
678 static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
680 struct brcmnand_controller *ctrl = host->ctrl;
681 int shift = brcmnand_sector_1k_shift(ctrl);
682 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
683 BRCMNAND_CS_ACC_CONTROL);
688 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
691 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
693 struct brcmnand_controller *ctrl = host->ctrl;
694 int shift = brcmnand_sector_1k_shift(ctrl);
695 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
696 BRCMNAND_CS_ACC_CONTROL);
702 tmp = nand_readreg(ctrl, acc_control_offs);
703 tmp &= ~(1 << shift);
704 tmp |= (!!val) << shift;
705 nand_writereg(ctrl, acc_control_offs, tmp);
708 /***********************************************************************
710 ***********************************************************************/
713 CS_SELECT_NAND_WP = BIT(29),
714 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30),
717 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
719 u32 val = en ? CS_SELECT_NAND_WP : 0;
721 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
724 /***********************************************************************
726 ***********************************************************************/
729 FLASH_DMA_REVISION = 0x00,
730 FLASH_DMA_FIRST_DESC = 0x04,
731 FLASH_DMA_FIRST_DESC_EXT = 0x08,
732 FLASH_DMA_CTRL = 0x0c,
733 FLASH_DMA_MODE = 0x10,
734 FLASH_DMA_STATUS = 0x14,
735 FLASH_DMA_INTERRUPT_DESC = 0x18,
736 FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c,
737 FLASH_DMA_ERROR_STATUS = 0x20,
738 FLASH_DMA_CURRENT_DESC = 0x24,
739 FLASH_DMA_CURRENT_DESC_EXT = 0x28,
742 static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
744 return ctrl->flash_dma_base;
747 static inline bool flash_dma_buf_ok(const void *buf)
749 return buf && !is_vmalloc_addr(buf) &&
750 likely(IS_ALIGNED((uintptr_t)buf, 4));
753 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
756 brcmnand_writel(val, ctrl->flash_dma_base + offs);
759 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
761 return brcmnand_readl(ctrl->flash_dma_base + offs);
764 /* Low-level operation types: command, address, write, or read */
765 enum brcmnand_llop_type {
772 /***********************************************************************
773 * Internal support functions
774 ***********************************************************************/
776 static inline bool is_hamming_ecc(struct brcmnand_cfg *cfg)
778 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
779 cfg->ecc_level == 15;
783 * Returns a nand_ecclayout strucutre for the given layout/configuration.
784 * Returns NULL on failure.
786 static struct nand_ecclayout *brcmnand_create_layout(int ecc_level,
787 struct brcmnand_host *host)
789 struct brcmnand_cfg *cfg = &host->hwcfg;
791 struct nand_ecclayout *layout;
797 layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
801 sectors = cfg->page_size / (512 << cfg->sector_size_1k);
802 sas = cfg->spare_area_size << cfg->sector_size_1k;
805 if (is_hamming_ecc(cfg)) {
806 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
807 /* First sector of each page may have BBI */
809 layout->oobfree[idx2].offset = i * sas + 1;
810 /* Small-page NAND use byte 6 for BBI */
811 if (cfg->page_size == 512)
812 layout->oobfree[idx2].offset--;
813 layout->oobfree[idx2].length = 5;
815 layout->oobfree[idx2].offset = i * sas;
816 layout->oobfree[idx2].length = 6;
819 layout->eccpos[idx1++] = i * sas + 6;
820 layout->eccpos[idx1++] = i * sas + 7;
821 layout->eccpos[idx1++] = i * sas + 8;
822 layout->oobfree[idx2].offset = i * sas + 9;
823 layout->oobfree[idx2].length = 7;
825 /* Leave zero-terminated entry for OOBFREE */
826 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
827 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
834 * CONTROLLER_VERSION:
835 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
836 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
837 * But we will just be conservative.
839 req = DIV_ROUND_UP(ecc_level * 14, 8);
841 dev_err(&host->pdev->dev,
842 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
847 layout->eccbytes = req * sectors;
848 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
849 for (j = sas - req; j < sas && idx1 <
850 MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
851 layout->eccpos[idx1] = i * sas + j;
853 /* First sector of each page may have BBI */
855 if (cfg->page_size == 512 && (sas - req >= 6)) {
856 /* Small-page NAND use byte 6 for BBI */
857 layout->oobfree[idx2].offset = 0;
858 layout->oobfree[idx2].length = 5;
861 layout->oobfree[idx2].offset = 6;
862 layout->oobfree[idx2].length =
866 } else if (sas > req + 1) {
867 layout->oobfree[idx2].offset = i * sas + 1;
868 layout->oobfree[idx2].length = sas - req - 1;
871 } else if (sas > req) {
872 layout->oobfree[idx2].offset = i * sas;
873 layout->oobfree[idx2].length = sas - req;
876 /* Leave zero-terminated entry for OOBFREE */
877 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
878 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
882 /* Sum available OOB */
883 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE; i++)
884 layout->oobavail += layout->oobfree[i].length;
888 static struct nand_ecclayout *brcmstb_choose_ecc_layout(
889 struct brcmnand_host *host)
891 struct nand_ecclayout *layout;
892 struct brcmnand_cfg *p = &host->hwcfg;
893 unsigned int ecc_level = p->ecc_level;
895 if (p->sector_size_1k)
898 layout = brcmnand_create_layout(ecc_level, host);
900 dev_err(&host->pdev->dev,
901 "no proper ecc_layout for this NAND cfg\n");
908 static void brcmnand_wp(struct mtd_info *mtd, int wp)
910 struct nand_chip *chip = mtd->priv;
911 struct brcmnand_host *host = chip->priv;
912 struct brcmnand_controller *ctrl = host->ctrl;
914 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
915 static int old_wp = -1;
918 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
921 brcmnand_set_wp(ctrl, wp);
925 /* Helper functions for reading and writing OOB registers */
926 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
928 u16 offset0, offset10, reg_offs;
930 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
931 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
933 if (offs >= ctrl->max_oob)
936 if (offs >= 16 && offset10)
937 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
939 reg_offs = offset0 + (offs & ~0x03);
941 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
944 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
947 u16 offset0, offset10, reg_offs;
949 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
950 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
952 if (offs >= ctrl->max_oob)
955 if (offs >= 16 && offset10)
956 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
958 reg_offs = offset0 + (offs & ~0x03);
960 nand_writereg(ctrl, reg_offs, data);
964 * read_oob_from_regs - read data from OOB registers
965 * @ctrl: NAND controller
966 * @i: sub-page sector index
967 * @oob: buffer to read to
968 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
969 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
971 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
972 int sas, int sector_1k)
974 int tbytes = sas << sector_1k;
977 /* Adjust OOB values for 1K sector size */
978 if (sector_1k && (i & 0x01))
979 tbytes = max(0, tbytes - (int)ctrl->max_oob);
980 tbytes = min_t(int, tbytes, ctrl->max_oob);
982 for (j = 0; j < tbytes; j++)
983 oob[j] = oob_reg_read(ctrl, j);
988 * write_oob_to_regs - write data to OOB registers
989 * @i: sub-page sector index
990 * @oob: buffer to write from
991 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
992 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
994 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
995 const u8 *oob, int sas, int sector_1k)
997 int tbytes = sas << sector_1k;
1000 /* Adjust OOB values for 1K sector size */
1001 if (sector_1k && (i & 0x01))
1002 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1003 tbytes = min_t(int, tbytes, ctrl->max_oob);
1005 for (j = 0; j < tbytes; j += 4)
1006 oob_reg_write(ctrl, j,
1007 (oob[j + 0] << 24) |
1008 (oob[j + 1] << 16) |
1014 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1016 struct brcmnand_controller *ctrl = data;
1018 /* Discard all NAND_CTLRDY interrupts during DMA */
1019 if (ctrl->dma_pending)
1022 complete(&ctrl->done);
1026 /* Handle SoC-specific interrupt hardware */
1027 static irqreturn_t brcmnand_irq(int irq, void *data)
1029 struct brcmnand_controller *ctrl = data;
1031 if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1032 return brcmnand_ctlrdy_irq(irq, data);
1037 static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1039 struct brcmnand_controller *ctrl = data;
1041 complete(&ctrl->dma_done);
1046 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1048 struct brcmnand_controller *ctrl = host->ctrl;
1051 dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
1052 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
1053 BUG_ON(ctrl->cmd_pending != 0);
1054 ctrl->cmd_pending = cmd;
1056 intfc = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1057 BUG_ON(!(intfc & INTFC_CTLR_READY));
1059 mb(); /* flush previous writes */
1060 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1061 cmd << brcmnand_cmd_shift(ctrl));
1064 /***********************************************************************
1065 * NAND MTD API: read/program/erase
1066 ***********************************************************************/
1068 static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1071 /* intentionally left blank */
1074 static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1076 struct nand_chip *chip = mtd->priv;
1077 struct brcmnand_host *host = chip->priv;
1078 struct brcmnand_controller *ctrl = host->ctrl;
1079 unsigned long timeo = msecs_to_jiffies(100);
1081 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1082 if (ctrl->cmd_pending &&
1083 wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1084 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1085 >> brcmnand_cmd_shift(ctrl);
1087 dev_err_ratelimited(ctrl->dev,
1088 "timeout waiting for command %#02x\n", cmd);
1089 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1090 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1092 ctrl->cmd_pending = 0;
1093 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1102 LLOP_RETURN_IDLE = BIT(31),
1104 LLOP_DATA_MASK = GENMASK(15, 0),
1107 static int brcmnand_low_level_op(struct brcmnand_host *host,
1108 enum brcmnand_llop_type type, u32 data,
1111 struct mtd_info *mtd = &host->mtd;
1112 struct nand_chip *chip = &host->chip;
1113 struct brcmnand_controller *ctrl = host->ctrl;
1116 tmp = data & LLOP_DATA_MASK;
1119 tmp |= LLOP_WE | LLOP_CLE;
1123 tmp |= LLOP_WE | LLOP_ALE;
1136 tmp |= LLOP_RETURN_IDLE;
1138 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1140 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1141 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1143 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1144 return brcmnand_waitfunc(mtd, chip);
1147 static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1148 int column, int page_addr)
1150 struct nand_chip *chip = mtd->priv;
1151 struct brcmnand_host *host = chip->priv;
1152 struct brcmnand_controller *ctrl = host->ctrl;
1153 u64 addr = (u64)page_addr << chip->page_shift;
1156 if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1157 command == NAND_CMD_RNDOUT)
1159 /* Avoid propagating a negative, don't-care address */
1160 else if (page_addr < 0)
1163 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1164 (unsigned long long)addr);
1166 host->last_cmd = command;
1167 host->last_byte = 0;
1168 host->last_addr = addr;
1171 case NAND_CMD_RESET:
1172 native_cmd = CMD_FLASH_RESET;
1174 case NAND_CMD_STATUS:
1175 native_cmd = CMD_STATUS_READ;
1177 case NAND_CMD_READID:
1178 native_cmd = CMD_DEVICE_ID_READ;
1180 case NAND_CMD_READOOB:
1181 native_cmd = CMD_SPARE_AREA_READ;
1183 case NAND_CMD_ERASE1:
1184 native_cmd = CMD_BLOCK_ERASE;
1185 brcmnand_wp(mtd, 0);
1187 case NAND_CMD_PARAM:
1188 native_cmd = CMD_PARAMETER_READ;
1190 case NAND_CMD_SET_FEATURES:
1191 case NAND_CMD_GET_FEATURES:
1192 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1193 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1195 case NAND_CMD_RNDOUT:
1196 native_cmd = CMD_PARAMETER_CHANGE_COL;
1197 addr &= ~((u64)(FC_BYTES - 1));
1199 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1200 * NB: hwcfg.sector_size_1k may not be initialized yet
1202 if (brcmnand_get_sector_size_1k(host)) {
1203 host->hwcfg.sector_size_1k =
1204 brcmnand_get_sector_size_1k(host);
1205 brcmnand_set_sector_size_1k(host, 0);
1213 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1214 (host->cs << 16) | ((addr >> 32) & 0xffff));
1215 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1216 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1217 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1219 brcmnand_send_cmd(host, native_cmd);
1220 brcmnand_waitfunc(mtd, chip);
1222 if (native_cmd == CMD_PARAMETER_READ ||
1223 native_cmd == CMD_PARAMETER_CHANGE_COL) {
1226 brcmnand_soc_data_bus_prepare(ctrl->soc);
1229 * Must cache the FLASH_CACHE now, since changes in
1230 * SECTOR_SIZE_1K may invalidate it
1232 for (i = 0; i < FC_WORDS; i++)
1233 ctrl->flash_cache[i] = brcmnand_read_fc(ctrl, i);
1235 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1237 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1238 if (host->hwcfg.sector_size_1k)
1239 brcmnand_set_sector_size_1k(host,
1240 host->hwcfg.sector_size_1k);
1243 /* Re-enable protection is necessary only after erase */
1244 if (command == NAND_CMD_ERASE1)
1245 brcmnand_wp(mtd, 1);
1248 static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1250 struct nand_chip *chip = mtd->priv;
1251 struct brcmnand_host *host = chip->priv;
1252 struct brcmnand_controller *ctrl = host->ctrl;
1256 switch (host->last_cmd) {
1257 case NAND_CMD_READID:
1258 if (host->last_byte < 4)
1259 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1260 (24 - (host->last_byte << 3));
1261 else if (host->last_byte < 8)
1262 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1263 (56 - (host->last_byte << 3));
1266 case NAND_CMD_READOOB:
1267 ret = oob_reg_read(ctrl, host->last_byte);
1270 case NAND_CMD_STATUS:
1271 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1273 if (wp_on) /* hide WP status */
1274 ret |= NAND_STATUS_WP;
1277 case NAND_CMD_PARAM:
1278 case NAND_CMD_RNDOUT:
1279 addr = host->last_addr + host->last_byte;
1280 offs = addr & (FC_BYTES - 1);
1282 /* At FC_BYTES boundary, switch to next column */
1283 if (host->last_byte > 0 && offs == 0)
1284 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
1286 ret = ctrl->flash_cache[offs >> 2] >>
1287 (24 - ((offs & 0x03) << 3));
1289 case NAND_CMD_GET_FEATURES:
1290 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1293 bool last = host->last_byte ==
1294 ONFI_SUBFEATURE_PARAM_LEN - 1;
1295 brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1296 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1300 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1306 static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1310 for (i = 0; i < len; i++, buf++)
1311 *buf = brcmnand_read_byte(mtd);
1314 static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1318 struct nand_chip *chip = mtd->priv;
1319 struct brcmnand_host *host = chip->priv;
1321 switch (host->last_cmd) {
1322 case NAND_CMD_SET_FEATURES:
1323 for (i = 0; i < len; i++)
1324 brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1334 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1335 * following ahead of time:
1336 * - Is this descriptor the beginning or end of a linked list?
1337 * - What is the (DMA) address of the next descriptor in the linked list?
1339 static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1340 struct brcm_nand_dma_desc *desc, u64 addr,
1341 dma_addr_t buf, u32 len, u8 dma_cmd,
1342 bool begin, bool end,
1343 dma_addr_t next_desc)
1345 memset(desc, 0, sizeof(*desc));
1346 /* Descriptors are written in native byte order (wordwise) */
1347 desc->next_desc = lower_32_bits(next_desc);
1348 desc->next_desc_ext = upper_32_bits(next_desc);
1349 desc->cmd_irq = (dma_cmd << 24) |
1350 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1351 (!!begin) | ((!!end) << 1); /* head, tail */
1352 #ifdef CONFIG_CPU_BIG_ENDIAN
1353 desc->cmd_irq |= 0x01 << 12;
1355 desc->dram_addr = lower_32_bits(buf);
1356 desc->dram_addr_ext = upper_32_bits(buf);
1357 desc->tfr_len = len;
1358 desc->total_len = len;
1359 desc->flash_addr = lower_32_bits(addr);
1360 desc->flash_addr_ext = upper_32_bits(addr);
1361 desc->cs = host->cs;
1362 desc->status_valid = 0x01;
1367 * Kick the FLASH_DMA engine, with a given DMA descriptor
1369 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1371 struct brcmnand_controller *ctrl = host->ctrl;
1372 unsigned long timeo = msecs_to_jiffies(100);
1374 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1375 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1376 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1377 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1379 /* Start FLASH_DMA engine */
1380 ctrl->dma_pending = true;
1381 mb(); /* flush previous writes */
1382 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1384 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1386 "timeout waiting for DMA; status %#x, error status %#x\n",
1387 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1388 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1390 ctrl->dma_pending = false;
1391 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1394 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1395 u32 len, u8 dma_cmd)
1397 struct brcmnand_controller *ctrl = host->ctrl;
1399 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1401 buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1402 if (dma_mapping_error(ctrl->dev, buf_pa)) {
1403 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1407 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1408 dma_cmd, true, true, 0);
1410 brcmnand_dma_run(host, ctrl->dma_pa);
1412 dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1414 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1416 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1423 * Assumes proper CS is already set
1425 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1426 u64 addr, unsigned int trans, u32 *buf,
1427 u8 *oob, u64 *err_addr)
1429 struct brcmnand_host *host = chip->priv;
1430 struct brcmnand_controller *ctrl = host->ctrl;
1433 /* Clear error addresses */
1434 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1435 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
1437 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1438 (host->cs << 16) | ((addr >> 32) & 0xffff));
1439 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1441 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1442 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1443 lower_32_bits(addr));
1444 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1445 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1446 brcmnand_send_cmd(host, CMD_PAGE_READ);
1447 brcmnand_waitfunc(mtd, chip);
1450 brcmnand_soc_data_bus_prepare(ctrl->soc);
1452 for (j = 0; j < FC_WORDS; j++, buf++)
1453 *buf = brcmnand_read_fc(ctrl, j);
1455 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1459 oob += read_oob_from_regs(ctrl, i, oob,
1460 mtd->oobsize / trans,
1461 host->hwcfg.sector_size_1k);
1464 *err_addr = brcmnand_read_reg(ctrl,
1465 BRCMNAND_UNCORR_ADDR) |
1466 ((u64)(brcmnand_read_reg(ctrl,
1467 BRCMNAND_UNCORR_EXT_ADDR)
1474 *err_addr = brcmnand_read_reg(ctrl,
1475 BRCMNAND_CORR_ADDR) |
1476 ((u64)(brcmnand_read_reg(ctrl,
1477 BRCMNAND_CORR_EXT_ADDR)
1487 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1488 u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1490 struct brcmnand_host *host = chip->priv;
1491 struct brcmnand_controller *ctrl = host->ctrl;
1495 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1497 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1499 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1500 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1503 if (mtd_is_bitflip_or_eccerr(err))
1510 memset(oob, 0x99, mtd->oobsize);
1512 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1516 if (mtd_is_eccerr(err)) {
1517 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1518 (unsigned long long)err_addr);
1519 mtd->ecc_stats.failed++;
1520 /* NAND layer expects zero on ECC errors */
1524 if (mtd_is_bitflip(err)) {
1525 unsigned int corrected = brcmnand_count_corrected(ctrl);
1527 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1528 (unsigned long long)err_addr);
1529 mtd->ecc_stats.corrected += corrected;
1530 /* Always exceed the software-imposed threshold */
1531 return max(mtd->bitflip_threshold, corrected);
1537 static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1538 uint8_t *buf, int oob_required, int page)
1540 struct brcmnand_host *host = chip->priv;
1541 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1543 return brcmnand_read(mtd, chip, host->last_addr,
1544 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1547 static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1548 uint8_t *buf, int oob_required, int page)
1550 struct brcmnand_host *host = chip->priv;
1551 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1554 brcmnand_set_ecc_enabled(host, 0);
1555 ret = brcmnand_read(mtd, chip, host->last_addr,
1556 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1557 brcmnand_set_ecc_enabled(host, 1);
1561 static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1564 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1565 mtd->writesize >> FC_SHIFT,
1566 NULL, (u8 *)chip->oob_poi);
1569 static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1572 struct brcmnand_host *host = chip->priv;
1574 brcmnand_set_ecc_enabled(host, 0);
1575 brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1576 mtd->writesize >> FC_SHIFT,
1577 NULL, (u8 *)chip->oob_poi);
1578 brcmnand_set_ecc_enabled(host, 1);
1582 static int brcmnand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1583 uint32_t data_offs, uint32_t readlen,
1584 uint8_t *bufpoi, int page)
1586 struct brcmnand_host *host = chip->priv;
1588 return brcmnand_read(mtd, chip, host->last_addr + data_offs,
1589 readlen >> FC_SHIFT, (u32 *)bufpoi, NULL);
1592 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1593 u64 addr, const u32 *buf, u8 *oob)
1595 struct brcmnand_host *host = chip->priv;
1596 struct brcmnand_controller *ctrl = host->ctrl;
1597 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1598 int status, ret = 0;
1600 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1602 if (unlikely((unsigned long)buf & 0x03)) {
1603 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
1604 buf = (u32 *)((unsigned long)buf & ~0x03);
1607 brcmnand_wp(mtd, 0);
1609 for (i = 0; i < ctrl->max_oob; i += 4)
1610 oob_reg_write(ctrl, i, 0xffffffff);
1612 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1613 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1614 mtd->writesize, CMD_PROGRAM_PAGE))
1619 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1620 (host->cs << 16) | ((addr >> 32) & 0xffff));
1621 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1623 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1624 /* full address MUST be set before populating FC */
1625 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1626 lower_32_bits(addr));
1627 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1630 brcmnand_soc_data_bus_prepare(ctrl->soc);
1632 for (j = 0; j < FC_WORDS; j++, buf++)
1633 brcmnand_write_fc(ctrl, j, *buf);
1635 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1637 for (j = 0; j < FC_WORDS; j++)
1638 brcmnand_write_fc(ctrl, j, 0xffffffff);
1642 oob += write_oob_to_regs(ctrl, i, oob,
1643 mtd->oobsize / trans,
1644 host->hwcfg.sector_size_1k);
1647 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1648 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1649 status = brcmnand_waitfunc(mtd, chip);
1651 if (status & NAND_STATUS_FAIL) {
1652 dev_info(ctrl->dev, "program failed at %llx\n",
1653 (unsigned long long)addr);
1659 brcmnand_wp(mtd, 1);
1663 static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1664 const uint8_t *buf, int oob_required, int page)
1666 struct brcmnand_host *host = chip->priv;
1667 void *oob = oob_required ? chip->oob_poi : NULL;
1669 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1673 static int brcmnand_write_page_raw(struct mtd_info *mtd,
1674 struct nand_chip *chip, const uint8_t *buf,
1675 int oob_required, int page)
1677 struct brcmnand_host *host = chip->priv;
1678 void *oob = oob_required ? chip->oob_poi : NULL;
1680 brcmnand_set_ecc_enabled(host, 0);
1681 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1682 brcmnand_set_ecc_enabled(host, 1);
1686 static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1689 return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1690 NULL, chip->oob_poi);
1693 static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1696 struct brcmnand_host *host = chip->priv;
1699 brcmnand_set_ecc_enabled(host, 0);
1700 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1701 (u8 *)chip->oob_poi);
1702 brcmnand_set_ecc_enabled(host, 1);
1707 /***********************************************************************
1708 * Per-CS setup (1 NAND device)
1709 ***********************************************************************/
1711 static int brcmnand_set_cfg(struct brcmnand_host *host,
1712 struct brcmnand_cfg *cfg)
1714 struct brcmnand_controller *ctrl = host->ctrl;
1715 struct nand_chip *chip = &host->chip;
1716 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1717 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1718 BRCMNAND_CS_CFG_EXT);
1719 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1720 BRCMNAND_CS_ACC_CONTROL);
1721 u8 block_size = 0, page_size = 0, device_size = 0;
1724 if (ctrl->block_sizes) {
1727 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
1728 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
1733 dev_warn(ctrl->dev, "invalid block size %u\n",
1738 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
1741 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
1742 cfg->block_size > ctrl->max_block_size)) {
1743 dev_warn(ctrl->dev, "invalid block size %u\n",
1748 if (ctrl->page_sizes) {
1751 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
1752 if (ctrl->page_sizes[i] == cfg->page_size) {
1757 dev_warn(ctrl->dev, "invalid page size %u\n",
1762 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
1765 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
1766 cfg->page_size > ctrl->max_page_size)) {
1767 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
1771 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
1772 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
1773 (unsigned long long)cfg->device_size);
1776 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
1778 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
1779 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
1780 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
1781 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
1782 (device_size << CFG_DEVICE_SIZE_SHIFT);
1783 if (cfg_offs == cfg_ext_offs) {
1784 tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
1785 (block_size << CFG_BLK_SIZE_SHIFT);
1786 nand_writereg(ctrl, cfg_offs, tmp);
1788 nand_writereg(ctrl, cfg_offs, tmp);
1789 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
1790 (block_size << CFG_EXT_BLK_SIZE_SHIFT);
1791 nand_writereg(ctrl, cfg_ext_offs, tmp);
1794 tmp = nand_readreg(ctrl, acc_control_offs);
1795 tmp &= ~brcmnand_ecc_level_mask(ctrl);
1796 tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
1797 tmp &= ~brcmnand_spare_area_mask(ctrl);
1798 tmp |= cfg->spare_area_size;
1799 nand_writereg(ctrl, acc_control_offs, tmp);
1801 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
1803 /* threshold = ceil(BCH-level * 0.75) */
1804 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
1809 static void brcmnand_print_cfg(char *buf, struct brcmnand_cfg *cfg)
1812 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
1813 (unsigned long long)cfg->device_size >> 20,
1814 cfg->block_size >> 10,
1815 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
1816 cfg->page_size >= 1024 ? "KiB" : "B",
1817 cfg->spare_area_size, cfg->device_width);
1819 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
1820 if (is_hamming_ecc(cfg))
1821 sprintf(buf, ", Hamming ECC");
1822 else if (cfg->sector_size_1k)
1823 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
1825 sprintf(buf, ", BCH-%u", cfg->ecc_level);
1829 * Minimum number of bytes to address a page. Calculated as:
1830 * roundup(log2(size / page-size) / 8)
1832 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
1833 * OK because many other things will break if 'size' is irregular...
1835 static inline int get_blk_adr_bytes(u64 size, u32 writesize)
1837 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
1840 static int brcmnand_setup_dev(struct brcmnand_host *host)
1842 struct mtd_info *mtd = &host->mtd;
1843 struct nand_chip *chip = &host->chip;
1844 struct brcmnand_controller *ctrl = host->ctrl;
1845 struct brcmnand_cfg *cfg = &host->hwcfg;
1847 u32 offs, tmp, oob_sector;
1850 memset(cfg, 0, sizeof(*cfg));
1852 ret = of_property_read_u32(chip->flash_node,
1853 "brcm,nand-oob-sector-size",
1856 /* Use detected size */
1857 cfg->spare_area_size = mtd->oobsize /
1858 (mtd->writesize >> FC_SHIFT);
1860 cfg->spare_area_size = oob_sector;
1862 if (cfg->spare_area_size > ctrl->max_oob)
1863 cfg->spare_area_size = ctrl->max_oob;
1865 * Set oobsize to be consistent with controller's spare_area_size, as
1866 * the rest is inaccessible.
1868 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
1870 cfg->device_size = mtd->size;
1871 cfg->block_size = mtd->erasesize;
1872 cfg->page_size = mtd->writesize;
1873 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
1874 cfg->col_adr_bytes = 2;
1875 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
1877 switch (chip->ecc.size) {
1879 if (chip->ecc.strength == 1) /* Hamming */
1880 cfg->ecc_level = 15;
1882 cfg->ecc_level = chip->ecc.strength;
1883 cfg->sector_size_1k = 0;
1886 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
1887 dev_err(ctrl->dev, "1KB sectors not supported\n");
1890 if (chip->ecc.strength & 0x1) {
1892 "odd ECC not supported with 1KB sectors\n");
1896 cfg->ecc_level = chip->ecc.strength >> 1;
1897 cfg->sector_size_1k = 1;
1900 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
1905 cfg->ful_adr_bytes = cfg->blk_adr_bytes;
1906 if (mtd->writesize > 512)
1907 cfg->ful_adr_bytes += cfg->col_adr_bytes;
1909 cfg->ful_adr_bytes += 1;
1911 ret = brcmnand_set_cfg(host, cfg);
1915 brcmnand_set_ecc_enabled(host, 1);
1917 brcmnand_print_cfg(msg, cfg);
1918 dev_info(ctrl->dev, "detected %s\n", msg);
1920 /* Configure ACC_CONTROL */
1921 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
1922 tmp = nand_readreg(ctrl, offs);
1923 tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
1924 tmp &= ~ACC_CONTROL_RD_ERASED;
1925 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
1926 if (ctrl->features & BRCMNAND_HAS_PREFETCH)
1927 tmp &= ~ACC_CONTROL_PREFETCH;
1929 nand_writereg(ctrl, offs, tmp);
1934 static int brcmnand_init_cs(struct brcmnand_host *host)
1936 struct brcmnand_controller *ctrl = host->ctrl;
1937 struct device_node *dn = host->of_node;
1938 struct platform_device *pdev = host->pdev;
1939 struct mtd_info *mtd;
1940 struct nand_chip *chip;
1943 struct mtd_part_parser_data ppdata = { .of_node = dn };
1945 ret = of_property_read_u32(dn, "reg", &host->cs);
1947 dev_err(&pdev->dev, "can't get chip-select\n");
1954 chip->flash_node = dn;
1957 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
1959 mtd->owner = THIS_MODULE;
1960 mtd->dev.parent = &pdev->dev;
1962 chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
1963 chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
1965 chip->cmd_ctrl = brcmnand_cmd_ctrl;
1966 chip->cmdfunc = brcmnand_cmdfunc;
1967 chip->waitfunc = brcmnand_waitfunc;
1968 chip->read_byte = brcmnand_read_byte;
1969 chip->read_buf = brcmnand_read_buf;
1970 chip->write_buf = brcmnand_write_buf;
1972 chip->ecc.mode = NAND_ECC_HW;
1973 chip->ecc.read_page = brcmnand_read_page;
1974 chip->ecc.read_subpage = brcmnand_read_subpage;
1975 chip->ecc.write_page = brcmnand_write_page;
1976 chip->ecc.read_page_raw = brcmnand_read_page_raw;
1977 chip->ecc.write_page_raw = brcmnand_write_page_raw;
1978 chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
1979 chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
1980 chip->ecc.read_oob = brcmnand_read_oob;
1981 chip->ecc.write_oob = brcmnand_write_oob;
1983 chip->controller = &ctrl->controller;
1986 * The bootloader might have configured 16bit mode but
1987 * NAND READID command only works in 8bit mode. We force
1988 * 8bit mode here to ensure that NAND READID commands works.
1990 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1991 nand_writereg(ctrl, cfg_offs,
1992 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
1994 if (nand_scan_ident(mtd, 1, NULL))
1997 chip->options |= NAND_NO_SUBPAGE_WRITE;
1999 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
2000 * to/from, and have nand_base pass us a bounce buffer instead, as
2003 chip->options |= NAND_USE_BOUNCE_BUFFER;
2005 if (of_get_nand_on_flash_bbt(dn))
2006 chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
2008 if (brcmnand_setup_dev(host))
2011 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2012 /* only use our internal HW threshold */
2013 mtd->bitflip_threshold = 1;
2015 chip->ecc.layout = brcmstb_choose_ecc_layout(host);
2016 if (!chip->ecc.layout)
2019 if (nand_scan_tail(mtd))
2022 return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
2025 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
2028 struct brcmnand_controller *ctrl = host->ctrl;
2029 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2030 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2031 BRCMNAND_CS_CFG_EXT);
2032 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2033 BRCMNAND_CS_ACC_CONTROL);
2034 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2035 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2038 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2039 if (cfg_offs != cfg_ext_offs)
2040 nand_writereg(ctrl, cfg_ext_offs,
2041 host->hwcfg.config_ext);
2042 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2043 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2044 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2046 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2047 if (cfg_offs != cfg_ext_offs)
2048 host->hwcfg.config_ext =
2049 nand_readreg(ctrl, cfg_ext_offs);
2050 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2051 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2052 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2056 static int brcmnand_suspend(struct device *dev)
2058 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2059 struct brcmnand_host *host;
2061 list_for_each_entry(host, &ctrl->host_list, node)
2062 brcmnand_save_restore_cs_config(host, 0);
2064 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2065 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2066 ctrl->corr_stat_threshold =
2067 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2069 if (has_flash_dma(ctrl))
2070 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2075 static int brcmnand_resume(struct device *dev)
2077 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2078 struct brcmnand_host *host;
2080 if (has_flash_dma(ctrl)) {
2081 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2082 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2085 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2086 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2087 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2088 ctrl->corr_stat_threshold);
2090 /* Clear/re-enable interrupt */
2091 ctrl->soc->ctlrdy_ack(ctrl->soc);
2092 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2095 list_for_each_entry(host, &ctrl->host_list, node) {
2096 struct mtd_info *mtd = &host->mtd;
2097 struct nand_chip *chip = mtd->priv;
2099 brcmnand_save_restore_cs_config(host, 1);
2101 /* Reset the chip, required by some chips after power-up */
2102 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2108 const struct dev_pm_ops brcmnand_pm_ops = {
2109 .suspend = brcmnand_suspend,
2110 .resume = brcmnand_resume,
2112 EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2114 static const struct of_device_id brcmnand_of_match[] = {
2115 { .compatible = "brcm,brcmnand-v4.0" },
2116 { .compatible = "brcm,brcmnand-v5.0" },
2117 { .compatible = "brcm,brcmnand-v6.0" },
2118 { .compatible = "brcm,brcmnand-v6.1" },
2119 { .compatible = "brcm,brcmnand-v7.0" },
2120 { .compatible = "brcm,brcmnand-v7.1" },
2123 MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2125 /***********************************************************************
2126 * Platform driver setup (per controller)
2127 ***********************************************************************/
2129 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2131 struct device *dev = &pdev->dev;
2132 struct device_node *dn = dev->of_node, *child;
2133 struct brcmnand_controller *ctrl;
2134 struct resource *res;
2137 /* We only support device-tree instantiation */
2141 if (!of_match_node(brcmnand_of_match, dn))
2144 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2148 dev_set_drvdata(dev, ctrl);
2151 init_completion(&ctrl->done);
2152 init_completion(&ctrl->dma_done);
2153 spin_lock_init(&ctrl->controller.lock);
2154 init_waitqueue_head(&ctrl->controller.wq);
2155 INIT_LIST_HEAD(&ctrl->host_list);
2157 /* NAND register range */
2158 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2159 ctrl->nand_base = devm_ioremap_resource(dev, res);
2160 if (IS_ERR(ctrl->nand_base))
2161 return PTR_ERR(ctrl->nand_base);
2163 /* Initialize NAND revision */
2164 ret = brcmnand_revision_init(ctrl);
2169 * Most chips have this cache at a fixed offset within 'nand' block.
2170 * Some must specify this region separately.
2172 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2174 ctrl->nand_fc = devm_ioremap_resource(dev, res);
2175 if (IS_ERR(ctrl->nand_fc))
2176 return PTR_ERR(ctrl->nand_fc);
2178 ctrl->nand_fc = ctrl->nand_base +
2179 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2183 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2185 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2186 if (IS_ERR(ctrl->flash_dma_base))
2187 return PTR_ERR(ctrl->flash_dma_base);
2189 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2190 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2192 /* Allocate descriptor(s) */
2193 ctrl->dma_desc = dmam_alloc_coherent(dev,
2194 sizeof(*ctrl->dma_desc),
2195 &ctrl->dma_pa, GFP_KERNEL);
2196 if (!ctrl->dma_desc)
2199 ctrl->dma_irq = platform_get_irq(pdev, 1);
2200 if ((int)ctrl->dma_irq < 0) {
2201 dev_err(dev, "missing FLASH_DMA IRQ\n");
2205 ret = devm_request_irq(dev, ctrl->dma_irq,
2206 brcmnand_dma_irq, 0, DRV_NAME,
2209 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2210 ctrl->dma_irq, ret);
2214 dev_info(dev, "enabling FLASH_DMA\n");
2217 /* Disable automatic device ID config, direct addressing */
2218 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2219 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2220 /* Disable XOR addressing */
2221 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2223 if (ctrl->features & BRCMNAND_HAS_WP) {
2224 /* Permanently disable write protection */
2226 brcmnand_set_wp(ctrl, false);
2232 ctrl->irq = platform_get_irq(pdev, 0);
2233 if ((int)ctrl->irq < 0) {
2234 dev_err(dev, "no IRQ defined\n");
2239 * Some SoCs integrate this controller (e.g., its interrupt bits) in
2245 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2248 /* Enable interrupt */
2249 ctrl->soc->ctlrdy_ack(ctrl->soc);
2250 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2252 /* Use standard interrupt infrastructure */
2253 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2257 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2262 for_each_available_child_of_node(dn, child) {
2263 if (of_device_is_compatible(child, "brcm,nandcs")) {
2264 struct brcmnand_host *host;
2266 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2271 host->of_node = child;
2273 ret = brcmnand_init_cs(host);
2275 continue; /* Try all chip-selects */
2277 list_add_tail(&host->node, &ctrl->host_list);
2281 /* No chip-selects could initialize properly */
2282 if (list_empty(&ctrl->host_list))
2287 EXPORT_SYMBOL_GPL(brcmnand_probe);
2289 int brcmnand_remove(struct platform_device *pdev)
2291 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2292 struct brcmnand_host *host;
2294 list_for_each_entry(host, &ctrl->host_list, node)
2295 nand_release(&host->mtd);
2297 dev_set_drvdata(&pdev->dev, NULL);
2301 EXPORT_SYMBOL_GPL(brcmnand_remove);
2303 MODULE_LICENSE("GPL v2");
2304 MODULE_AUTHOR("Kevin Cernekee");
2305 MODULE_AUTHOR("Brian Norris");
2306 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2307 MODULE_ALIAS("platform:brcmnand");