drivers/mtd/nand/brcmnand/brcmnand.c

   1 /*
   2  * Copyright © 2010-2015 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/version.h>
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/err.h>
  22 #include <linux/completion.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/ioport.h>
  27 #include <linux/bug.h>
  28 #include <linux/kernel.h>
  29 #include <linux/bitops.h>
  30 #include <linux/mm.h>
  31 #include <linux/mtd/mtd.h>
  32 #include <linux/mtd/nand.h>
  33 #include <linux/mtd/partitions.h>
  34 #include <linux/of.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/slab.h>
  37 #include <linux/list.h>
  38 #include <linux/log2.h>
  39
  40 #include "brcmnand.h"
  41
  42 /*
  43  * This flag controls if WP stays on between erase/write commands to mitigate
  44  * flash corruption due to power glitches. Values:
  45  * 0: NAND_WP is not used or not available
  46  * 1: NAND_WP is set by default, cleared for erase/write operations
  47  * 2: NAND_WP is always cleared
  48  */
  49 static int wp_on = 1;
  50 module_param(wp_on, int, 0444);
  51
  52 /***********************************************************************
  53  * Definitions
  54  ***********************************************************************/
  55
  56 #define DRV_NAME                        "brcmnand"
  57
  58 #define CMD_NULL                        0x00
  59 #define CMD_PAGE_READ                   0x01
  60 #define CMD_SPARE_AREA_READ             0x02
  61 #define CMD_STATUS_READ                 0x03
  62 #define CMD_PROGRAM_PAGE                0x04
  63 #define CMD_PROGRAM_SPARE_AREA          0x05
  64 #define CMD_COPY_BACK                   0x06
  65 #define CMD_DEVICE_ID_READ              0x07
  66 #define CMD_BLOCK_ERASE                 0x08
  67 #define CMD_FLASH_RESET                 0x09
  68 #define CMD_BLOCKS_LOCK                 0x0a
  69 #define CMD_BLOCKS_LOCK_DOWN            0x0b
  70 #define CMD_BLOCKS_UNLOCK               0x0c
  71 #define CMD_READ_BLOCKS_LOCK_STATUS     0x0d
  72 #define CMD_PARAMETER_READ              0x0e
  73 #define CMD_PARAMETER_CHANGE_COL        0x0f
  74 #define CMD_LOW_LEVEL_OP                0x10
  75
  76 struct brcm_nand_dma_desc {
  77         u32 next_desc;
  78         u32 next_desc_ext;
  79         u32 cmd_irq;
  80         u32 dram_addr;
  81         u32 dram_addr_ext;
  82         u32 tfr_len;
  83         u32 total_len;
  84         u32 flash_addr;
  85         u32 flash_addr_ext;
  86         u32 cs;
  87         u32 pad2[5];
  88         u32 status_valid;
  89 } __packed;
  90
  91 /* Bitfields for brcm_nand_dma_desc::status_valid */
  92 #define FLASH_DMA_ECC_ERROR     (1 << 8)
  93 #define FLASH_DMA_CORR_ERROR    (1 << 9)
  94
  95 /* 512B flash cache in the NAND controller HW */
  96 #define FC_SHIFT                9U
  97 #define FC_BYTES                512U
  98 #define FC_WORDS                (FC_BYTES >> 2)
  99
 100 #define BRCMNAND_MIN_PAGESIZE   512
 101 #define BRCMNAND_MIN_BLOCKSIZE  (8 * 1024)
 102 #define BRCMNAND_MIN_DEVSIZE    (4ULL * 1024 * 1024)
 103
 104 #define NAND_CTRL_RDY                   (INTFC_CTLR_READY | INTFC_FLASH_READY)
 105 #define NAND_POLL_STATUS_TIMEOUT_MS     100
 106
 107 /* Controller feature flags */
 108 enum {
 109         BRCMNAND_HAS_1K_SECTORS                 = BIT(0),
 110         BRCMNAND_HAS_PREFETCH                   = BIT(1),
 111         BRCMNAND_HAS_CACHE_MODE                 = BIT(2),
 112         BRCMNAND_HAS_WP                         = BIT(3),
 113 };
 114
 115 struct brcmnand_controller {
 116         struct device           *dev;
 117         struct nand_hw_control  controller;
 118         void __iomem            *nand_base;
 119         void __iomem            *nand_fc; /* flash cache */
 120         void __iomem            *flash_dma_base;
 121         unsigned int            irq;
 122         unsigned int            dma_irq;
 123         int                     nand_version;
 124
 125         /* Some SoCs provide custom interrupt status register(s) */
 126         struct brcmnand_soc     *soc;
 127
 128         /* Some SoCs have a gateable clock for the controller */
 129         struct clk              *clk;
 130
 131         int                     cmd_pending;
 132         bool                    dma_pending;
 133         struct completion       done;
 134         struct completion       dma_done;
 135
 136         /* List of NAND hosts (one for each chip-select) */
 137         struct list_head host_list;
 138
 139         struct brcm_nand_dma_desc *dma_desc;
 140         dma_addr_t              dma_pa;
 141
 142         /* in-memory cache of the FLASH_CACHE, used only for some commands */
 143         u8                      flash_cache[FC_BYTES];
 144
 145         /* Controller revision details */
 146         const u16               *reg_offsets;
 147         unsigned int            reg_spacing; /* between CS1, CS2, ... regs */
 148         const u8                *cs_offsets; /* within each chip-select */
 149         const u8                *cs0_offsets; /* within CS0, if different */
 150         unsigned int            max_block_size;
 151         const unsigned int      *block_sizes;
 152         unsigned int            max_page_size;
 153         const unsigned int      *page_sizes;
 154         unsigned int            max_oob;
 155         u32                     features;
 156
 157         /* for low-power standby/resume only */
 158         u32                     nand_cs_nand_select;
 159         u32                     nand_cs_nand_xor;
 160         u32                     corr_stat_threshold;
 161         u32                     flash_dma_mode;
 162 };
 163
 164 struct brcmnand_cfg {
 165         u64                     device_size;
 166         unsigned int            block_size;
 167         unsigned int            page_size;
 168         unsigned int            spare_area_size;
 169         unsigned int            device_width;
 170         unsigned int            col_adr_bytes;
 171         unsigned int            blk_adr_bytes;
 172         unsigned int            ful_adr_bytes;
 173         unsigned int            sector_size_1k;
 174         unsigned int            ecc_level;
 175         /* use for low-power standby/resume only */
 176         u32                     acc_control;
 177         u32                     config;
 178         u32                     config_ext;
 179         u32                     timing_1;
 180         u32                     timing_2;
 181 };
 182
 183 struct brcmnand_host {
 184         struct list_head        node;
 185
 186         struct nand_chip        chip;
 187         struct platform_device  *pdev;
 188         int                     cs;
 189
 190         unsigned int            last_cmd;
 191         unsigned int            last_byte;
 192         u64                     last_addr;
 193         struct brcmnand_cfg     hwcfg;
 194         struct brcmnand_controller *ctrl;
 195 };
 196
 197 enum brcmnand_reg {
 198         BRCMNAND_CMD_START = 0,
 199         BRCMNAND_CMD_EXT_ADDRESS,
 200         BRCMNAND_CMD_ADDRESS,
 201         BRCMNAND_INTFC_STATUS,
 202         BRCMNAND_CS_SELECT,
 203         BRCMNAND_CS_XOR,
 204         BRCMNAND_LL_OP,
 205         BRCMNAND_CS0_BASE,
 206         BRCMNAND_CS1_BASE,              /* CS1 regs, if non-contiguous */
 207         BRCMNAND_CORR_THRESHOLD,
 208         BRCMNAND_CORR_THRESHOLD_EXT,
 209         BRCMNAND_UNCORR_COUNT,
 210         BRCMNAND_CORR_COUNT,
 211         BRCMNAND_CORR_EXT_ADDR,
 212         BRCMNAND_CORR_ADDR,
 213         BRCMNAND_UNCORR_EXT_ADDR,
 214         BRCMNAND_UNCORR_ADDR,
 215         BRCMNAND_SEMAPHORE,
 216         BRCMNAND_ID,
 217         BRCMNAND_ID_EXT,
 218         BRCMNAND_LL_RDATA,
 219         BRCMNAND_OOB_READ_BASE,
 220         BRCMNAND_OOB_READ_10_BASE,      /* offset 0x10, if non-contiguous */
 221         BRCMNAND_OOB_WRITE_BASE,
 222         BRCMNAND_OOB_WRITE_10_BASE,     /* offset 0x10, if non-contiguous */
 223         BRCMNAND_FC_BASE,
 224 };
 225
 226 /* BRCMNAND v4.0 */
 227 static const u16 brcmnand_regs_v40[] = {
 228         [BRCMNAND_CMD_START]            =  0x04,
 229         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 230         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 231         [BRCMNAND_INTFC_STATUS]         =  0x6c,
 232         [BRCMNAND_CS_SELECT]            =  0x14,
 233         [BRCMNAND_CS_XOR]               =  0x18,
 234         [BRCMNAND_LL_OP]                = 0x178,
 235         [BRCMNAND_CS0_BASE]             =  0x40,
 236         [BRCMNAND_CS1_BASE]             =  0xd0,
 237         [BRCMNAND_CORR_THRESHOLD]       =  0x84,
 238         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
 239         [BRCMNAND_UNCORR_COUNT]         =     0,
 240         [BRCMNAND_CORR_COUNT]           =     0,
 241         [BRCMNAND_CORR_EXT_ADDR]        =  0x70,
 242         [BRCMNAND_CORR_ADDR]            =  0x74,
 243         [BRCMNAND_UNCORR_EXT_ADDR]      =  0x78,
 244         [BRCMNAND_UNCORR_ADDR]          =  0x7c,
 245         [BRCMNAND_SEMAPHORE]            =  0x58,
 246         [BRCMNAND_ID]                   =  0x60,
 247         [BRCMNAND_ID_EXT]               =  0x64,
 248         [BRCMNAND_LL_RDATA]             = 0x17c,
 249         [BRCMNAND_OOB_READ_BASE]        =  0x20,
 250         [BRCMNAND_OOB_READ_10_BASE]     = 0x130,
 251         [BRCMNAND_OOB_WRITE_BASE]       =  0x30,
 252         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 253         [BRCMNAND_FC_BASE]              = 0x200,
 254 };
 255
 256 /* BRCMNAND v5.0 */
 257 static const u16 brcmnand_regs_v50[] = {
 258         [BRCMNAND_CMD_START]            =  0x04,
 259         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 260         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 261         [BRCMNAND_INTFC_STATUS]         =  0x6c,
 262         [BRCMNAND_CS_SELECT]            =  0x14,
 263         [BRCMNAND_CS_XOR]               =  0x18,
 264         [BRCMNAND_LL_OP]                = 0x178,
 265         [BRCMNAND_CS0_BASE]             =  0x40,
 266         [BRCMNAND_CS1_BASE]             =  0xd0,
 267         [BRCMNAND_CORR_THRESHOLD]       =  0x84,
 268         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
 269         [BRCMNAND_UNCORR_COUNT]         =     0,
 270         [BRCMNAND_CORR_COUNT]           =     0,
 271         [BRCMNAND_CORR_EXT_ADDR]        =  0x70,
 272         [BRCMNAND_CORR_ADDR]            =  0x74,
 273         [BRCMNAND_UNCORR_EXT_ADDR]      =  0x78,
 274         [BRCMNAND_UNCORR_ADDR]          =  0x7c,
 275         [BRCMNAND_SEMAPHORE]            =  0x58,
 276         [BRCMNAND_ID]                   =  0x60,
 277         [BRCMNAND_ID_EXT]               =  0x64,
 278         [BRCMNAND_LL_RDATA]             = 0x17c,
 279         [BRCMNAND_OOB_READ_BASE]        =  0x20,
 280         [BRCMNAND_OOB_READ_10_BASE]     = 0x130,
 281         [BRCMNAND_OOB_WRITE_BASE]       =  0x30,
 282         [BRCMNAND_OOB_WRITE_10_BASE]    = 0x140,
 283         [BRCMNAND_FC_BASE]              = 0x200,
 284 };
 285
 286 /* BRCMNAND v6.0 - v7.1 */
 287 static const u16 brcmnand_regs_v60[] = {
 288         [BRCMNAND_CMD_START]            =  0x04,
 289         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 290         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 291         [BRCMNAND_INTFC_STATUS]         =  0x14,
 292         [BRCMNAND_CS_SELECT]            =  0x18,
 293         [BRCMNAND_CS_XOR]               =  0x1c,
 294         [BRCMNAND_LL_OP]                =  0x20,
 295         [BRCMNAND_CS0_BASE]             =  0x50,
 296         [BRCMNAND_CS1_BASE]             =     0,
 297         [BRCMNAND_CORR_THRESHOLD]       =  0xc0,
 298         [BRCMNAND_CORR_THRESHOLD_EXT]   =  0xc4,
 299         [BRCMNAND_UNCORR_COUNT]         =  0xfc,
 300         [BRCMNAND_CORR_COUNT]           = 0x100,
 301         [BRCMNAND_CORR_EXT_ADDR]        = 0x10c,
 302         [BRCMNAND_CORR_ADDR]            = 0x110,
 303         [BRCMNAND_UNCORR_EXT_ADDR]      = 0x114,
 304         [BRCMNAND_UNCORR_ADDR]          = 0x118,
 305         [BRCMNAND_SEMAPHORE]            = 0x150,
 306         [BRCMNAND_ID]                   = 0x194,
 307         [BRCMNAND_ID_EXT]               = 0x198,
 308         [BRCMNAND_LL_RDATA]             = 0x19c,
 309         [BRCMNAND_OOB_READ_BASE]        = 0x200,
 310         [BRCMNAND_OOB_READ_10_BASE]     =     0,
 311         [BRCMNAND_OOB_WRITE_BASE]       = 0x280,
 312         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 313         [BRCMNAND_FC_BASE]              = 0x400,
 314 };
 315
 316 /* BRCMNAND v7.1 */
 317 static const u16 brcmnand_regs_v71[] = {
 318         [BRCMNAND_CMD_START]            =  0x04,
 319         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 320         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 321         [BRCMNAND_INTFC_STATUS]         =  0x14,
 322         [BRCMNAND_CS_SELECT]            =  0x18,
 323         [BRCMNAND_CS_XOR]               =  0x1c,
 324         [BRCMNAND_LL_OP]                =  0x20,
 325         [BRCMNAND_CS0_BASE]             =  0x50,
 326         [BRCMNAND_CS1_BASE]             =     0,
 327         [BRCMNAND_CORR_THRESHOLD]       =  0xdc,
 328         [BRCMNAND_CORR_THRESHOLD_EXT]   =  0xe0,
 329         [BRCMNAND_UNCORR_COUNT]         =  0xfc,
 330         [BRCMNAND_CORR_COUNT]           = 0x100,
 331         [BRCMNAND_CORR_EXT_ADDR]        = 0x10c,
 332         [BRCMNAND_CORR_ADDR]            = 0x110,
 333         [BRCMNAND_UNCORR_EXT_ADDR]      = 0x114,
 334         [BRCMNAND_UNCORR_ADDR]          = 0x118,
 335         [BRCMNAND_SEMAPHORE]            = 0x150,
 336         [BRCMNAND_ID]                   = 0x194,
 337         [BRCMNAND_ID_EXT]               = 0x198,
 338         [BRCMNAND_LL_RDATA]             = 0x19c,
 339         [BRCMNAND_OOB_READ_BASE]        = 0x200,
 340         [BRCMNAND_OOB_READ_10_BASE]     =     0,
 341         [BRCMNAND_OOB_WRITE_BASE]       = 0x280,
 342         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 343         [BRCMNAND_FC_BASE]              = 0x400,
 344 };
 345
 346 /* BRCMNAND v7.2 */
 347 static const u16 brcmnand_regs_v72[] = {
 348         [BRCMNAND_CMD_START]            =  0x04,
 349         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 350         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 351         [BRCMNAND_INTFC_STATUS]         =  0x14,
 352         [BRCMNAND_CS_SELECT]            =  0x18,
 353         [BRCMNAND_CS_XOR]               =  0x1c,
 354         [BRCMNAND_LL_OP]                =  0x20,
 355         [BRCMNAND_CS0_BASE]             =  0x50,
 356         [BRCMNAND_CS1_BASE]             =     0,
 357         [BRCMNAND_CORR_THRESHOLD]       =  0xdc,
 358         [BRCMNAND_CORR_THRESHOLD_EXT]   =  0xe0,
 359         [BRCMNAND_UNCORR_COUNT]         =  0xfc,
 360         [BRCMNAND_CORR_COUNT]           = 0x100,
 361         [BRCMNAND_CORR_EXT_ADDR]        = 0x10c,
 362         [BRCMNAND_CORR_ADDR]            = 0x110,
 363         [BRCMNAND_UNCORR_EXT_ADDR]      = 0x114,
 364         [BRCMNAND_UNCORR_ADDR]          = 0x118,
 365         [BRCMNAND_SEMAPHORE]            = 0x150,
 366         [BRCMNAND_ID]                   = 0x194,
 367         [BRCMNAND_ID_EXT]               = 0x198,
 368         [BRCMNAND_LL_RDATA]             = 0x19c,
 369         [BRCMNAND_OOB_READ_BASE]        = 0x200,
 370         [BRCMNAND_OOB_READ_10_BASE]     =     0,
 371         [BRCMNAND_OOB_WRITE_BASE]       = 0x400,
 372         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 373         [BRCMNAND_FC_BASE]              = 0x600,
 374 };
 375
 376 enum brcmnand_cs_reg {
 377         BRCMNAND_CS_CFG_EXT = 0,
 378         BRCMNAND_CS_CFG,
 379         BRCMNAND_CS_ACC_CONTROL,
 380         BRCMNAND_CS_TIMING1,
 381         BRCMNAND_CS_TIMING2,
 382 };
 383
 384 /* Per chip-select offsets for v7.1 */
 385 static const u8 brcmnand_cs_offsets_v71[] = {
 386         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 387         [BRCMNAND_CS_CFG_EXT]           = 0x04,
 388         [BRCMNAND_CS_CFG]               = 0x08,
 389         [BRCMNAND_CS_TIMING1]           = 0x0c,
 390         [BRCMNAND_CS_TIMING2]           = 0x10,
 391 };
 392
 393 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
 394 static const u8 brcmnand_cs_offsets[] = {
 395         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 396         [BRCMNAND_CS_CFG_EXT]           = 0x04,
 397         [BRCMNAND_CS_CFG]               = 0x04,
 398         [BRCMNAND_CS_TIMING1]           = 0x08,
 399         [BRCMNAND_CS_TIMING2]           = 0x0c,
 400 };
 401
 402 /* Per chip-select offset for <= v5.0 on CS0 only */
 403 static const u8 brcmnand_cs_offsets_cs0[] = {
 404         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 405         [BRCMNAND_CS_CFG_EXT]           = 0x08,
 406         [BRCMNAND_CS_CFG]               = 0x08,
 407         [BRCMNAND_CS_TIMING1]           = 0x10,
 408         [BRCMNAND_CS_TIMING2]           = 0x14,
 409 };
 410
 411 /*
 412  * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
 413  * one config register, but once the bitfields overflowed, newer controllers
 414  * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
 415  */
 416 enum {
 417         CFG_BLK_ADR_BYTES_SHIFT         = 8,
 418         CFG_COL_ADR_BYTES_SHIFT         = 12,
 419         CFG_FUL_ADR_BYTES_SHIFT         = 16,
 420         CFG_BUS_WIDTH_SHIFT             = 23,
 421         CFG_BUS_WIDTH                   = BIT(CFG_BUS_WIDTH_SHIFT),
 422         CFG_DEVICE_SIZE_SHIFT           = 24,
 423
 424         /* Only for pre-v7.1 (with no CFG_EXT register) */
 425         CFG_PAGE_SIZE_SHIFT             = 20,
 426         CFG_BLK_SIZE_SHIFT              = 28,
 427
 428         /* Only for v7.1+ (with CFG_EXT register) */
 429         CFG_EXT_PAGE_SIZE_SHIFT         = 0,
 430         CFG_EXT_BLK_SIZE_SHIFT          = 4,
 431 };
 432
 433 /* BRCMNAND_INTFC_STATUS */
 434 enum {
 435         INTFC_FLASH_STATUS              = GENMASK(7, 0),
 436
 437         INTFC_ERASED                    = BIT(27),
 438         INTFC_OOB_VALID                 = BIT(28),
 439         INTFC_CACHE_VALID               = BIT(29),
 440         INTFC_FLASH_READY               = BIT(30),
 441         INTFC_CTLR_READY                = BIT(31),
 442 };
 443
 444 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
 445 {
 446         return brcmnand_readl(ctrl->nand_base + offs);
 447 }
 448
 449 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
 450                                  u32 val)
 451 {
 452         brcmnand_writel(val, ctrl->nand_base + offs);
 453 }
 454
 455 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
 456 {
 457         static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
 458         static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
 459         static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
 460
 461         ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
 462
 463         /* Only support v4.0+? */
 464         if (ctrl->nand_version < 0x0400) {
 465                 dev_err(ctrl->dev, "version %#x not supported\n",
 466                         ctrl->nand_version);
 467                 return -ENODEV;
 468         }
 469
 470         /* Register offsets */
 471         if (ctrl->nand_version >= 0x0702)
 472                 ctrl->reg_offsets = brcmnand_regs_v72;
 473         else if (ctrl->nand_version >= 0x0701)
 474                 ctrl->reg_offsets = brcmnand_regs_v71;
 475         else if (ctrl->nand_version >= 0x0600)
 476                 ctrl->reg_offsets = brcmnand_regs_v60;
 477         else if (ctrl->nand_version >= 0x0500)
 478                 ctrl->reg_offsets = brcmnand_regs_v50;
 479         else if (ctrl->nand_version >= 0x0400)
 480                 ctrl->reg_offsets = brcmnand_regs_v40;
 481
 482         /* Chip-select stride */
 483         if (ctrl->nand_version >= 0x0701)
 484                 ctrl->reg_spacing = 0x14;
 485         else
 486                 ctrl->reg_spacing = 0x10;
 487
 488         /* Per chip-select registers */
 489         if (ctrl->nand_version >= 0x0701) {
 490                 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
 491         } else {
 492                 ctrl->cs_offsets = brcmnand_cs_offsets;
 493
 494                 /* v3.3-5.0 have a different CS0 offset layout */
 495                 if (ctrl->nand_version >= 0x0303 &&
 496                     ctrl->nand_version <= 0x0500)
 497                         ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
 498         }
 499
 500         /* Page / block sizes */
 501         if (ctrl->nand_version >= 0x0701) {
 502                 /* >= v7.1 use nice power-of-2 values! */
 503                 ctrl->max_page_size = 16 * 1024;
 504                 ctrl->max_block_size = 2 * 1024 * 1024;
 505         } else {
 506                 ctrl->page_sizes = page_sizes;
 507                 if (ctrl->nand_version >= 0x0600)
 508                         ctrl->block_sizes = block_sizes_v6;
 509                 else
 510                         ctrl->block_sizes = block_sizes_v4;
 511
 512                 if (ctrl->nand_version < 0x0400) {
 513                         ctrl->max_page_size = 4096;
 514                         ctrl->max_block_size = 512 * 1024;
 515                 }
 516         }
 517
 518         /* Maximum spare area sector size (per 512B) */
 519         if (ctrl->nand_version >= 0x0702)
 520                 ctrl->max_oob = 128;
 521         else if (ctrl->nand_version >= 0x0600)
 522                 ctrl->max_oob = 64;
 523         else if (ctrl->nand_version >= 0x0500)
 524                 ctrl->max_oob = 32;
 525         else
 526                 ctrl->max_oob = 16;
 527
 528         /* v6.0 and newer (except v6.1) have prefetch support */
 529         if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
 530                 ctrl->features |= BRCMNAND_HAS_PREFETCH;
 531
 532         /*
 533          * v6.x has cache mode, but it's implemented differently. Ignore it for
 534          * now.
 535          */
 536         if (ctrl->nand_version >= 0x0700)
 537                 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
 538
 539         if (ctrl->nand_version >= 0x0500)
 540                 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
 541
 542         if (ctrl->nand_version >= 0x0700)
 543                 ctrl->features |= BRCMNAND_HAS_WP;
 544         else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
 545                 ctrl->features |= BRCMNAND_HAS_WP;
 546
 547         return 0;
 548 }
 549
 550 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
 551                 enum brcmnand_reg reg)
 552 {
 553         u16 offs = ctrl->reg_offsets[reg];
 554
 555         if (offs)
 556                 return nand_readreg(ctrl, offs);
 557         else
 558                 return 0;
 559 }
 560
 561 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
 562                                       enum brcmnand_reg reg, u32 val)
 563 {
 564         u16 offs = ctrl->reg_offsets[reg];
 565
 566         if (offs)
 567                 nand_writereg(ctrl, offs, val);
 568 }
 569
 570 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
 571                                     enum brcmnand_reg reg, u32 mask, unsigned
 572                                     int shift, u32 val)
 573 {
 574         u32 tmp = brcmnand_read_reg(ctrl, reg);
 575
 576         tmp &= ~mask;
 577         tmp |= val << shift;
 578         brcmnand_write_reg(ctrl, reg, tmp);
 579 }
 580
 581 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
 582 {
 583         return __raw_readl(ctrl->nand_fc + word * 4);
 584 }
 585
 586 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
 587                                      int word, u32 val)
 588 {
 589         __raw_writel(val, ctrl->nand_fc + word * 4);
 590 }
 591
 592 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
 593                                      enum brcmnand_cs_reg reg)
 594 {
 595         u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
 596         u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
 597         u8 cs_offs;
 598
 599         if (cs == 0 && ctrl->cs0_offsets)
 600                 cs_offs = ctrl->cs0_offsets[reg];
 601         else
 602                 cs_offs = ctrl->cs_offsets[reg];
 603
 604         if (cs && offs_cs1)
 605                 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
 606
 607         return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
 608 }
 609
 610 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
 611 {
 612         if (ctrl->nand_version < 0x0600)
 613                 return 1;
 614         return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
 615 }
 616
 617 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
 618 {
 619         struct brcmnand_controller *ctrl = host->ctrl;
 620         unsigned int shift = 0, bits;
 621         enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
 622         int cs = host->cs;
 623
 624         if (ctrl->nand_version >= 0x0702)
 625                 bits = 7;
 626         else if (ctrl->nand_version >= 0x0600)
 627                 bits = 6;
 628         else if (ctrl->nand_version >= 0x0500)
 629                 bits = 5;
 630         else
 631                 bits = 4;
 632
 633         if (ctrl->nand_version >= 0x0702) {
 634                 if (cs >= 4)
 635                         reg = BRCMNAND_CORR_THRESHOLD_EXT;
 636                 shift = (cs % 4) * bits;
 637         } else if (ctrl->nand_version >= 0x0600) {
 638                 if (cs >= 5)
 639                         reg = BRCMNAND_CORR_THRESHOLD_EXT;
 640                 shift = (cs % 5) * bits;
 641         }
 642         brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
 643 }
 644
 645 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
 646 {
 647         if (ctrl->nand_version < 0x0602)
 648                 return 24;
 649         return 0;
 650 }
 651
 652 /***********************************************************************
 653  * NAND ACC CONTROL bitfield
 654  *
 655  * Some bits have remained constant throughout hardware revision, while
 656  * others have shifted around.
 657  ***********************************************************************/
 658
 659 /* Constant for all versions (where supported) */
 660 enum {
 661         /* See BRCMNAND_HAS_CACHE_MODE */
 662         ACC_CONTROL_CACHE_MODE                          = BIT(22),
 663
 664         /* See BRCMNAND_HAS_PREFETCH */
 665         ACC_CONTROL_PREFETCH                            = BIT(23),
 666
 667         ACC_CONTROL_PAGE_HIT                            = BIT(24),
 668         ACC_CONTROL_WR_PREEMPT                          = BIT(25),
 669         ACC_CONTROL_PARTIAL_PAGE                        = BIT(26),
 670         ACC_CONTROL_RD_ERASED                           = BIT(27),
 671         ACC_CONTROL_FAST_PGM_RDIN                       = BIT(28),
 672         ACC_CONTROL_WR_ECC                              = BIT(30),
 673         ACC_CONTROL_RD_ECC                              = BIT(31),
 674 };
 675
 676 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
 677 {
 678         if (ctrl->nand_version >= 0x0702)
 679                 return GENMASK(7, 0);
 680         else if (ctrl->nand_version >= 0x0600)
 681                 return GENMASK(6, 0);
 682         else
 683                 return GENMASK(5, 0);
 684 }
 685
 686 #define NAND_ACC_CONTROL_ECC_SHIFT      16
 687 #define NAND_ACC_CONTROL_ECC_EXT_SHIFT  13
 688
 689 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
 690 {
 691         u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
 692
 693         mask <<= NAND_ACC_CONTROL_ECC_SHIFT;
 694
 695         /* v7.2 includes additional ECC levels */
 696         if (ctrl->nand_version >= 0x0702)
 697                 mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT;
 698
 699         return mask;
 700 }
 701
 702 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
 703 {
 704         struct brcmnand_controller *ctrl = host->ctrl;
 705         u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
 706         u32 acc_control = nand_readreg(ctrl, offs);
 707         u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
 708
 709         if (en) {
 710                 acc_control |= ecc_flags; /* enable RD/WR ECC */
 711                 acc_control |= host->hwcfg.ecc_level
 712                                << NAND_ACC_CONTROL_ECC_SHIFT;
 713         } else {
 714                 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
 715                 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
 716         }
 717
 718         nand_writereg(ctrl, offs, acc_control);
 719 }
 720
 721 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
 722 {
 723         if (ctrl->nand_version >= 0x0702)
 724                 return 9;
 725         else if (ctrl->nand_version >= 0x0600)
 726                 return 7;
 727         else if (ctrl->nand_version >= 0x0500)
 728                 return 6;
 729         else
 730                 return -1;
 731 }
 732
 733 static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
 734 {
 735         struct brcmnand_controller *ctrl = host->ctrl;
 736         int shift = brcmnand_sector_1k_shift(ctrl);
 737         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
 738                                                   BRCMNAND_CS_ACC_CONTROL);
 739
 740         if (shift < 0)
 741                 return 0;
 742
 743         return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
 744 }
 745
 746 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
 747 {
 748         struct brcmnand_controller *ctrl = host->ctrl;
 749         int shift = brcmnand_sector_1k_shift(ctrl);
 750         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
 751                                                   BRCMNAND_CS_ACC_CONTROL);
 752         u32 tmp;
 753
 754         if (shift < 0)
 755                 return;
 756
 757         tmp = nand_readreg(ctrl, acc_control_offs);
 758         tmp &= ~(1 << shift);
 759         tmp |= (!!val) << shift;
 760         nand_writereg(ctrl, acc_control_offs, tmp);
 761 }
 762
 763 /***********************************************************************
 764  * CS_NAND_SELECT
 765  ***********************************************************************/
 766
 767 enum {
 768         CS_SELECT_NAND_WP                       = BIT(29),
 769         CS_SELECT_AUTO_DEVICE_ID_CFG            = BIT(30),
 770 };
 771
 772 static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl,
 773                                     u32 mask, u32 expected_val,
 774                                     unsigned long timeout_ms)
 775 {
 776         unsigned long limit;
 777         u32 val;
 778
 779         if (!timeout_ms)
 780                 timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS;
 781
 782         limit = jiffies + msecs_to_jiffies(timeout_ms);
 783         do {
 784                 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
 785                 if ((val & mask) == expected_val)
 786                         return 0;
 787
 788                 cpu_relax();
 789         } while (time_after(limit, jiffies));
 790
 791         dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
 792                  expected_val, val & mask);
 793
 794         return -ETIMEDOUT;
 795 }
 796
 797 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
 798 {
 799         u32 val = en ? CS_SELECT_NAND_WP : 0;
 800
 801         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
 802 }
 803
 804 /***********************************************************************
 805  * Flash DMA
 806  ***********************************************************************/
 807
 808 enum flash_dma_reg {
 809         FLASH_DMA_REVISION              = 0x00,
 810         FLASH_DMA_FIRST_DESC            = 0x04,
 811         FLASH_DMA_FIRST_DESC_EXT        = 0x08,
 812         FLASH_DMA_CTRL                  = 0x0c,
 813         FLASH_DMA_MODE                  = 0x10,
 814         FLASH_DMA_STATUS                = 0x14,
 815         FLASH_DMA_INTERRUPT_DESC        = 0x18,
 816         FLASH_DMA_INTERRUPT_DESC_EXT    = 0x1c,
 817         FLASH_DMA_ERROR_STATUS          = 0x20,
 818         FLASH_DMA_CURRENT_DESC          = 0x24,
 819         FLASH_DMA_CURRENT_DESC_EXT      = 0x28,
 820 };
 821
 822 static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
 823 {
 824         return ctrl->flash_dma_base;
 825 }
 826
 827 static inline bool flash_dma_buf_ok(const void *buf)
 828 {
 829         return buf && !is_vmalloc_addr(buf) &&
 830                 likely(IS_ALIGNED((uintptr_t)buf, 4));
 831 }
 832
 833 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
 834                                     u32 val)
 835 {
 836         brcmnand_writel(val, ctrl->flash_dma_base + offs);
 837 }
 838
 839 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
 840 {
 841         return brcmnand_readl(ctrl->flash_dma_base + offs);
 842 }
 843
 844 /* Low-level operation types: command, address, write, or read */
 845 enum brcmnand_llop_type {
 846         LL_OP_CMD,
 847         LL_OP_ADDR,
 848         LL_OP_WR,
 849         LL_OP_RD,
 850 };
 851
 852 /***********************************************************************
 853  * Internal support functions
 854  ***********************************************************************/
 855
 856 static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl,
 857                                   struct brcmnand_cfg *cfg)
 858 {
 859         if (ctrl->nand_version <= 0x0701)
 860                 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
 861                         cfg->ecc_level == 15;
 862         else
 863                 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 &&
 864                         cfg->ecc_level == 15) ||
 865                         (cfg->spare_area_size == 28 && cfg->ecc_level == 16));
 866 }
 867
 868 /*
 869  * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
 870  * the layout/configuration.
 871  * Returns -ERRCODE on failure.
 872  */
 873 static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section,
 874                                           struct mtd_oob_region *oobregion)
 875 {
 876         struct nand_chip *chip = mtd_to_nand(mtd);
 877         struct brcmnand_host *host = nand_get_controller_data(chip);
 878         struct brcmnand_cfg *cfg = &host->hwcfg;
 879         int sas = cfg->spare_area_size << cfg->sector_size_1k;
 880         int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 881
 882         if (section >= sectors)
 883                 return -ERANGE;
 884
 885         oobregion->offset = (section * sas) + 6;
 886         oobregion->length = 3;
 887
 888         return 0;
 889 }
 890
 891 static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section,
 892                                            struct mtd_oob_region *oobregion)
 893 {
 894         struct nand_chip *chip = mtd_to_nand(mtd);
 895         struct brcmnand_host *host = nand_get_controller_data(chip);
 896         struct brcmnand_cfg *cfg = &host->hwcfg;
 897         int sas = cfg->spare_area_size << cfg->sector_size_1k;
 898         int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 899
 900         if (section >= sectors * 2)
 901                 return -ERANGE;
 902
 903         oobregion->offset = (section / 2) * sas;
 904
 905         if (section & 1) {
 906                 oobregion->offset += 9;
 907                 oobregion->length = 7;
 908         } else {
 909                 oobregion->length = 6;
 910
 911                 /* First sector of each page may have BBI */
 912                 if (!section) {
 913                         /*
 914                          * Small-page NAND use byte 6 for BBI while large-page
 915                          * NAND use bytes 0 and 1.
 916                          */
 917                         if (cfg->page_size > 512) {
 918                                 oobregion->offset += 2;
 919                                 oobregion->length -= 2;
 920                         } else {
 921                                 oobregion->length--;
 922                         }
 923                 }
 924         }
 925
 926         return 0;
 927 }
 928
 929 static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = {
 930         .ecc = brcmnand_hamming_ooblayout_ecc,
 931         .free = brcmnand_hamming_ooblayout_free,
 932 };
 933
 934 static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section,
 935                                       struct mtd_oob_region *oobregion)
 936 {
 937         struct nand_chip *chip = mtd_to_nand(mtd);
 938         struct brcmnand_host *host = nand_get_controller_data(chip);
 939         struct brcmnand_cfg *cfg = &host->hwcfg;
 940         int sas = cfg->spare_area_size << cfg->sector_size_1k;
 941         int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 942
 943         if (section >= sectors)
 944                 return -ERANGE;
 945
 946         oobregion->offset = (section * (sas + 1)) - chip->ecc.bytes;
 947         oobregion->length = chip->ecc.bytes;
 948
 949         return 0;
 950 }
 951
 952 static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section,
 953                                           struct mtd_oob_region *oobregion)
 954 {
 955         struct nand_chip *chip = mtd_to_nand(mtd);
 956         struct brcmnand_host *host = nand_get_controller_data(chip);
 957         struct brcmnand_cfg *cfg = &host->hwcfg;
 958         int sas = cfg->spare_area_size << cfg->sector_size_1k;
 959         int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 960
 961         if (section >= sectors)
 962                 return -ERANGE;
 963
 964         if (sas <= chip->ecc.bytes)
 965                 return 0;
 966
 967         oobregion->offset = section * sas;
 968         oobregion->length = sas - chip->ecc.bytes;
 969
 970         if (!section) {
 971                 oobregion->offset++;
 972                 oobregion->length--;
 973         }
 974
 975         return 0;
 976 }
 977
 978 static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section,
 979                                           struct mtd_oob_region *oobregion)
 980 {
 981         struct nand_chip *chip = mtd_to_nand(mtd);
 982         struct brcmnand_host *host = nand_get_controller_data(chip);
 983         struct brcmnand_cfg *cfg = &host->hwcfg;
 984         int sas = cfg->spare_area_size << cfg->sector_size_1k;
 985
 986         if (section > 1 || sas - chip->ecc.bytes < 6 ||
 987             (section && sas - chip->ecc.bytes == 6))
 988                 return -ERANGE;
 989
 990         if (!section) {
 991                 oobregion->offset = 0;
 992                 oobregion->length = 5;
 993         } else {
 994                 oobregion->offset = 6;
 995                 oobregion->length = sas - chip->ecc.bytes - 6;
 996         }
 997
 998         return 0;
 999 }
1000
1001 static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = {
1002         .ecc = brcmnand_bch_ooblayout_ecc,
1003         .free = brcmnand_bch_ooblayout_free_lp,
1004 };
1005
1006 static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = {
1007         .ecc = brcmnand_bch_ooblayout_ecc,
1008         .free = brcmnand_bch_ooblayout_free_sp,
1009 };
1010
1011 static int brcmstb_choose_ecc_layout(struct brcmnand_host *host)
1012 {
1013         struct brcmnand_cfg *p = &host->hwcfg;
1014         struct mtd_info *mtd = nand_to_mtd(&host->chip);
1015         struct nand_ecc_ctrl *ecc = &host->chip.ecc;
1016         unsigned int ecc_level = p->ecc_level;
1017         int sas = p->spare_area_size << p->sector_size_1k;
1018         int sectors = p->page_size / (512 << p->sector_size_1k);
1019
1020         if (p->sector_size_1k)
1021                 ecc_level <<= 1;
1022
1023         if (is_hamming_ecc(host->ctrl, p)) {
1024                 ecc->bytes = 3 * sectors;
1025                 mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops);
1026                 return 0;
1027         }
1028
1029         /*
1030          * CONTROLLER_VERSION:
1031          *   < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
1032          *  >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
1033          * But we will just be conservative.
1034          */
1035         ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8);
1036         if (p->page_size == 512)
1037                 mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops);
1038         else
1039                 mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops);
1040
1041         if (ecc->bytes >= sas) {
1042                 dev_err(&host->pdev->dev,
1043                         "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
1044                         ecc->bytes, sas);
1045                 return -EINVAL;
1046         }
1047
1048         return 0;
1049 }
1050
1051 static void brcmnand_wp(struct mtd_info *mtd, int wp)
1052 {
1053         struct nand_chip *chip = mtd_to_nand(mtd);
1054         struct brcmnand_host *host = nand_get_controller_data(chip);
1055         struct brcmnand_controller *ctrl = host->ctrl;
1056
1057         if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
1058                 static int old_wp = -1;
1059                 int ret;
1060
1061                 if (old_wp != wp) {
1062                         dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
1063                         old_wp = wp;
1064                 }
1065
1066                 /*
1067                  * make sure ctrl/flash ready before and after
1068                  * changing state of #WP pin
1069                  */
1070                 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY |
1071                                                NAND_STATUS_READY,
1072                                                NAND_CTRL_RDY |
1073                                                NAND_STATUS_READY, 0);
1074                 if (ret)
1075                         return;
1076
1077                 brcmnand_set_wp(ctrl, wp);
1078                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1079                 /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */
1080                 ret = bcmnand_ctrl_poll_status(ctrl,
1081                                                NAND_CTRL_RDY |
1082                                                NAND_STATUS_READY |
1083                                                NAND_STATUS_WP,
1084                                                NAND_CTRL_RDY |
1085                                                NAND_STATUS_READY |
1086                                                (wp ? 0 : NAND_STATUS_WP), 0);
1087
1088                 if (ret)
1089                         dev_err_ratelimited(&host->pdev->dev,
1090                                             "nand #WP expected %s\n",
1091                                             wp ? "on" : "off");
1092         }
1093 }
1094
1095 /* Helper functions for reading and writing OOB registers */
1096 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
1097 {
1098         u16 offset0, offset10, reg_offs;
1099
1100         offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
1101         offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
1102
1103         if (offs >= ctrl->max_oob)
1104                 return 0x77;
1105
1106         if (offs >= 16 && offset10)
1107                 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1108         else
1109                 reg_offs = offset0 + (offs & ~0x03);
1110
1111         return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
1112 }
1113
1114 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
1115                                  u32 data)
1116 {
1117         u16 offset0, offset10, reg_offs;
1118
1119         offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
1120         offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
1121
1122         if (offs >= ctrl->max_oob)
1123                 return;
1124
1125         if (offs >= 16 && offset10)
1126                 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1127         else
1128                 reg_offs = offset0 + (offs & ~0x03);
1129
1130         nand_writereg(ctrl, reg_offs, data);
1131 }
1132
1133 /*
1134  * read_oob_from_regs - read data from OOB registers
1135  * @ctrl: NAND controller
1136  * @i: sub-page sector index
1137  * @oob: buffer to read to
1138  * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1139  * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1140  */
1141 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
1142                               int sas, int sector_1k)
1143 {
1144         int tbytes = sas << sector_1k;
1145         int j;
1146
1147         /* Adjust OOB values for 1K sector size */
1148         if (sector_1k && (i & 0x01))
1149                 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1150         tbytes = min_t(int, tbytes, ctrl->max_oob);
1151
1152         for (j = 0; j < tbytes; j++)
1153                 oob[j] = oob_reg_read(ctrl, j);
1154         return tbytes;
1155 }
1156
1157 /*
1158  * write_oob_to_regs - write data to OOB registers
1159  * @i: sub-page sector index
1160  * @oob: buffer to write from
1161  * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1162  * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1163  */
1164 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
1165                              const u8 *oob, int sas, int sector_1k)
1166 {
1167         int tbytes = sas << sector_1k;
1168         int j;
1169
1170         /* Adjust OOB values for 1K sector size */
1171         if (sector_1k && (i & 0x01))
1172                 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1173         tbytes = min_t(int, tbytes, ctrl->max_oob);
1174
1175         for (j = 0; j < tbytes; j += 4)
1176                 oob_reg_write(ctrl, j,
1177                                 (oob[j + 0] << 24) |
1178                                 (oob[j + 1] << 16) |
1179                                 (oob[j + 2] <<  8) |
1180                                 (oob[j + 3] <<  0));
1181         return tbytes;
1182 }
1183
1184 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1185 {
1186         struct brcmnand_controller *ctrl = data;
1187
1188         /* Discard all NAND_CTLRDY interrupts during DMA */
1189         if (ctrl->dma_pending)
1190                 return IRQ_HANDLED;
1191
1192         complete(&ctrl->done);
1193         return IRQ_HANDLED;
1194 }
1195
1196 /* Handle SoC-specific interrupt hardware */
1197 static irqreturn_t brcmnand_irq(int irq, void *data)
1198 {
1199         struct brcmnand_controller *ctrl = data;
1200
1201         if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1202                 return brcmnand_ctlrdy_irq(irq, data);
1203
1204         return IRQ_NONE;
1205 }
1206
1207 static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1208 {
1209         struct brcmnand_controller *ctrl = data;
1210
1211         complete(&ctrl->dma_done);
1212
1213         return IRQ_HANDLED;
1214 }
1215
1216 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1217 {
1218         struct brcmnand_controller *ctrl = host->ctrl;
1219         int ret;
1220
1221         dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
1222                 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
1223         BUG_ON(ctrl->cmd_pending != 0);
1224         ctrl->cmd_pending = cmd;
1225
1226         ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
1227         WARN_ON(ret);
1228
1229         mb(); /* flush previous writes */
1230         brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1231                            cmd << brcmnand_cmd_shift(ctrl));
1232 }
1233
1234 /***********************************************************************
1235  * NAND MTD API: read/program/erase
1236  ***********************************************************************/
1237
1238 static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1239         unsigned int ctrl)
1240 {
1241         /* intentionally left blank */
1242 }
1243
1244 static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1245 {
1246         struct nand_chip *chip = mtd_to_nand(mtd);
1247         struct brcmnand_host *host = nand_get_controller_data(chip);
1248         struct brcmnand_controller *ctrl = host->ctrl;
1249         unsigned long timeo = msecs_to_jiffies(100);
1250
1251         dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1252         if (ctrl->cmd_pending &&
1253                         wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1254                 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1255                                         >> brcmnand_cmd_shift(ctrl);
1256
1257                 dev_err_ratelimited(ctrl->dev,
1258                         "timeout waiting for command %#02x\n", cmd);
1259                 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1260                         brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1261         }
1262         ctrl->cmd_pending = 0;
1263         return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1264                                  INTFC_FLASH_STATUS;
1265 }
1266
1267 enum {
1268         LLOP_RE                         = BIT(16),
1269         LLOP_WE                         = BIT(17),
1270         LLOP_ALE                        = BIT(18),
1271         LLOP_CLE                        = BIT(19),
1272         LLOP_RETURN_IDLE                = BIT(31),
1273
1274         LLOP_DATA_MASK                  = GENMASK(15, 0),
1275 };
1276
1277 static int brcmnand_low_level_op(struct brcmnand_host *host,
1278                                  enum brcmnand_llop_type type, u32 data,
1279                                  bool last_op)
1280 {
1281         struct mtd_info *mtd = nand_to_mtd(&host->chip);
1282         struct nand_chip *chip = &host->chip;
1283         struct brcmnand_controller *ctrl = host->ctrl;
1284         u32 tmp;
1285
1286         tmp = data & LLOP_DATA_MASK;
1287         switch (type) {
1288         case LL_OP_CMD:
1289                 tmp |= LLOP_WE | LLOP_CLE;
1290                 break;
1291         case LL_OP_ADDR:
1292                 /* WE | ALE */
1293                 tmp |= LLOP_WE | LLOP_ALE;
1294                 break;
1295         case LL_OP_WR:
1296                 /* WE */
1297                 tmp |= LLOP_WE;
1298                 break;
1299         case LL_OP_RD:
1300                 /* RE */
1301                 tmp |= LLOP_RE;
1302                 break;
1303         }
1304         if (last_op)
1305                 /* RETURN_IDLE */
1306                 tmp |= LLOP_RETURN_IDLE;
1307
1308         dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1309
1310         brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1311         (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1312
1313         brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1314         return brcmnand_waitfunc(mtd, chip);
1315 }
1316
1317 static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1318                              int column, int page_addr)
1319 {
1320         struct nand_chip *chip = mtd_to_nand(mtd);
1321         struct brcmnand_host *host = nand_get_controller_data(chip);
1322         struct brcmnand_controller *ctrl = host->ctrl;
1323         u64 addr = (u64)page_addr << chip->page_shift;
1324         int native_cmd = 0;
1325
1326         if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1327                         command == NAND_CMD_RNDOUT)
1328                 addr = (u64)column;
1329         /* Avoid propagating a negative, don't-care address */
1330         else if (page_addr < 0)
1331                 addr = 0;
1332
1333         dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1334                 (unsigned long long)addr);
1335
1336         host->last_cmd = command;
1337         host->last_byte = 0;
1338         host->last_addr = addr;
1339
1340         switch (command) {
1341         case NAND_CMD_RESET:
1342                 native_cmd = CMD_FLASH_RESET;
1343                 break;
1344         case NAND_CMD_STATUS:
1345                 native_cmd = CMD_STATUS_READ;
1346                 break;
1347         case NAND_CMD_READID:
1348                 native_cmd = CMD_DEVICE_ID_READ;
1349                 break;
1350         case NAND_CMD_READOOB:
1351                 native_cmd = CMD_SPARE_AREA_READ;
1352                 break;
1353         case NAND_CMD_ERASE1:
1354                 native_cmd = CMD_BLOCK_ERASE;
1355                 brcmnand_wp(mtd, 0);
1356                 break;
1357         case NAND_CMD_PARAM:
1358                 native_cmd = CMD_PARAMETER_READ;
1359                 break;
1360         case NAND_CMD_SET_FEATURES:
1361         case NAND_CMD_GET_FEATURES:
1362                 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1363                 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1364                 break;
1365         case NAND_CMD_RNDOUT:
1366                 native_cmd = CMD_PARAMETER_CHANGE_COL;
1367                 addr &= ~((u64)(FC_BYTES - 1));
1368                 /*
1369                  * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1370                  * NB: hwcfg.sector_size_1k may not be initialized yet
1371                  */
1372                 if (brcmnand_get_sector_size_1k(host)) {
1373                         host->hwcfg.sector_size_1k =
1374                                 brcmnand_get_sector_size_1k(host);
1375                         brcmnand_set_sector_size_1k(host, 0);
1376                 }
1377                 break;
1378         }
1379
1380         if (!native_cmd)
1381                 return;
1382
1383         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1384                 (host->cs << 16) | ((addr >> 32) & 0xffff));
1385         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1386         brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1387         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1388
1389         brcmnand_send_cmd(host, native_cmd);
1390         brcmnand_waitfunc(mtd, chip);
1391
1392         if (native_cmd == CMD_PARAMETER_READ ||
1393                         native_cmd == CMD_PARAMETER_CHANGE_COL) {
1394                 /* Copy flash cache word-wise */
1395                 u32 *flash_cache = (u32 *)ctrl->flash_cache;
1396                 int i;
1397
1398                 brcmnand_soc_data_bus_prepare(ctrl->soc, true);
1399
1400                 /*
1401                  * Must cache the FLASH_CACHE now, since changes in
1402                  * SECTOR_SIZE_1K may invalidate it
1403                  */
1404                 for (i = 0; i < FC_WORDS; i++)
1405                         /*
1406                          * Flash cache is big endian for parameter pages, at
1407                          * least on STB SoCs
1408                          */
1409                         flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i));
1410
1411                 brcmnand_soc_data_bus_unprepare(ctrl->soc, true);
1412
1413                 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1414                 if (host->hwcfg.sector_size_1k)
1415                         brcmnand_set_sector_size_1k(host,
1416                                                     host->hwcfg.sector_size_1k);
1417         }
1418
1419         /* Re-enable protection is necessary only after erase */
1420         if (command == NAND_CMD_ERASE1)
1421                 brcmnand_wp(mtd, 1);
1422 }
1423
1424 static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1425 {
1426         struct nand_chip *chip = mtd_to_nand(mtd);
1427         struct brcmnand_host *host = nand_get_controller_data(chip);
1428         struct brcmnand_controller *ctrl = host->ctrl;
1429         uint8_t ret = 0;
1430         int addr, offs;
1431
1432         switch (host->last_cmd) {
1433         case NAND_CMD_READID:
1434                 if (host->last_byte < 4)
1435                         ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1436                                 (24 - (host->last_byte << 3));
1437                 else if (host->last_byte < 8)
1438                         ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1439                                 (56 - (host->last_byte << 3));
1440                 break;
1441
1442         case NAND_CMD_READOOB:
1443                 ret = oob_reg_read(ctrl, host->last_byte);
1444                 break;
1445
1446         case NAND_CMD_STATUS:
1447                 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1448                                         INTFC_FLASH_STATUS;
1449                 if (wp_on) /* hide WP status */
1450                         ret |= NAND_STATUS_WP;
1451                 break;
1452
1453         case NAND_CMD_PARAM:
1454         case NAND_CMD_RNDOUT:
1455                 addr = host->last_addr + host->last_byte;
1456                 offs = addr & (FC_BYTES - 1);
1457
1458                 /* At FC_BYTES boundary, switch to next column */
1459                 if (host->last_byte > 0 && offs == 0)
1460                         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
1461
1462                 ret = ctrl->flash_cache[offs];
1463                 break;
1464         case NAND_CMD_GET_FEATURES:
1465                 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1466                         ret = 0;
1467                 } else {
1468                         bool last = host->last_byte ==
1469                                 ONFI_SUBFEATURE_PARAM_LEN - 1;
1470                         brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1471                         ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1472                 }
1473         }
1474
1475         dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1476         host->last_byte++;
1477
1478         return ret;
1479 }
1480
1481 static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1482 {
1483         int i;
1484
1485         for (i = 0; i < len; i++, buf++)
1486                 *buf = brcmnand_read_byte(mtd);
1487 }
1488
1489 static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1490                                    int len)
1491 {
1492         int i;
1493         struct nand_chip *chip = mtd_to_nand(mtd);
1494         struct brcmnand_host *host = nand_get_controller_data(chip);
1495
1496         switch (host->last_cmd) {
1497         case NAND_CMD_SET_FEATURES:
1498                 for (i = 0; i < len; i++)
1499                         brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1500                                                   (i + 1) == len);
1501                 break;
1502         default:
1503                 BUG();
1504                 break;
1505         }
1506 }
1507
1508 /**
1509  * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1510  * following ahead of time:
1511  *  - Is this descriptor the beginning or end of a linked list?
1512  *  - What is the (DMA) address of the next descriptor in the linked list?
1513  */
1514 static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1515                                   struct brcm_nand_dma_desc *desc, u64 addr,
1516                                   dma_addr_t buf, u32 len, u8 dma_cmd,
1517                                   bool begin, bool end,
1518                                   dma_addr_t next_desc)
1519 {
1520         memset(desc, 0, sizeof(*desc));
1521         /* Descriptors are written in native byte order (wordwise) */
1522         desc->next_desc = lower_32_bits(next_desc);
1523         desc->next_desc_ext = upper_32_bits(next_desc);
1524         desc->cmd_irq = (dma_cmd << 24) |
1525                 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1526                 (!!begin) | ((!!end) << 1); /* head, tail */
1527 #ifdef CONFIG_CPU_BIG_ENDIAN
1528         desc->cmd_irq |= 0x01 << 12;
1529 #endif
1530         desc->dram_addr = lower_32_bits(buf);
1531         desc->dram_addr_ext = upper_32_bits(buf);
1532         desc->tfr_len = len;
1533         desc->total_len = len;
1534         desc->flash_addr = lower_32_bits(addr);
1535         desc->flash_addr_ext = upper_32_bits(addr);
1536         desc->cs = host->cs;
1537         desc->status_valid = 0x01;
1538         return 0;
1539 }
1540
1541 /**
1542  * Kick the FLASH_DMA engine, with a given DMA descriptor
1543  */
1544 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1545 {
1546         struct brcmnand_controller *ctrl = host->ctrl;
1547         unsigned long timeo = msecs_to_jiffies(100);
1548
1549         flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1550         (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1551         flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1552         (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1553
1554         /* Start FLASH_DMA engine */
1555         ctrl->dma_pending = true;
1556         mb(); /* flush previous writes */
1557         flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1558
1559         if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1560                 dev_err(ctrl->dev,
1561                                 "timeout waiting for DMA; status %#x, error status %#x\n",
1562                                 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1563                                 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1564         }
1565         ctrl->dma_pending = false;
1566         flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1567 }
1568
1569 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1570                               u32 len, u8 dma_cmd)
1571 {
1572         struct brcmnand_controller *ctrl = host->ctrl;
1573         dma_addr_t buf_pa;
1574         int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1575
1576         buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1577         if (dma_mapping_error(ctrl->dev, buf_pa)) {
1578                 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1579                 return -ENOMEM;
1580         }
1581
1582         brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1583                                    dma_cmd, true, true, 0);
1584
1585         brcmnand_dma_run(host, ctrl->dma_pa);
1586
1587         dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1588
1589         if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1590                 return -EBADMSG;
1591         else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1592                 return -EUCLEAN;
1593
1594         return 0;
1595 }
1596
1597 /*
1598  * Assumes proper CS is already set
1599  */
1600 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1601                                 u64 addr, unsigned int trans, u32 *buf,
1602                                 u8 *oob, u64 *err_addr)
1603 {
1604         struct brcmnand_host *host = nand_get_controller_data(chip);
1605         struct brcmnand_controller *ctrl = host->ctrl;
1606         int i, j, ret = 0;
1607
1608         /* Clear error addresses */
1609         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1610         brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
1611         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
1612         brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
1613
1614         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1615                         (host->cs << 16) | ((addr >> 32) & 0xffff));
1616         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1617
1618         for (i = 0; i < trans; i++, addr += FC_BYTES) {
1619                 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1620                                    lower_32_bits(addr));
1621                 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1622                 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1623                 brcmnand_send_cmd(host, CMD_PAGE_READ);
1624                 brcmnand_waitfunc(mtd, chip);
1625
1626                 if (likely(buf)) {
1627                         brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1628
1629                         for (j = 0; j < FC_WORDS; j++, buf++)
1630                                 *buf = brcmnand_read_fc(ctrl, j);
1631
1632                         brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1633                 }
1634
1635                 if (oob)
1636                         oob += read_oob_from_regs(ctrl, i, oob,
1637                                         mtd->oobsize / trans,
1638                                         host->hwcfg.sector_size_1k);
1639
1640                 if (ret != -EBADMSG) {
1641                         *err_addr = brcmnand_read_reg(ctrl,
1642                                         BRCMNAND_UNCORR_ADDR) |
1643                                 ((u64)(brcmnand_read_reg(ctrl,
1644                                                 BRCMNAND_UNCORR_EXT_ADDR)
1645                                         & 0xffff) << 32);
1646                         if (*err_addr)
1647                                 ret = -EBADMSG;
1648                 }
1649
1650                 if (!ret) {
1651                         *err_addr = brcmnand_read_reg(ctrl,
1652                                         BRCMNAND_CORR_ADDR) |
1653                                 ((u64)(brcmnand_read_reg(ctrl,
1654                                                 BRCMNAND_CORR_EXT_ADDR)
1655                                         & 0xffff) << 32);
1656                         if (*err_addr)
1657                                 ret = -EUCLEAN;
1658                 }
1659         }
1660
1661         return ret;
1662 }
1663
1664 /*
1665  * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC
1666  * error
1667  *
1668  * Because the HW ECC signals an ECC error if an erase paged has even a single
1669  * bitflip, we must check each ECC error to see if it is actually an erased
1670  * page with bitflips, not a truly corrupted page.
1671  *
1672  * On a real error, return a negative error code (-EBADMSG for ECC error), and
1673  * buf will contain raw data.
1674  * Otherwise, buf gets filled with 0xffs and return the maximum number of
1675  * bitflips-per-ECC-sector to the caller.
1676  *
1677  */
1678 static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
1679                   struct nand_chip *chip, void *buf, u64 addr)
1680 {
1681         int i, sas;
1682         void *oob = chip->oob_poi;
1683         int bitflips = 0;
1684         int page = addr >> chip->page_shift;
1685         int ret;
1686
1687         if (!buf) {
1688                 buf = chip->buffers->databuf;
1689                 /* Invalidate page cache */
1690                 chip->pagebuf = -1;
1691         }
1692
1693         sas = mtd->oobsize / chip->ecc.steps;
1694
1695         /* read without ecc for verification */
1696         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1697         ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
1698         if (ret)
1699                 return ret;
1700
1701         for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
1702                 ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size,
1703                                                   oob, sas, NULL, 0,
1704                                                   chip->ecc.strength);
1705                 if (ret < 0)
1706                         return ret;
1707
1708                 bitflips = max(bitflips, ret);
1709         }
1710
1711         return bitflips;
1712 }
1713
1714 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1715                          u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1716 {
1717         struct brcmnand_host *host = nand_get_controller_data(chip);
1718         struct brcmnand_controller *ctrl = host->ctrl;
1719         u64 err_addr = 0;
1720         int err;
1721         bool retry = true;
1722
1723         dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1724
1725 try_dmaread:
1726         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1727
1728         if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1729                 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1730                                              CMD_PAGE_READ);
1731                 if (err) {
1732                         if (mtd_is_bitflip_or_eccerr(err))
1733                                 err_addr = addr;
1734                         else
1735                                 return -EIO;
1736                 }
1737         } else {
1738                 if (oob)
1739                         memset(oob, 0x99, mtd->oobsize);
1740
1741                 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1742                                                oob, &err_addr);
1743         }
1744
1745         if (mtd_is_eccerr(err)) {
1746                 /*
1747                  * On controller version and 7.0, 7.1 , DMA read after a
1748                  * prior PIO read that reported uncorrectable error,
1749                  * the DMA engine captures this error following DMA read
1750                  * cleared only on subsequent DMA read, so just retry once
1751                  * to clear a possible false error reported for current DMA
1752                  * read
1753                  */
1754                 if ((ctrl->nand_version == 0x0700) ||
1755                     (ctrl->nand_version == 0x0701)) {
1756                         if (retry) {
1757                                 retry = false;
1758                                 goto try_dmaread;
1759                         }
1760                 }
1761
1762                 /*
1763                  * Controller version 7.2 has hw encoder to detect erased page
1764                  * bitflips, apply sw verification for older controllers only
1765                  */
1766                 if (ctrl->nand_version < 0x0702) {
1767                         err = brcmstb_nand_verify_erased_page(mtd, chip, buf,
1768                                                               addr);
1769                         /* erased page bitflips corrected */
1770                         if (err >= 0)
1771                                 return err;
1772                 }
1773
1774                 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1775                         (unsigned long long)err_addr);
1776                 mtd->ecc_stats.failed++;
1777                 /* NAND layer expects zero on ECC errors */
1778                 return 0;
1779         }
1780
1781         if (mtd_is_bitflip(err)) {
1782                 unsigned int corrected = brcmnand_count_corrected(ctrl);
1783
1784                 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1785                         (unsigned long long)err_addr);
1786                 mtd->ecc_stats.corrected += corrected;
1787                 /* Always exceed the software-imposed threshold */
1788                 return max(mtd->bitflip_threshold, corrected);
1789         }
1790
1791         return 0;
1792 }
1793
1794 static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1795                               uint8_t *buf, int oob_required, int page)
1796 {
1797         struct brcmnand_host *host = nand_get_controller_data(chip);
1798         u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1799
1800         return brcmnand_read(mtd, chip, host->last_addr,
1801                         mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1802 }
1803
1804 static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1805                                   uint8_t *buf, int oob_required, int page)
1806 {
1807         struct brcmnand_host *host = nand_get_controller_data(chip);
1808         u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1809         int ret;
1810
1811         brcmnand_set_ecc_enabled(host, 0);
1812         ret = brcmnand_read(mtd, chip, host->last_addr,
1813                         mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1814         brcmnand_set_ecc_enabled(host, 1);
1815         return ret;
1816 }
1817
1818 static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1819                              int page)
1820 {
1821         return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1822                         mtd->writesize >> FC_SHIFT,
1823                         NULL, (u8 *)chip->oob_poi);
1824 }
1825
1826 static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1827                                  int page)
1828 {
1829         struct brcmnand_host *host = nand_get_controller_data(chip);
1830
1831         brcmnand_set_ecc_enabled(host, 0);
1832         brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1833                 mtd->writesize >> FC_SHIFT,
1834                 NULL, (u8 *)chip->oob_poi);
1835         brcmnand_set_ecc_enabled(host, 1);
1836         return 0;
1837 }
1838
1839 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1840                           u64 addr, const u32 *buf, u8 *oob)
1841 {
1842         struct brcmnand_host *host = nand_get_controller_data(chip);
1843         struct brcmnand_controller *ctrl = host->ctrl;
1844         unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1845         int status, ret = 0;
1846
1847         dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1848
1849         if (unlikely((unsigned long)buf & 0x03)) {
1850                 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
1851                 buf = (u32 *)((unsigned long)buf & ~0x03);
1852         }
1853
1854         brcmnand_wp(mtd, 0);
1855
1856         for (i = 0; i < ctrl->max_oob; i += 4)
1857                 oob_reg_write(ctrl, i, 0xffffffff);
1858
1859         if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1860                 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1861                                         mtd->writesize, CMD_PROGRAM_PAGE))
1862                         ret = -EIO;
1863                 goto out;
1864         }
1865
1866         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1867                         (host->cs << 16) | ((addr >> 32) & 0xffff));
1868         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1869
1870         for (i = 0; i < trans; i++, addr += FC_BYTES) {
1871                 /* full address MUST be set before populating FC */
1872                 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1873                                    lower_32_bits(addr));
1874                 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1875
1876                 if (buf) {
1877                         brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1878
1879                         for (j = 0; j < FC_WORDS; j++, buf++)
1880                                 brcmnand_write_fc(ctrl, j, *buf);
1881
1882                         brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1883                 } else if (oob) {
1884                         for (j = 0; j < FC_WORDS; j++)
1885                                 brcmnand_write_fc(ctrl, j, 0xffffffff);
1886                 }
1887
1888                 if (oob) {
1889                         oob += write_oob_to_regs(ctrl, i, oob,
1890                                         mtd->oobsize / trans,
1891                                         host->hwcfg.sector_size_1k);
1892                 }
1893
1894                 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1895                 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1896                 status = brcmnand_waitfunc(mtd, chip);
1897
1898                 if (status & NAND_STATUS_FAIL) {
1899                         dev_info(ctrl->dev, "program failed at %llx\n",
1900                                 (unsigned long long)addr);
1901                         ret = -EIO;
1902                         goto out;
1903                 }
1904         }
1905 out:
1906         brcmnand_wp(mtd, 1);
1907         return ret;
1908 }
1909
1910 static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1911                                const uint8_t *buf, int oob_required, int page)
1912 {
1913         struct brcmnand_host *host = nand_get_controller_data(chip);
1914         void *oob = oob_required ? chip->oob_poi : NULL;
1915
1916         brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1917         return 0;
1918 }
1919
1920 static int brcmnand_write_page_raw(struct mtd_info *mtd,
1921                                    struct nand_chip *chip, const uint8_t *buf,
1922                                    int oob_required, int page)
1923 {
1924         struct brcmnand_host *host = nand_get_controller_data(chip);
1925         void *oob = oob_required ? chip->oob_poi : NULL;
1926
1927         brcmnand_set_ecc_enabled(host, 0);
1928         brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1929         brcmnand_set_ecc_enabled(host, 1);
1930         return 0;
1931 }
1932
1933 static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1934                                   int page)
1935 {
1936         return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1937                                   NULL, chip->oob_poi);
1938 }
1939
1940 static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1941                                   int page)
1942 {
1943         struct brcmnand_host *host = nand_get_controller_data(chip);
1944         int ret;
1945
1946         brcmnand_set_ecc_enabled(host, 0);
1947         ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1948                                  (u8 *)chip->oob_poi);
1949         brcmnand_set_ecc_enabled(host, 1);
1950
1951         return ret;
1952 }
1953
1954 /***********************************************************************
1955  * Per-CS setup (1 NAND device)
1956  ***********************************************************************/
1957
1958 static int brcmnand_set_cfg(struct brcmnand_host *host,
1959                             struct brcmnand_cfg *cfg)
1960 {
1961         struct brcmnand_controller *ctrl = host->ctrl;
1962         struct nand_chip *chip = &host->chip;
1963         u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1964         u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1965                         BRCMNAND_CS_CFG_EXT);
1966         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1967                         BRCMNAND_CS_ACC_CONTROL);
1968         u8 block_size = 0, page_size = 0, device_size = 0;
1969         u32 tmp;
1970
1971         if (ctrl->block_sizes) {
1972                 int i, found;
1973
1974                 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
1975                         if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
1976                                 block_size = i;
1977                                 found = 1;
1978                         }
1979                 if (!found) {
1980                         dev_warn(ctrl->dev, "invalid block size %u\n",
1981                                         cfg->block_size);
1982                         return -EINVAL;
1983                 }
1984         } else {
1985                 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
1986         }
1987
1988         if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
1989                                 cfg->block_size > ctrl->max_block_size)) {
1990                 dev_warn(ctrl->dev, "invalid block size %u\n",
1991                                 cfg->block_size);
1992                 block_size = 0;
1993         }
1994
1995         if (ctrl->page_sizes) {
1996                 int i, found;
1997
1998                 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
1999                         if (ctrl->page_sizes[i] == cfg->page_size) {
2000                                 page_size = i;
2001                                 found = 1;
2002                         }
2003                 if (!found) {
2004                         dev_warn(ctrl->dev, "invalid page size %u\n",
2005                                         cfg->page_size);
2006                         return -EINVAL;
2007                 }
2008         } else {
2009                 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
2010         }
2011
2012         if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
2013                                 cfg->page_size > ctrl->max_page_size)) {
2014                 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
2015                 return -EINVAL;
2016         }
2017
2018         if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
2019                 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
2020                         (unsigned long long)cfg->device_size);
2021                 return -EINVAL;
2022         }
2023         device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
2024
2025         tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
2026                 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
2027                 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
2028                 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
2029                 (device_size << CFG_DEVICE_SIZE_SHIFT);
2030         if (cfg_offs == cfg_ext_offs) {
2031                 tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
2032                        (block_size << CFG_BLK_SIZE_SHIFT);
2033                 nand_writereg(ctrl, cfg_offs, tmp);
2034         } else {
2035                 nand_writereg(ctrl, cfg_offs, tmp);
2036                 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
2037                       (block_size << CFG_EXT_BLK_SIZE_SHIFT);
2038                 nand_writereg(ctrl, cfg_ext_offs, tmp);
2039         }
2040
2041         tmp = nand_readreg(ctrl, acc_control_offs);
2042         tmp &= ~brcmnand_ecc_level_mask(ctrl);
2043         tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
2044         tmp &= ~brcmnand_spare_area_mask(ctrl);
2045         tmp |= cfg->spare_area_size;
2046         nand_writereg(ctrl, acc_control_offs, tmp);
2047
2048         brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
2049
2050         /* threshold = ceil(BCH-level * 0.75) */
2051         brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
2052
2053         return 0;
2054 }
2055
2056 static void brcmnand_print_cfg(struct brcmnand_host *host,
2057                                char *buf, struct brcmnand_cfg *cfg)
2058 {
2059         buf += sprintf(buf,
2060                 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
2061                 (unsigned long long)cfg->device_size >> 20,
2062                 cfg->block_size >> 10,
2063                 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
2064                 cfg->page_size >= 1024 ? "KiB" : "B",
2065                 cfg->spare_area_size, cfg->device_width);
2066
2067         /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
2068         if (is_hamming_ecc(host->ctrl, cfg))
2069                 sprintf(buf, ", Hamming ECC");
2070         else if (cfg->sector_size_1k)
2071                 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
2072         else
2073                 sprintf(buf, ", BCH-%u", cfg->ecc_level);
2074 }
2075
2076 /*
2077  * Minimum number of bytes to address a page. Calculated as:
2078  *     roundup(log2(size / page-size) / 8)
2079  *
2080  * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2081  *     OK because many other things will break if 'size' is irregular...
2082  */
2083 static inline int get_blk_adr_bytes(u64 size, u32 writesize)
2084 {
2085         return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
2086 }
2087
2088 static int brcmnand_setup_dev(struct brcmnand_host *host)
2089 {
2090         struct mtd_info *mtd = nand_to_mtd(&host->chip);
2091         struct nand_chip *chip = &host->chip;
2092         struct brcmnand_controller *ctrl = host->ctrl;
2093         struct brcmnand_cfg *cfg = &host->hwcfg;
2094         char msg[128];
2095         u32 offs, tmp, oob_sector;
2096         int ret;
2097
2098         memset(cfg, 0, sizeof(*cfg));
2099
2100         ret = of_property_read_u32(nand_get_flash_node(chip),
2101                                    "brcm,nand-oob-sector-size",
2102                                    &oob_sector);
2103         if (ret) {
2104                 /* Use detected size */
2105                 cfg->spare_area_size = mtd->oobsize /
2106                                         (mtd->writesize >> FC_SHIFT);
2107         } else {
2108                 cfg->spare_area_size = oob_sector;
2109         }
2110         if (cfg->spare_area_size > ctrl->max_oob)
2111                 cfg->spare_area_size = ctrl->max_oob;
2112         /*
2113          * Set oobsize to be consistent with controller's spare_area_size, as
2114          * the rest is inaccessible.
2115          */
2116         mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
2117
2118         cfg->device_size = mtd->size;
2119         cfg->block_size = mtd->erasesize;
2120         cfg->page_size = mtd->writesize;
2121         cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
2122         cfg->col_adr_bytes = 2;
2123         cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
2124
2125         if (chip->ecc.mode != NAND_ECC_HW) {
2126                 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n",
2127                         chip->ecc.mode);
2128                 return -EINVAL;
2129         }
2130
2131         if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
2132                 if (chip->ecc.strength == 1 && chip->ecc.size == 512)
2133                         /* Default to Hamming for 1-bit ECC, if unspecified */
2134                         chip->ecc.algo = NAND_ECC_HAMMING;
2135                 else
2136                         /* Otherwise, BCH */
2137                         chip->ecc.algo = NAND_ECC_BCH;
2138         }
2139
2140         if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 ||
2141                                                    chip->ecc.size != 512)) {
2142                 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n",
2143                         chip->ecc.strength, chip->ecc.size);
2144                 return -EINVAL;
2145         }
2146
2147         switch (chip->ecc.size) {
2148         case 512:
2149                 if (chip->ecc.algo == NAND_ECC_HAMMING)
2150                         cfg->ecc_level = 15;
2151                 else
2152                         cfg->ecc_level = chip->ecc.strength;
2153                 cfg->sector_size_1k = 0;
2154                 break;
2155         case 1024:
2156                 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
2157                         dev_err(ctrl->dev, "1KB sectors not supported\n");
2158                         return -EINVAL;
2159                 }
2160                 if (chip->ecc.strength & 0x1) {
2161                         dev_err(ctrl->dev,
2162                                 "odd ECC not supported with 1KB sectors\n");
2163                         return -EINVAL;
2164                 }
2165
2166                 cfg->ecc_level = chip->ecc.strength >> 1;
2167                 cfg->sector_size_1k = 1;
2168                 break;
2169         default:
2170                 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
2171                         chip->ecc.size);
2172                 return -EINVAL;
2173         }
2174
2175         cfg->ful_adr_bytes = cfg->blk_adr_bytes;
2176         if (mtd->writesize > 512)
2177                 cfg->ful_adr_bytes += cfg->col_adr_bytes;
2178         else
2179                 cfg->ful_adr_bytes += 1;
2180
2181         ret = brcmnand_set_cfg(host, cfg);
2182         if (ret)
2183                 return ret;
2184
2185         brcmnand_set_ecc_enabled(host, 1);
2186
2187         brcmnand_print_cfg(host, msg, cfg);
2188         dev_info(ctrl->dev, "detected %s\n", msg);
2189
2190         /* Configure ACC_CONTROL */
2191         offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
2192         tmp = nand_readreg(ctrl, offs);
2193         tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
2194         tmp &= ~ACC_CONTROL_RD_ERASED;
2195
2196         /* We need to turn on Read from erased paged protected by ECC */
2197         if (ctrl->nand_version >= 0x0702)
2198                 tmp |= ACC_CONTROL_RD_ERASED;
2199         tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
2200         if (ctrl->features & BRCMNAND_HAS_PREFETCH)
2201                 tmp &= ~ACC_CONTROL_PREFETCH;
2202
2203         nand_writereg(ctrl, offs, tmp);
2204
2205         return 0;
2206 }
2207
2208 static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
2209 {
2210         struct brcmnand_controller *ctrl = host->ctrl;
2211         struct platform_device *pdev = host->pdev;
2212         struct mtd_info *mtd;
2213         struct nand_chip *chip;
2214         int ret;
2215         u16 cfg_offs;
2216
2217         ret = of_property_read_u32(dn, "reg", &host->cs);
2218         if (ret) {
2219                 dev_err(&pdev->dev, "can't get chip-select\n");
2220                 return -ENXIO;
2221         }
2222
2223         mtd = nand_to_mtd(&host->chip);
2224         chip = &host->chip;
2225
2226         nand_set_flash_node(chip, dn);
2227         nand_set_controller_data(chip, host);
2228         mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
2229                                    host->cs);
2230         mtd->owner = THIS_MODULE;
2231         mtd->dev.parent = &pdev->dev;
2232
2233         chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
2234         chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
2235
2236         chip->cmd_ctrl = brcmnand_cmd_ctrl;
2237         chip->cmdfunc = brcmnand_cmdfunc;
2238         chip->waitfunc = brcmnand_waitfunc;
2239         chip->read_byte = brcmnand_read_byte;
2240         chip->read_buf = brcmnand_read_buf;
2241         chip->write_buf = brcmnand_write_buf;
2242
2243         chip->ecc.mode = NAND_ECC_HW;
2244         chip->ecc.read_page = brcmnand_read_page;
2245         chip->ecc.write_page = brcmnand_write_page;
2246         chip->ecc.read_page_raw = brcmnand_read_page_raw;
2247         chip->ecc.write_page_raw = brcmnand_write_page_raw;
2248         chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
2249         chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
2250         chip->ecc.read_oob = brcmnand_read_oob;
2251         chip->ecc.write_oob = brcmnand_write_oob;
2252
2253         chip->controller = &ctrl->controller;
2254
2255         /*
2256          * The bootloader might have configured 16bit mode but
2257          * NAND READID command only works in 8bit mode. We force
2258          * 8bit mode here to ensure that NAND READID commands works.
2259          */
2260         cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2261         nand_writereg(ctrl, cfg_offs,
2262                       nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
2263
2264         if (nand_scan_ident(mtd, 1, NULL))
2265                 return -ENXIO;
2266
2267         chip->options |= NAND_NO_SUBPAGE_WRITE;
2268         /*
2269          * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
2270          * to/from, and have nand_base pass us a bounce buffer instead, as
2271          * needed.
2272          */
2273         chip->options |= NAND_USE_BOUNCE_BUFFER;
2274
2275         if (chip->bbt_options & NAND_BBT_USE_FLASH)
2276                 chip->bbt_options |= NAND_BBT_NO_OOB;
2277
2278         if (brcmnand_setup_dev(host))
2279                 return -ENXIO;
2280
2281         chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2282         /* only use our internal HW threshold */
2283         mtd->bitflip_threshold = 1;
2284
2285         ret = brcmstb_choose_ecc_layout(host);
2286         if (ret)
2287                 return ret;
2288
2289         if (nand_scan_tail(mtd))
2290                 return -ENXIO;
2291
2292         return mtd_device_register(mtd, NULL, 0);
2293 }
2294
2295 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
2296                                             int restore)
2297 {
2298         struct brcmnand_controller *ctrl = host->ctrl;
2299         u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2300         u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2301                         BRCMNAND_CS_CFG_EXT);
2302         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2303                         BRCMNAND_CS_ACC_CONTROL);
2304         u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2305         u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2306
2307         if (restore) {
2308                 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2309                 if (cfg_offs != cfg_ext_offs)
2310                         nand_writereg(ctrl, cfg_ext_offs,
2311                                       host->hwcfg.config_ext);
2312                 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2313                 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2314                 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2315         } else {
2316                 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2317                 if (cfg_offs != cfg_ext_offs)
2318                         host->hwcfg.config_ext =
2319                                 nand_readreg(ctrl, cfg_ext_offs);
2320                 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2321                 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2322                 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2323         }
2324 }
2325
2326 static int brcmnand_suspend(struct device *dev)
2327 {
2328         struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2329         struct brcmnand_host *host;
2330
2331         list_for_each_entry(host, &ctrl->host_list, node)
2332                 brcmnand_save_restore_cs_config(host, 0);
2333
2334         ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2335         ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2336         ctrl->corr_stat_threshold =
2337                 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2338
2339         if (has_flash_dma(ctrl))
2340                 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2341
2342         return 0;
2343 }
2344
2345 static int brcmnand_resume(struct device *dev)
2346 {
2347         struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2348         struct brcmnand_host *host;
2349
2350         if (has_flash_dma(ctrl)) {
2351                 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2352                 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2353         }
2354
2355         brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2356         brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2357         brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2358                         ctrl->corr_stat_threshold);
2359         if (ctrl->soc) {
2360                 /* Clear/re-enable interrupt */
2361                 ctrl->soc->ctlrdy_ack(ctrl->soc);
2362                 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2363         }
2364
2365         list_for_each_entry(host, &ctrl->host_list, node) {
2366                 struct nand_chip *chip = &host->chip;
2367                 struct mtd_info *mtd = nand_to_mtd(chip);
2368
2369                 brcmnand_save_restore_cs_config(host, 1);
2370
2371                 /* Reset the chip, required by some chips after power-up */
2372                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2373         }
2374
2375         return 0;
2376 }
2377
2378 const struct dev_pm_ops brcmnand_pm_ops = {
2379         .suspend                = brcmnand_suspend,
2380         .resume                 = brcmnand_resume,
2381 };
2382 EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2383
2384 static const struct of_device_id brcmnand_of_match[] = {
2385         { .compatible = "brcm,brcmnand-v4.0" },
2386         { .compatible = "brcm,brcmnand-v5.0" },
2387         { .compatible = "brcm,brcmnand-v6.0" },
2388         { .compatible = "brcm,brcmnand-v6.1" },
2389         { .compatible = "brcm,brcmnand-v6.2" },
2390         { .compatible = "brcm,brcmnand-v7.0" },
2391         { .compatible = "brcm,brcmnand-v7.1" },
2392         { .compatible = "brcm,brcmnand-v7.2" },
2393         {},
2394 };
2395 MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2396
2397 /***********************************************************************
2398  * Platform driver setup (per controller)
2399  ***********************************************************************/
2400
2401 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2402 {
2403         struct device *dev = &pdev->dev;
2404         struct device_node *dn = dev->of_node, *child;
2405         struct brcmnand_controller *ctrl;
2406         struct resource *res;
2407         int ret;
2408
2409         /* We only support device-tree instantiation */
2410         if (!dn)
2411                 return -ENODEV;
2412
2413         if (!of_match_node(brcmnand_of_match, dn))
2414                 return -ENODEV;
2415
2416         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2417         if (!ctrl)
2418                 return -ENOMEM;
2419
2420         dev_set_drvdata(dev, ctrl);
2421         ctrl->dev = dev;
2422
2423         init_completion(&ctrl->done);
2424         init_completion(&ctrl->dma_done);
2425         nand_hw_control_init(&ctrl->controller);
2426         INIT_LIST_HEAD(&ctrl->host_list);
2427
2428         /* NAND register range */
2429         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2430         ctrl->nand_base = devm_ioremap_resource(dev, res);
2431         if (IS_ERR(ctrl->nand_base))
2432                 return PTR_ERR(ctrl->nand_base);
2433
2434         /* Enable clock before using NAND registers */
2435         ctrl->clk = devm_clk_get(dev, "nand");
2436         if (!IS_ERR(ctrl->clk)) {
2437                 ret = clk_prepare_enable(ctrl->clk);
2438                 if (ret)
2439                         return ret;
2440         } else {
2441                 ret = PTR_ERR(ctrl->clk);
2442                 if (ret == -EPROBE_DEFER)
2443                         return ret;
2444
2445                 ctrl->clk = NULL;
2446         }
2447
2448         /* Initialize NAND revision */
2449         ret = brcmnand_revision_init(ctrl);
2450         if (ret)
2451                 goto err;
2452
2453         /*
2454          * Most chips have this cache at a fixed offset within 'nand' block.
2455          * Some must specify this region separately.
2456          */
2457         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2458         if (res) {
2459                 ctrl->nand_fc = devm_ioremap_resource(dev, res);
2460                 if (IS_ERR(ctrl->nand_fc)) {
2461                         ret = PTR_ERR(ctrl->nand_fc);
2462                         goto err;
2463                 }
2464         } else {
2465                 ctrl->nand_fc = ctrl->nand_base +
2466                                 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2467         }
2468
2469         /* FLASH_DMA */
2470         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2471         if (res) {
2472                 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2473                 if (IS_ERR(ctrl->flash_dma_base)) {
2474                         ret = PTR_ERR(ctrl->flash_dma_base);
2475                         goto err;
2476                 }
2477
2478                 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2479                 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2480
2481                 /* Allocate descriptor(s) */
2482                 ctrl->dma_desc = dmam_alloc_coherent(dev,
2483                                                      sizeof(*ctrl->dma_desc),
2484                                                      &ctrl->dma_pa, GFP_KERNEL);
2485                 if (!ctrl->dma_desc) {
2486                         ret = -ENOMEM;
2487                         goto err;
2488                 }
2489
2490                 ctrl->dma_irq = platform_get_irq(pdev, 1);
2491                 if ((int)ctrl->dma_irq < 0) {
2492                         dev_err(dev, "missing FLASH_DMA IRQ\n");
2493                         ret = -ENODEV;
2494                         goto err;
2495                 }
2496
2497                 ret = devm_request_irq(dev, ctrl->dma_irq,
2498                                 brcmnand_dma_irq, 0, DRV_NAME,
2499                                 ctrl);
2500                 if (ret < 0) {
2501                         dev_err(dev, "can't allocate IRQ %d: error %d\n",
2502                                         ctrl->dma_irq, ret);
2503                         goto err;
2504                 }
2505
2506                 dev_info(dev, "enabling FLASH_DMA\n");
2507         }
2508
2509         /* Disable automatic device ID config, direct addressing */
2510         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2511                          CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2512         /* Disable XOR addressing */
2513         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2514
2515         if (ctrl->features & BRCMNAND_HAS_WP) {
2516                 /* Permanently disable write protection */
2517                 if (wp_on == 2)
2518                         brcmnand_set_wp(ctrl, false);
2519         } else {
2520                 wp_on = 0;
2521         }
2522
2523         /* IRQ */
2524         ctrl->irq = platform_get_irq(pdev, 0);
2525         if ((int)ctrl->irq < 0) {
2526                 dev_err(dev, "no IRQ defined\n");
2527                 ret = -ENODEV;
2528                 goto err;
2529         }
2530
2531         /*
2532          * Some SoCs integrate this controller (e.g., its interrupt bits) in
2533          * interesting ways
2534          */
2535         if (soc) {
2536                 ctrl->soc = soc;
2537
2538                 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2539                                        DRV_NAME, ctrl);
2540
2541                 /* Enable interrupt */
2542                 ctrl->soc->ctlrdy_ack(ctrl->soc);
2543                 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2544         } else {
2545                 /* Use standard interrupt infrastructure */
2546                 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2547                                        DRV_NAME, ctrl);
2548         }
2549         if (ret < 0) {
2550                 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2551                         ctrl->irq, ret);
2552                 goto err;
2553         }
2554
2555         for_each_available_child_of_node(dn, child) {
2556                 if (of_device_is_compatible(child, "brcm,nandcs")) {
2557                         struct brcmnand_host *host;
2558
2559                         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2560                         if (!host) {
2561                                 of_node_put(child);
2562                                 ret = -ENOMEM;
2563                                 goto err;
2564                         }
2565                         host->pdev = pdev;
2566                         host->ctrl = ctrl;
2567
2568                         ret = brcmnand_init_cs(host, child);
2569                         if (ret) {
2570                                 devm_kfree(dev, host);
2571                                 continue; /* Try all chip-selects */
2572                         }
2573
2574                         list_add_tail(&host->node, &ctrl->host_list);
2575                 }
2576         }
2577
2578         /* No chip-selects could initialize properly */
2579         if (list_empty(&ctrl->host_list)) {
2580                 ret = -ENODEV;
2581                 goto err;
2582         }
2583
2584         return 0;
2585
2586 err:
2587         clk_disable_unprepare(ctrl->clk);
2588         return ret;
2589
2590 }
2591 EXPORT_SYMBOL_GPL(brcmnand_probe);
2592
2593 int brcmnand_remove(struct platform_device *pdev)
2594 {
2595         struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2596         struct brcmnand_host *host;
2597
2598         list_for_each_entry(host, &ctrl->host_list, node)
2599                 nand_release(&host->chip);
2600
2601         clk_disable_unprepare(ctrl->clk);
2602
2603         dev_set_drvdata(&pdev->dev, NULL);
2604
2605         return 0;
2606 }
2607 EXPORT_SYMBOL_GPL(brcmnand_remove);
2608
2609 MODULE_LICENSE("GPL v2");
2610 MODULE_AUTHOR("Kevin Cernekee");
2611 MODULE_AUTHOR("Brian Norris");
2612 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2613 MODULE_ALIAS("platform:brcmnand");