2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
4 * Author: Mike Lavender, mike@steroidmicros.com
6 * Copyright (c) 2005, Intec Automation Inc.
8 * Some parts are based on lart.c by Abraham Van Der Merwe
10 * Cleaned up and generalized based on mtd_dataflash.c
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <linux/err.h>
19 #include <linux/errno.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/flash.h>
28 #include <linux/mtd/spi-nor.h>
30 #define MAX_CMD_SIZE 6
32 struct spi_device *spi;
33 struct spi_nor spi_nor;
34 u8 command[MAX_CMD_SIZE];
37 static int m25p80_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
39 struct m25p *flash = nor->priv;
40 struct spi_device *spi = flash->spi;
43 ret = spi_write_then_read(spi, &code, 1, val, len);
45 dev_err(&spi->dev, "error %d reading %x\n", ret, code);
50 static void m25p_addr2cmd(struct spi_nor *nor, unsigned int addr, u8 *cmd)
52 /* opcode is in cmd[0] */
53 cmd[1] = addr >> (nor->addr_width * 8 - 8);
54 cmd[2] = addr >> (nor->addr_width * 8 - 16);
55 cmd[3] = addr >> (nor->addr_width * 8 - 24);
56 cmd[4] = addr >> (nor->addr_width * 8 - 32);
59 static int m25p_cmdsz(struct spi_nor *nor)
61 return 1 + nor->addr_width;
64 static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
66 struct m25p *flash = nor->priv;
67 struct spi_device *spi = flash->spi;
69 flash->command[0] = opcode;
71 memcpy(&flash->command[1], buf, len);
73 return spi_write(spi, flash->command, len + 1);
76 static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
79 struct m25p *flash = nor->priv;
80 struct spi_device *spi = flash->spi;
81 unsigned int inst_nbits, addr_nbits, data_nbits, data_idx;
82 struct spi_transfer t[3] = {};
84 int cmd_sz = m25p_cmdsz(nor);
87 /* get transfer protocols. */
88 inst_nbits = spi_nor_get_protocol_inst_nbits(nor->write_proto);
89 addr_nbits = spi_nor_get_protocol_addr_nbits(nor->write_proto);
90 data_nbits = spi_nor_get_protocol_data_nbits(nor->write_proto);
94 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
97 flash->command[0] = nor->program_opcode;
98 m25p_addr2cmd(nor, to, flash->command);
100 t[0].tx_buf = flash->command;
101 t[0].tx_nbits = inst_nbits;
103 spi_message_add_tail(&t[0], &m);
105 /* split the op code and address bytes into two transfers if needed. */
107 if (addr_nbits != inst_nbits) {
110 t[1].tx_buf = &flash->command[1];
111 t[1].tx_nbits = addr_nbits;
112 t[1].len = cmd_sz - 1;
113 spi_message_add_tail(&t[1], &m);
118 t[data_idx].tx_buf = buf;
119 t[data_idx].tx_nbits = data_nbits;
120 t[data_idx].len = len;
121 spi_message_add_tail(&t[data_idx], &m);
123 ret = spi_sync(spi, &m);
127 ret = m.actual_length - cmd_sz;
134 * Read an address range from the nor chip. The address range
135 * may be any size provided it is within the physical boundaries.
137 static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
140 struct m25p *flash = nor->priv;
141 struct spi_device *spi = flash->spi;
142 unsigned int inst_nbits, addr_nbits, data_nbits, data_idx;
143 struct spi_transfer t[3];
144 struct spi_message m;
145 unsigned int dummy = nor->read_dummy;
149 /* get transfer protocols. */
150 inst_nbits = spi_nor_get_protocol_inst_nbits(nor->read_proto);
151 addr_nbits = spi_nor_get_protocol_addr_nbits(nor->read_proto);
152 data_nbits = spi_nor_get_protocol_data_nbits(nor->read_proto);
154 /* convert the dummy cycles to the number of bytes */
155 dummy = (dummy * addr_nbits) / 8;
157 if (spi_flash_read_supported(spi)) {
158 struct spi_flash_read_message msg;
160 memset(&msg, 0, sizeof(msg));
165 msg.read_opcode = nor->read_opcode;
166 msg.addr_width = nor->addr_width;
167 msg.dummy_bytes = dummy;
168 msg.opcode_nbits = inst_nbits;
169 msg.addr_nbits = addr_nbits;
170 msg.data_nbits = data_nbits;
172 ret = spi_flash_read(spi, &msg);
178 spi_message_init(&m);
179 memset(t, 0, (sizeof t));
181 flash->command[0] = nor->read_opcode;
182 m25p_addr2cmd(nor, from, flash->command);
184 t[0].tx_buf = flash->command;
185 t[0].tx_nbits = inst_nbits;
186 t[0].len = m25p_cmdsz(nor) + dummy;
187 spi_message_add_tail(&t[0], &m);
190 * Set all dummy/mode cycle bits to avoid sending some manufacturer
191 * specific pattern, which might make the memory enter its Continuous
192 * Read mode by mistake.
193 * Based on the different mode cycle bit patterns listed and described
194 * in the JESD216B specification, the 0xff value works for all memories
195 * and all manufacturers.
198 memset(flash->command + cmd_sz - dummy, 0xff, dummy);
200 /* split the op code and address bytes into two transfers if needed. */
202 if (addr_nbits != inst_nbits) {
205 t[1].tx_buf = &flash->command[1];
206 t[1].tx_nbits = addr_nbits;
207 t[1].len = cmd_sz - 1;
208 spi_message_add_tail(&t[1], &m);
213 t[data_idx].rx_buf = buf;
214 t[data_idx].rx_nbits = data_nbits;
215 t[data_idx].len = min3(len, spi_max_transfer_size(spi),
216 spi_max_message_size(spi) - cmd_sz);
217 spi_message_add_tail(&t[data_idx], &m);
219 ret = spi_sync(spi, &m);
223 ret = m.actual_length - cmd_sz;
230 * board specific setup should have ensured the SPI clock used here
231 * matches what the READ command supports, at least until this driver
232 * understands FAST_READ (for clocks over 25 MHz).
234 static int m25p_probe(struct spi_device *spi)
236 struct flash_platform_data *data;
239 struct spi_nor_hwcaps hwcaps = {
240 .mask = SNOR_HWCAPS_READ |
241 SNOR_HWCAPS_READ_FAST |
247 data = dev_get_platdata(&spi->dev);
249 flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
253 nor = &flash->spi_nor;
255 /* install the hooks */
256 nor->read = m25p80_read;
257 nor->write = m25p80_write;
258 nor->write_reg = m25p80_write_reg;
259 nor->read_reg = m25p80_read_reg;
261 nor->dev = &spi->dev;
262 spi_nor_set_flash_node(nor, spi->dev.of_node);
265 spi_set_drvdata(spi, flash);
268 if (spi->mode & SPI_RX_QUAD) {
269 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
271 if (spi->mode & SPI_TX_QUAD)
272 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
273 SNOR_HWCAPS_PP_1_1_4 |
274 SNOR_HWCAPS_PP_1_4_4);
275 } else if (spi->mode & SPI_RX_DUAL) {
276 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
278 if (spi->mode & SPI_TX_DUAL)
279 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
282 if (data && data->name)
283 nor->mtd.name = data->name;
285 /* For some (historical?) reason many platforms provide two different
286 * names in flash_platform_data: "name" and "type". Quite often name is
287 * set to "m25p80" and then "type" provides a real chip name.
288 * If that's the case, respect "type" and ignore a "name".
290 if (data && data->type)
291 flash_name = data->type;
292 else if (!strcmp(spi->modalias, "spi-nor"))
293 flash_name = NULL; /* auto-detect */
295 flash_name = spi->modalias;
297 ret = spi_nor_scan(nor, flash_name, &hwcaps);
301 return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
302 data ? data->nr_parts : 0);
306 static int m25p_remove(struct spi_device *spi)
308 struct m25p *flash = spi_get_drvdata(spi);
310 /* Clean up MTD stuff. */
311 return mtd_device_unregister(&flash->spi_nor.mtd);
315 * Do NOT add to this array without reading the following:
317 * Historically, many flash devices are bound to this driver by their name. But
318 * since most of these flash are compatible to some extent, and their
319 * differences can often be differentiated by the JEDEC read-ID command, we
320 * encourage new users to add support to the spi-nor library, and simply bind
321 * against a generic string here (e.g., "jedec,spi-nor").
323 * Many flash names are kept here in this list (as well as in spi-nor.c) to
324 * keep them available as module aliases for existing platforms.
326 static const struct spi_device_id m25p_ids[] = {
328 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and
329 * hack around the fact that the SPI core does not provide uevent
330 * matching for .of_match_table
335 * Entries not used in DTs that should be safe to drop after replacing
336 * them with "spi-nor" in platform data.
338 {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"},
341 * Entries that were used in DTs without "jedec,spi-nor" fallback and
342 * should be kept for backward compatibility.
344 {"at25df321a"}, {"at25df641"}, {"at26df081a"},
345 {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"},
346 {"mx25l25635e"},{"mx66l51235l"},
347 {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"},
348 {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"},
350 {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
351 {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"},
352 {"m25p64"}, {"m25p128"},
353 {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
354 {"w25q80bl"}, {"w25q128"}, {"w25q256"},
356 /* Flashes that can't be detected using JEDEC */
357 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
358 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
359 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
361 /* Everspin MRAMs (non-JEDEC) */
362 { "mr25h256" }, /* 256 Kib, 40 MHz */
363 { "mr25h10" }, /* 1 Mib, 40 MHz */
364 { "mr25h40" }, /* 4 Mib, 40 MHz */
368 MODULE_DEVICE_TABLE(spi, m25p_ids);
370 static const struct of_device_id m25p_of_table[] = {
372 * Generic compatibility for SPI NOR that can be identified by the
373 * JEDEC READ ID opcode (0x9F). Use this, if possible.
375 { .compatible = "jedec,spi-nor" },
378 MODULE_DEVICE_TABLE(of, m25p_of_table);
380 static struct spi_driver m25p80_driver = {
383 .of_match_table = m25p_of_table,
385 .id_table = m25p_ids,
387 .remove = m25p_remove,
389 /* REVISIT: many of these chips have deep power-down modes, which
390 * should clearly be entered on suspend() to minimize power use.
391 * And also when they're otherwise idle...
395 module_spi_driver(m25p80_driver);
397 MODULE_LICENSE("GPL");
398 MODULE_AUTHOR("Mike Lavender");
399 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");