2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
28 #include <asm/byteorder.h>
30 #include <linux/errno.h>
31 #include <linux/slab.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/reboot.h>
36 #include <linux/of_platform.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
47 #define SST49LF004B 0x0060
48 #define SST49LF040B 0x0050
49 #define SST49LF008A 0x005a
50 #define AT49BV6416 0x00d6
53 * Status Register bit description. Used by flash devices that don't
54 * support DQ polling (e.g. HyperFlash)
56 #define CFI_SR_DRB BIT(7)
57 #define CFI_SR_ESB BIT(5)
58 #define CFI_SR_PSB BIT(4)
59 #define CFI_SR_WBASB BIT(3)
60 #define CFI_SR_SLSB BIT(1)
63 CFI_QUIRK_DQ_TRUE_DATA = BIT(0),
66 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
67 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
69 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
71 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
72 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
73 static void cfi_amdstd_sync (struct mtd_info *);
74 static int cfi_amdstd_suspend (struct mtd_info *);
75 static void cfi_amdstd_resume (struct mtd_info *);
76 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
77 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *, size_t,
78 size_t *, struct otp_info *);
79 static int cfi_amdstd_get_user_prot_info(struct mtd_info *, size_t,
80 size_t *, struct otp_info *);
81 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
82 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *, loff_t, size_t,
84 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *, loff_t, size_t,
86 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *, loff_t, size_t,
88 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *, loff_t, size_t);
90 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
91 size_t *retlen, const u_char *buf);
93 static void cfi_amdstd_destroy(struct mtd_info *);
95 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
96 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
98 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
99 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
100 #include "fwh_lock.h"
102 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
103 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
105 static int cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
106 static int cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
107 static int cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
109 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
110 .probe = NULL, /* Not usable directly */
111 .destroy = cfi_amdstd_destroy,
112 .name = "cfi_cmdset_0002",
113 .module = THIS_MODULE
117 * Use status register to poll for Erase/write completion when DQ is not
118 * supported. This is indicated by Bit[1:0] of SoftwareFeatures field in
119 * CFI Primary Vendor-Specific Extended Query table 1.5
121 static int cfi_use_status_reg(struct cfi_private *cfi)
123 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
124 u8 poll_mask = CFI_POLL_STATUS_REG | CFI_POLL_DQ;
126 return extp && extp->MinorVersion >= '5' &&
127 (extp->SoftwareFeatures & poll_mask) == CFI_POLL_STATUS_REG;
130 static int cfi_check_err_status(struct map_info *map, struct flchip *chip,
133 struct cfi_private *cfi = map->fldrv_priv;
136 if (!cfi_use_status_reg(cfi))
139 cfi_send_gen_cmd(0x70, cfi->addr_unlock1, chip->start, map, cfi,
140 cfi->device_type, NULL);
141 status = map_read(map, adr);
143 /* The error bits are invalid while the chip's busy */
144 if (!map_word_bitsset(map, status, CMD(CFI_SR_DRB)))
147 if (map_word_bitsset(map, status, CMD(0x3a))) {
148 unsigned long chipstatus = MERGESTATUS(status);
150 if (chipstatus & CFI_SR_ESB)
151 pr_err("%s erase operation failed, status %lx\n",
152 map->name, chipstatus);
153 if (chipstatus & CFI_SR_PSB)
154 pr_err("%s program operation failed, status %lx\n",
155 map->name, chipstatus);
156 if (chipstatus & CFI_SR_WBASB)
157 pr_err("%s buffer program command aborted, status %lx\n",
158 map->name, chipstatus);
159 if (chipstatus & CFI_SR_SLSB)
160 pr_err("%s sector write protected, status %lx\n",
161 map->name, chipstatus);
163 /* Erase/Program status bits are set on the operation failure */
164 if (chipstatus & (CFI_SR_ESB | CFI_SR_PSB))
170 /* #define DEBUG_CFI_FEATURES */
173 #ifdef DEBUG_CFI_FEATURES
174 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
176 const char* erase_suspend[3] = {
177 "Not supported", "Read only", "Read/write"
179 const char* top_bottom[6] = {
180 "No WP", "8x8KiB sectors at top & bottom, no WP",
181 "Bottom boot", "Top boot",
182 "Uniform, Bottom WP", "Uniform, Top WP"
185 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
186 printk(" Address sensitive unlock: %s\n",
187 (extp->SiliconRevision & 1) ? "Not required" : "Required");
189 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
190 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
192 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
194 if (extp->BlkProt == 0)
195 printk(" Block protection: Not supported\n");
197 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
200 printk(" Temporary block unprotect: %s\n",
201 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
202 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
203 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
204 printk(" Burst mode: %s\n",
205 extp->BurstMode ? "Supported" : "Not supported");
206 if (extp->PageMode == 0)
207 printk(" Page mode: Not supported\n");
209 printk(" Page mode: %d word page\n", extp->PageMode << 2);
211 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
212 extp->VppMin >> 4, extp->VppMin & 0xf);
213 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
214 extp->VppMax >> 4, extp->VppMax & 0xf);
216 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
217 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
219 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
223 #ifdef AMD_BOOTLOC_BUG
224 /* Wheee. Bring me the head of someone at AMD. */
225 static void fixup_amd_bootblock(struct mtd_info *mtd)
227 struct map_info *map = mtd->priv;
228 struct cfi_private *cfi = map->fldrv_priv;
229 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
230 __u8 major = extp->MajorVersion;
231 __u8 minor = extp->MinorVersion;
233 if (((major << 8) | minor) < 0x3131) {
234 /* CFI version 1.0 => don't trust bootloc */
236 pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
237 map->name, cfi->mfr, cfi->id);
239 /* AFAICS all 29LV400 with a bottom boot block have a device ID
240 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
241 * These were badly detected as they have the 0x80 bit set
242 * so treat them as a special case.
244 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
246 /* Macronix added CFI to their 2nd generation
247 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
248 * Fujitsu, Spansion, EON, ESI and older Macronix)
251 * Therefore also check the manufacturer.
252 * This reduces the risk of false detection due to
253 * the 8-bit device ID.
255 (cfi->mfr == CFI_MFR_MACRONIX)) {
256 pr_debug("%s: Macronix MX29LV400C with bottom boot block"
257 " detected\n", map->name);
258 extp->TopBottom = 2; /* bottom boot */
260 if (cfi->id & 0x80) {
261 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
262 extp->TopBottom = 3; /* top boot */
264 extp->TopBottom = 2; /* bottom boot */
267 pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;"
268 " deduced %s from Device ID\n", map->name, major, minor,
269 extp->TopBottom == 2 ? "bottom" : "top");
274 #if !FORCE_WORD_WRITE
275 static void fixup_use_write_buffers(struct mtd_info *mtd)
277 struct map_info *map = mtd->priv;
278 struct cfi_private *cfi = map->fldrv_priv;
279 if (cfi->cfiq->BufWriteTimeoutTyp) {
280 pr_debug("Using buffer write method\n");
281 mtd->_write = cfi_amdstd_write_buffers;
284 #endif /* !FORCE_WORD_WRITE */
286 /* Atmel chips don't use the same PRI format as AMD chips */
287 static void fixup_convert_atmel_pri(struct mtd_info *mtd)
289 struct map_info *map = mtd->priv;
290 struct cfi_private *cfi = map->fldrv_priv;
291 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
292 struct cfi_pri_atmel atmel_pri;
294 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
295 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
297 if (atmel_pri.Features & 0x02)
298 extp->EraseSuspend = 2;
300 /* Some chips got it backwards... */
301 if (cfi->id == AT49BV6416) {
302 if (atmel_pri.BottomBoot)
307 if (atmel_pri.BottomBoot)
313 /* burst write mode not supported */
314 cfi->cfiq->BufWriteTimeoutTyp = 0;
315 cfi->cfiq->BufWriteTimeoutMax = 0;
318 static void fixup_use_secsi(struct mtd_info *mtd)
320 /* Setup for chips with a secsi area */
321 mtd->_read_user_prot_reg = cfi_amdstd_secsi_read;
322 mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read;
325 static void fixup_use_erase_chip(struct mtd_info *mtd)
327 struct map_info *map = mtd->priv;
328 struct cfi_private *cfi = map->fldrv_priv;
329 if ((cfi->cfiq->NumEraseRegions == 1) &&
330 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
331 mtd->_erase = cfi_amdstd_erase_chip;
337 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
340 static void fixup_use_atmel_lock(struct mtd_info *mtd)
342 mtd->_lock = cfi_atmel_lock;
343 mtd->_unlock = cfi_atmel_unlock;
344 mtd->flags |= MTD_POWERUP_LOCK;
347 static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
349 struct map_info *map = mtd->priv;
350 struct cfi_private *cfi = map->fldrv_priv;
353 * These flashes report two separate eraseblock regions based on the
354 * sector_erase-size and block_erase-size, although they both operate on the
355 * same memory. This is not allowed according to CFI, so we just pick the
358 cfi->cfiq->NumEraseRegions = 1;
361 static void fixup_sst39vf(struct mtd_info *mtd)
363 struct map_info *map = mtd->priv;
364 struct cfi_private *cfi = map->fldrv_priv;
366 fixup_old_sst_eraseregion(mtd);
368 cfi->addr_unlock1 = 0x5555;
369 cfi->addr_unlock2 = 0x2AAA;
372 static void fixup_sst39vf_rev_b(struct mtd_info *mtd)
374 struct map_info *map = mtd->priv;
375 struct cfi_private *cfi = map->fldrv_priv;
377 fixup_old_sst_eraseregion(mtd);
379 cfi->addr_unlock1 = 0x555;
380 cfi->addr_unlock2 = 0x2AA;
382 cfi->sector_erase_cmd = CMD(0x50);
385 static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd)
387 struct map_info *map = mtd->priv;
388 struct cfi_private *cfi = map->fldrv_priv;
390 fixup_sst39vf_rev_b(mtd);
393 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where
394 * it should report a size of 8KBytes (0x0020*256).
396 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff;
397 pr_warn("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n",
401 static void fixup_s29gl064n_sectors(struct mtd_info *mtd)
403 struct map_info *map = mtd->priv;
404 struct cfi_private *cfi = map->fldrv_priv;
406 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
407 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
408 pr_warn("%s: Bad S29GL064N CFI data; adjust from 64 to 128 sectors\n",
413 static void fixup_s29gl032n_sectors(struct mtd_info *mtd)
415 struct map_info *map = mtd->priv;
416 struct cfi_private *cfi = map->fldrv_priv;
418 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
419 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
420 pr_warn("%s: Bad S29GL032N CFI data; adjust from 127 to 63 sectors\n",
425 static void fixup_s29ns512p_sectors(struct mtd_info *mtd)
427 struct map_info *map = mtd->priv;
428 struct cfi_private *cfi = map->fldrv_priv;
431 * S29NS512P flash uses more than 8bits to report number of sectors,
432 * which is not permitted by CFI.
434 cfi->cfiq->EraseRegionInfo[0] = 0x020001ff;
435 pr_warn("%s: Bad S29NS512P CFI data; adjust to 512 sectors\n",
439 static void fixup_quirks(struct mtd_info *mtd)
441 struct map_info *map = mtd->priv;
442 struct cfi_private *cfi = map->fldrv_priv;
444 if (cfi->mfr == CFI_MFR_AMD && cfi->id == 0x0c01)
445 cfi->quirks |= CFI_QUIRK_DQ_TRUE_DATA;
448 /* Used to fix CFI-Tables of chips without Extended Query Tables */
449 static struct cfi_fixup cfi_nopri_fixup_table[] = {
450 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */
451 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */
452 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */
453 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */
454 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */
455 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */
456 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */
457 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */
461 static struct cfi_fixup cfi_fixup_table[] = {
462 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri },
463 #ifdef AMD_BOOTLOC_BUG
464 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock },
465 { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock },
466 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock },
468 { CFI_MFR_AMD, 0x0050, fixup_use_secsi },
469 { CFI_MFR_AMD, 0x0053, fixup_use_secsi },
470 { CFI_MFR_AMD, 0x0055, fixup_use_secsi },
471 { CFI_MFR_AMD, 0x0056, fixup_use_secsi },
472 { CFI_MFR_AMD, 0x005C, fixup_use_secsi },
473 { CFI_MFR_AMD, 0x005F, fixup_use_secsi },
474 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors },
475 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors },
476 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors },
477 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors },
478 { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors },
479 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */
480 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */
481 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */
482 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */
483 #if !FORCE_WORD_WRITE
484 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers },
486 { CFI_MFR_ANY, CFI_ID_ANY, fixup_quirks },
489 static struct cfi_fixup jedec_fixup_table[] = {
490 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock },
491 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock },
492 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock },
496 static struct cfi_fixup fixup_table[] = {
497 /* The CFI vendor ids and the JEDEC vendor IDs appear
498 * to be common. It is like the devices id's are as
499 * well. This table is to pick all cases where
500 * we know that is the case.
502 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip },
503 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock },
508 static void cfi_fixup_major_minor(struct cfi_private *cfi,
509 struct cfi_pri_amdstd *extp)
511 if (cfi->mfr == CFI_MFR_SAMSUNG) {
512 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') ||
513 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) {
515 * Samsung K8P2815UQB and K8D6x16UxM chips
516 * report major=0 / minor=0.
517 * K8D3x16UxC chips report major=3 / minor=3.
519 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu"
520 " Extended Query version to 1.%c\n",
522 extp->MajorVersion = '1';
527 * SST 38VF640x chips report major=0xFF / minor=0xFF.
529 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) {
530 extp->MajorVersion = '1';
531 extp->MinorVersion = '0';
535 static int is_m29ew(struct cfi_private *cfi)
537 if (cfi->mfr == CFI_MFR_INTEL &&
538 ((cfi->device_type == CFI_DEVICETYPE_X8 && (cfi->id & 0xff) == 0x7e) ||
539 (cfi->device_type == CFI_DEVICETYPE_X16 && cfi->id == 0x227e)))
545 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 20:
546 * Some revisions of the M29EW suffer from erase suspend hang ups. In
547 * particular, it can occur when the sequence
548 * Erase Confirm -> Suspend -> Program -> Resume
549 * causes a lockup due to internal timing issues. The consequence is that the
550 * erase cannot be resumed without inserting a dummy command after programming
551 * and prior to resuming. [...] The work-around is to issue a dummy write cycle
552 * that writes an F0 command code before the RESUME command.
554 static void cfi_fixup_m29ew_erase_suspend(struct map_info *map,
557 struct cfi_private *cfi = map->fldrv_priv;
558 /* before resume, insert a dummy 0xF0 cycle for Micron M29EW devices */
560 map_write(map, CMD(0xF0), adr);
564 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 22:
566 * Some revisions of the M29EW (for example, A1 and A2 step revisions)
567 * are affected by a problem that could cause a hang up when an ERASE SUSPEND
568 * command is issued after an ERASE RESUME operation without waiting for a
569 * minimum delay. The result is that once the ERASE seems to be completed
570 * (no bits are toggling), the contents of the Flash memory block on which
571 * the erase was ongoing could be inconsistent with the expected values
572 * (typically, the array value is stuck to the 0xC0, 0xC4, 0x80, or 0x84
573 * values), causing a consequent failure of the ERASE operation.
574 * The occurrence of this issue could be high, especially when file system
575 * operations on the Flash are intensive. As a result, it is recommended
576 * that a patch be applied. Intensive file system operations can cause many
577 * calls to the garbage routine to free Flash space (also by erasing physical
578 * Flash blocks) and as a result, many consecutive SUSPEND and RESUME
579 * commands can occur. The problem disappears when a delay is inserted after
580 * the RESUME command by using the udelay() function available in Linux.
581 * The DELAY value must be tuned based on the customer's platform.
582 * The maximum value that fixes the problem in all cases is 500us.
583 * But, in our experience, a delay of 30 µs to 50 µs is sufficient
585 * We have chosen 500µs because this latency is acceptable.
587 static void cfi_fixup_m29ew_delay_after_resume(struct cfi_private *cfi)
590 * Resolving the Delay After Resume Issue see Micron TN-13-07
591 * Worst case delay must be 500µs but 30-50µs should be ok as well
597 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
599 struct cfi_private *cfi = map->fldrv_priv;
600 struct device_node __maybe_unused *np = map->device_node;
601 struct mtd_info *mtd;
604 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
608 mtd->type = MTD_NORFLASH;
610 /* Fill in the default mtd operations */
611 mtd->_erase = cfi_amdstd_erase_varsize;
612 mtd->_write = cfi_amdstd_write_words;
613 mtd->_read = cfi_amdstd_read;
614 mtd->_sync = cfi_amdstd_sync;
615 mtd->_suspend = cfi_amdstd_suspend;
616 mtd->_resume = cfi_amdstd_resume;
617 mtd->_read_user_prot_reg = cfi_amdstd_read_user_prot_reg;
618 mtd->_read_fact_prot_reg = cfi_amdstd_read_fact_prot_reg;
619 mtd->_get_fact_prot_info = cfi_amdstd_get_fact_prot_info;
620 mtd->_get_user_prot_info = cfi_amdstd_get_user_prot_info;
621 mtd->_write_user_prot_reg = cfi_amdstd_write_user_prot_reg;
622 mtd->_lock_user_prot_reg = cfi_amdstd_lock_user_prot_reg;
623 mtd->flags = MTD_CAP_NORFLASH;
624 mtd->name = map->name;
626 mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
628 pr_debug("MTD %s(): write buffer size %d\n", __func__,
631 mtd->_panic_write = cfi_amdstd_panic_write;
632 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
634 if (cfi->cfi_mode==CFI_MODE_CFI){
635 unsigned char bootloc;
636 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
637 struct cfi_pri_amdstd *extp;
639 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
642 * It's a real CFI chip, not one for which the probe
643 * routine faked a CFI structure.
645 cfi_fixup_major_minor(cfi, extp);
648 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5
649 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19
650 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf
651 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf
652 * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf
654 if (extp->MajorVersion != '1' ||
655 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) {
656 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
657 "version %c.%c (%#02x/%#02x).\n",
658 extp->MajorVersion, extp->MinorVersion,
659 extp->MajorVersion, extp->MinorVersion);
665 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n",
666 extp->MajorVersion, extp->MinorVersion);
668 /* Install our own private info structure */
669 cfi->cmdset_priv = extp;
671 /* Apply cfi device specific fixups */
672 cfi_fixup(mtd, cfi_fixup_table);
674 #ifdef DEBUG_CFI_FEATURES
675 /* Tell the user about it in lots of lovely detail */
676 cfi_tell_features(extp);
680 if (np && of_property_read_bool(
681 np, "use-advanced-sector-protection")
682 && extp->BlkProtUnprot == 8) {
683 printk(KERN_INFO " Advanced Sector Protection (PPB Locking) supported\n");
684 mtd->_lock = cfi_ppb_lock;
685 mtd->_unlock = cfi_ppb_unlock;
686 mtd->_is_locked = cfi_ppb_is_locked;
690 bootloc = extp->TopBottom;
691 if ((bootloc < 2) || (bootloc > 5)) {
692 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
693 "bank location (%d). Assuming bottom.\n",
698 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
699 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
701 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
702 int j = (cfi->cfiq->NumEraseRegions-1)-i;
704 swap(cfi->cfiq->EraseRegionInfo[i],
705 cfi->cfiq->EraseRegionInfo[j]);
708 /* Set the default CFI lock/unlock addresses */
709 cfi->addr_unlock1 = 0x555;
710 cfi->addr_unlock2 = 0x2aa;
712 cfi_fixup(mtd, cfi_nopri_fixup_table);
714 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
720 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
721 /* Apply jedec specific fixups */
722 cfi_fixup(mtd, jedec_fixup_table);
724 /* Apply generic fixups */
725 cfi_fixup(mtd, fixup_table);
727 for (i=0; i< cfi->numchips; i++) {
728 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
729 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
730 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
732 * First calculate the timeout max according to timeout field
733 * of struct cfi_ident that probed from chip's CFI aera, if
734 * available. Specify a minimum of 2000us, in case the CFI data
737 if (cfi->cfiq->BufWriteTimeoutTyp &&
738 cfi->cfiq->BufWriteTimeoutMax)
739 cfi->chips[i].buffer_write_time_max =
740 1 << (cfi->cfiq->BufWriteTimeoutTyp +
741 cfi->cfiq->BufWriteTimeoutMax);
743 cfi->chips[i].buffer_write_time_max = 0;
745 cfi->chips[i].buffer_write_time_max =
746 max(cfi->chips[i].buffer_write_time_max, 2000);
748 cfi->chips[i].ref_point_counter = 0;
749 init_waitqueue_head(&(cfi->chips[i].wq));
752 map->fldrv = &cfi_amdstd_chipdrv;
754 return cfi_amdstd_setup(mtd);
756 struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
757 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
758 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
759 EXPORT_SYMBOL_GPL(cfi_cmdset_0006);
760 EXPORT_SYMBOL_GPL(cfi_cmdset_0701);
762 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
764 struct map_info *map = mtd->priv;
765 struct cfi_private *cfi = map->fldrv_priv;
766 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
767 unsigned long offset = 0;
770 printk(KERN_NOTICE "number of %s chips: %d\n",
771 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
772 /* Select the correct geometry setup */
773 mtd->size = devsize * cfi->numchips;
775 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
776 mtd->eraseregions = kmalloc_array(mtd->numeraseregions,
777 sizeof(struct mtd_erase_region_info),
779 if (!mtd->eraseregions)
782 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
783 unsigned long ernum, ersize;
784 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
785 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
787 if (mtd->erasesize < ersize) {
788 mtd->erasesize = ersize;
790 for (j=0; j<cfi->numchips; j++) {
791 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
792 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
793 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
795 offset += (ersize * ernum);
797 if (offset != devsize) {
799 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
803 __module_get(THIS_MODULE);
804 register_reboot_notifier(&mtd->reboot_notifier);
808 kfree(mtd->eraseregions);
810 kfree(cfi->cmdset_priv);
815 * Return true if the chip is ready and has the correct value.
817 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
818 * non-suspended sector) and is indicated by no toggle bits toggling.
820 * Error are indicated by toggling bits or bits held with the wrong value,
821 * or with bits toggling.
823 * Note that anything more complicated than checking if no bits are toggling
824 * (including checking DQ5 for an error status) is tricky to get working
825 * correctly and is therefore not done (particularly with interleaved chips
826 * as each chip must be checked independently of the others).
828 static int __xipram chip_ready(struct map_info *map, struct flchip *chip,
829 unsigned long addr, map_word *expected)
831 struct cfi_private *cfi = map->fldrv_priv;
835 if (cfi_use_status_reg(cfi)) {
836 map_word ready = CMD(CFI_SR_DRB);
838 * For chips that support status register, check device
841 cfi_send_gen_cmd(0x70, cfi->addr_unlock1, chip->start, map, cfi,
842 cfi->device_type, NULL);
843 t = map_read(map, addr);
845 return map_word_andequal(map, t, ready, ready);
848 d = map_read(map, addr);
849 t = map_read(map, addr);
851 ret = map_word_equal(map, d, t);
853 if (!ret || !expected)
856 return map_word_equal(map, t, *expected);
859 static int __xipram chip_good(struct map_info *map, struct flchip *chip,
860 unsigned long addr, map_word *expected)
862 struct cfi_private *cfi = map->fldrv_priv;
863 map_word *datum = expected;
865 if (cfi->quirks & CFI_QUIRK_DQ_TRUE_DATA)
868 return chip_ready(map, chip, addr, datum);
871 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
873 DECLARE_WAITQUEUE(wait, current);
874 struct cfi_private *cfi = map->fldrv_priv;
876 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
879 timeo = jiffies + HZ;
881 switch (chip->state) {
885 if (chip_ready(map, chip, adr, NULL))
888 if (time_after(jiffies, timeo)) {
889 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
892 mutex_unlock(&chip->mutex);
894 mutex_lock(&chip->mutex);
895 /* Someone else might have been playing with it. */
905 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
906 !(mode == FL_READY || mode == FL_POINT ||
907 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
910 /* Do not allow suspend iff read/write to EB address */
911 if ((adr & chip->in_progress_block_mask) ==
912 chip->in_progress_block_addr)
916 /* It's harmless to issue the Erase-Suspend and Erase-Resume
917 * commands when the erase algorithm isn't in progress. */
918 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
919 chip->oldstate = FL_ERASING;
920 chip->state = FL_ERASE_SUSPENDING;
921 chip->erase_suspended = 1;
923 if (chip_ready(map, chip, adr, NULL))
926 if (time_after(jiffies, timeo)) {
927 /* Should have suspended the erase by now.
928 * Send an Erase-Resume command as either
929 * there was an error (so leave the erase
930 * routine to recover from it) or we trying to
931 * use the erase-in-progress sector. */
932 put_chip(map, chip, adr);
933 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
937 mutex_unlock(&chip->mutex);
939 mutex_lock(&chip->mutex);
940 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
941 So we can just loop here. */
943 chip->state = FL_READY;
946 case FL_XIP_WHILE_ERASING:
947 if (mode != FL_READY && mode != FL_POINT &&
948 (!cfip || !(cfip->EraseSuspend&2)))
950 chip->oldstate = chip->state;
951 chip->state = FL_READY;
955 /* The machine is rebooting */
959 /* Only if there's no operation suspended... */
960 if (mode == FL_READY && chip->oldstate == FL_READY)
965 set_current_state(TASK_UNINTERRUPTIBLE);
966 add_wait_queue(&chip->wq, &wait);
967 mutex_unlock(&chip->mutex);
969 remove_wait_queue(&chip->wq, &wait);
970 mutex_lock(&chip->mutex);
976 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
978 struct cfi_private *cfi = map->fldrv_priv;
980 switch(chip->oldstate) {
982 cfi_fixup_m29ew_erase_suspend(map,
983 chip->in_progress_block_addr);
984 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
985 cfi_fixup_m29ew_delay_after_resume(cfi);
986 chip->oldstate = FL_READY;
987 chip->state = FL_ERASING;
990 case FL_XIP_WHILE_ERASING:
991 chip->state = chip->oldstate;
992 chip->oldstate = FL_READY;
999 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
1004 #ifdef CONFIG_MTD_XIP
1007 * No interrupt what so ever can be serviced while the flash isn't in array
1008 * mode. This is ensured by the xip_disable() and xip_enable() functions
1009 * enclosing any code path where the flash is known not to be in array mode.
1010 * And within a XIP disabled code path, only functions marked with __xipram
1011 * may be called and nothing else (it's a good thing to inspect generated
1012 * assembly to make sure inline functions were actually inlined and that gcc
1013 * didn't emit calls to its own support functions). Also configuring MTD CFI
1014 * support to a single buswidth and a single interleave is also recommended.
1017 static void xip_disable(struct map_info *map, struct flchip *chip,
1020 /* TODO: chips with no XIP use should ignore and return */
1021 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
1022 local_irq_disable();
1025 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
1028 struct cfi_private *cfi = map->fldrv_priv;
1030 if (chip->state != FL_POINT && chip->state != FL_READY) {
1031 map_write(map, CMD(0xf0), adr);
1032 chip->state = FL_READY;
1034 (void) map_read(map, adr);
1040 * When a delay is required for the flash operation to complete, the
1041 * xip_udelay() function is polling for both the given timeout and pending
1042 * (but still masked) hardware interrupts. Whenever there is an interrupt
1043 * pending then the flash erase operation is suspended, array mode restored
1044 * and interrupts unmasked. Task scheduling might also happen at that
1045 * point. The CPU eventually returns from the interrupt or the call to
1046 * schedule() and the suspended flash operation is resumed for the remaining
1047 * of the delay period.
1049 * Warning: this function _will_ fool interrupt latency tracing tools.
1052 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
1053 unsigned long adr, int usec)
1055 struct cfi_private *cfi = map->fldrv_priv;
1056 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
1057 map_word status, OK = CMD(0x80);
1058 unsigned long suspended, start = xip_currtime();
1063 if (xip_irqpending() && extp &&
1064 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
1065 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
1067 * Let's suspend the erase operation when supported.
1068 * Note that we currently don't try to suspend
1069 * interleaved chips if there is already another
1070 * operation suspended (imagine what happens
1071 * when one chip was already done with the current
1072 * operation while another chip suspended it, then
1073 * we resume the whole thing at once). Yes, it
1076 map_write(map, CMD(0xb0), adr);
1077 usec -= xip_elapsed_since(start);
1078 suspended = xip_currtime();
1080 if (xip_elapsed_since(suspended) > 100000) {
1082 * The chip doesn't want to suspend
1083 * after waiting for 100 msecs.
1084 * This is a critical error but there
1085 * is not much we can do here.
1089 status = map_read(map, adr);
1090 } while (!map_word_andequal(map, status, OK, OK));
1092 /* Suspend succeeded */
1093 oldstate = chip->state;
1094 if (!map_word_bitsset(map, status, CMD(0x40)))
1096 chip->state = FL_XIP_WHILE_ERASING;
1097 chip->erase_suspended = 1;
1098 map_write(map, CMD(0xf0), adr);
1099 (void) map_read(map, adr);
1102 mutex_unlock(&chip->mutex);
1107 * We're back. However someone else might have
1108 * decided to go write to the chip if we are in
1109 * a suspended erase state. If so let's wait
1112 mutex_lock(&chip->mutex);
1113 while (chip->state != FL_XIP_WHILE_ERASING) {
1114 DECLARE_WAITQUEUE(wait, current);
1115 set_current_state(TASK_UNINTERRUPTIBLE);
1116 add_wait_queue(&chip->wq, &wait);
1117 mutex_unlock(&chip->mutex);
1119 remove_wait_queue(&chip->wq, &wait);
1120 mutex_lock(&chip->mutex);
1122 /* Disallow XIP again */
1123 local_irq_disable();
1125 /* Correct Erase Suspend Hangups for M29EW */
1126 cfi_fixup_m29ew_erase_suspend(map, adr);
1127 /* Resume the write or erase operation */
1128 map_write(map, cfi->sector_erase_cmd, adr);
1129 chip->state = oldstate;
1130 start = xip_currtime();
1131 } else if (usec >= 1000000/HZ) {
1133 * Try to save on CPU power when waiting delay
1134 * is at least a system timer tick period.
1135 * No need to be extremely accurate here.
1139 status = map_read(map, adr);
1140 } while (!map_word_andequal(map, status, OK, OK)
1141 && xip_elapsed_since(start) < usec);
1144 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
1147 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
1148 * the flash is actively programming or erasing since we have to poll for
1149 * the operation to complete anyway. We can't do that in a generic way with
1150 * a XIP setup so do it before the actual flash operation in this case
1151 * and stub it out from INVALIDATE_CACHE_UDELAY.
1153 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
1154 INVALIDATE_CACHED_RANGE(map, from, size)
1156 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1157 UDELAY(map, chip, adr, usec)
1162 * Activating this XIP support changes the way the code works a bit. For
1163 * example the code to suspend the current process when concurrent access
1164 * happens is never executed because xip_udelay() will always return with the
1165 * same chip state as it was entered with. This is why there is no care for
1166 * the presence of add_wait_queue() or schedule() calls from within a couple
1167 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
1168 * The queueing and scheduling are always happening within xip_udelay().
1170 * Similarly, get_chip() and put_chip() just happen to always be executed
1171 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
1172 * is in array mode, therefore never executing many cases therein and not
1173 * causing any problem with XIP.
1178 #define xip_disable(map, chip, adr)
1179 #define xip_enable(map, chip, adr)
1180 #define XIP_INVAL_CACHED_RANGE(x...)
1182 #define UDELAY(map, chip, adr, usec) \
1184 mutex_unlock(&chip->mutex); \
1186 mutex_lock(&chip->mutex); \
1189 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1191 mutex_unlock(&chip->mutex); \
1192 INVALIDATE_CACHED_RANGE(map, adr, len); \
1194 mutex_lock(&chip->mutex); \
1199 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1201 unsigned long cmd_addr;
1202 struct cfi_private *cfi = map->fldrv_priv;
1207 /* Ensure cmd read/writes are aligned. */
1208 cmd_addr = adr & ~(map_bankwidth(map)-1);
1210 mutex_lock(&chip->mutex);
1211 ret = get_chip(map, chip, cmd_addr, FL_READY);
1213 mutex_unlock(&chip->mutex);
1217 if (chip->state != FL_POINT && chip->state != FL_READY) {
1218 map_write(map, CMD(0xf0), cmd_addr);
1219 chip->state = FL_READY;
1222 map_copy_from(map, buf, adr, len);
1224 put_chip(map, chip, cmd_addr);
1226 mutex_unlock(&chip->mutex);
1231 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1233 struct map_info *map = mtd->priv;
1234 struct cfi_private *cfi = map->fldrv_priv;
1239 /* ofs: offset within the first chip that the first read should start */
1240 chipnum = (from >> cfi->chipshift);
1241 ofs = from - (chipnum << cfi->chipshift);
1244 unsigned long thislen;
1246 if (chipnum >= cfi->numchips)
1249 if ((len + ofs -1) >> cfi->chipshift)
1250 thislen = (1<<cfi->chipshift) - ofs;
1254 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1268 typedef int (*otp_op_t)(struct map_info *map, struct flchip *chip,
1269 loff_t adr, size_t len, u_char *buf, size_t grouplen);
1271 static inline void otp_enter(struct map_info *map, struct flchip *chip,
1272 loff_t adr, size_t len)
1274 struct cfi_private *cfi = map->fldrv_priv;
1276 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1277 cfi->device_type, NULL);
1278 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1279 cfi->device_type, NULL);
1280 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi,
1281 cfi->device_type, NULL);
1283 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1286 static inline void otp_exit(struct map_info *map, struct flchip *chip,
1287 loff_t adr, size_t len)
1289 struct cfi_private *cfi = map->fldrv_priv;
1291 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1292 cfi->device_type, NULL);
1293 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1294 cfi->device_type, NULL);
1295 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi,
1296 cfi->device_type, NULL);
1297 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi,
1298 cfi->device_type, NULL);
1300 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1303 static inline int do_read_secsi_onechip(struct map_info *map,
1304 struct flchip *chip, loff_t adr,
1305 size_t len, u_char *buf,
1308 DECLARE_WAITQUEUE(wait, current);
1311 mutex_lock(&chip->mutex);
1313 if (chip->state != FL_READY){
1314 set_current_state(TASK_UNINTERRUPTIBLE);
1315 add_wait_queue(&chip->wq, &wait);
1317 mutex_unlock(&chip->mutex);
1320 remove_wait_queue(&chip->wq, &wait);
1327 chip->state = FL_READY;
1329 otp_enter(map, chip, adr, len);
1330 map_copy_from(map, buf, adr, len);
1331 otp_exit(map, chip, adr, len);
1334 mutex_unlock(&chip->mutex);
1339 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1341 struct map_info *map = mtd->priv;
1342 struct cfi_private *cfi = map->fldrv_priv;
1347 /* ofs: offset within the first chip that the first read should start */
1348 /* 8 secsi bytes per chip */
1353 unsigned long thislen;
1355 if (chipnum >= cfi->numchips)
1358 if ((len + ofs -1) >> 3)
1359 thislen = (1<<3) - ofs;
1363 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs,
1378 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1379 unsigned long adr, map_word datum,
1382 static int do_otp_write(struct map_info *map, struct flchip *chip, loff_t adr,
1383 size_t len, u_char *buf, size_t grouplen)
1387 unsigned long bus_ofs = adr & ~(map_bankwidth(map)-1);
1388 int gap = adr - bus_ofs;
1389 int n = min_t(int, len, map_bankwidth(map) - gap);
1390 map_word datum = map_word_ff(map);
1392 if (n != map_bankwidth(map)) {
1393 /* partial write of a word, load old contents */
1394 otp_enter(map, chip, bus_ofs, map_bankwidth(map));
1395 datum = map_read(map, bus_ofs);
1396 otp_exit(map, chip, bus_ofs, map_bankwidth(map));
1399 datum = map_word_load_partial(map, datum, buf, gap, n);
1400 ret = do_write_oneword(map, chip, bus_ofs, datum, FL_OTP_WRITE);
1412 static int do_otp_lock(struct map_info *map, struct flchip *chip, loff_t adr,
1413 size_t len, u_char *buf, size_t grouplen)
1415 struct cfi_private *cfi = map->fldrv_priv;
1417 unsigned long timeo;
1420 /* make sure area matches group boundaries */
1421 if ((adr != 0) || (len != grouplen))
1424 mutex_lock(&chip->mutex);
1425 ret = get_chip(map, chip, chip->start, FL_LOCKING);
1427 mutex_unlock(&chip->mutex);
1430 chip->state = FL_LOCKING;
1432 /* Enter lock register command */
1433 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1434 cfi->device_type, NULL);
1435 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1436 cfi->device_type, NULL);
1437 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi,
1438 cfi->device_type, NULL);
1440 /* read lock register */
1441 lockreg = cfi_read_query(map, 0);
1443 /* set bit 0 to protect extended memory block */
1446 /* set bit 0 to protect extended memory block */
1447 /* write lock register */
1448 map_write(map, CMD(0xA0), chip->start);
1449 map_write(map, CMD(lockreg), chip->start);
1451 /* wait for chip to become ready */
1452 timeo = jiffies + msecs_to_jiffies(2);
1454 if (chip_ready(map, chip, adr, NULL))
1457 if (time_after(jiffies, timeo)) {
1458 pr_err("Waiting for chip to be ready timed out.\n");
1462 UDELAY(map, chip, 0, 1);
1465 /* exit protection commands */
1466 map_write(map, CMD(0x90), chip->start);
1467 map_write(map, CMD(0x00), chip->start);
1469 chip->state = FL_READY;
1470 put_chip(map, chip, chip->start);
1471 mutex_unlock(&chip->mutex);
1476 static int cfi_amdstd_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
1477 size_t *retlen, u_char *buf,
1478 otp_op_t action, int user_regs)
1480 struct map_info *map = mtd->priv;
1481 struct cfi_private *cfi = map->fldrv_priv;
1482 int ofs_factor = cfi->interleave * cfi->device_type;
1485 struct flchip *chip;
1486 uint8_t otp, lockreg;
1489 size_t user_size, factory_size, otpsize;
1490 loff_t user_offset, factory_offset, otpoffset;
1491 int user_locked = 0, otplocked;
1495 for (chipnum = 0; chipnum < cfi->numchips; chipnum++) {
1496 chip = &cfi->chips[chipnum];
1500 /* Micron M29EW family */
1501 if (is_m29ew(cfi)) {
1504 /* check whether secsi area is factory locked
1506 mutex_lock(&chip->mutex);
1507 ret = get_chip(map, chip, base, FL_CFI_QUERY);
1509 mutex_unlock(&chip->mutex);
1512 cfi_qry_mode_on(base, map, cfi);
1513 otp = cfi_read_query(map, base + 0x3 * ofs_factor);
1514 cfi_qry_mode_off(base, map, cfi);
1515 put_chip(map, chip, base);
1516 mutex_unlock(&chip->mutex);
1519 /* factory locked */
1521 factory_size = 0x100;
1523 /* customer lockable */
1527 mutex_lock(&chip->mutex);
1528 ret = get_chip(map, chip, base, FL_LOCKING);
1530 mutex_unlock(&chip->mutex);
1534 /* Enter lock register command */
1535 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1,
1536 chip->start, map, cfi,
1537 cfi->device_type, NULL);
1538 cfi_send_gen_cmd(0x55, cfi->addr_unlock2,
1539 chip->start, map, cfi,
1540 cfi->device_type, NULL);
1541 cfi_send_gen_cmd(0x40, cfi->addr_unlock1,
1542 chip->start, map, cfi,
1543 cfi->device_type, NULL);
1544 /* read lock register */
1545 lockreg = cfi_read_query(map, 0);
1546 /* exit protection commands */
1547 map_write(map, CMD(0x90), chip->start);
1548 map_write(map, CMD(0x00), chip->start);
1549 put_chip(map, chip, chip->start);
1550 mutex_unlock(&chip->mutex);
1552 user_locked = ((lockreg & 0x01) == 0x00);
1556 otpsize = user_regs ? user_size : factory_size;
1559 otpoffset = user_regs ? user_offset : factory_offset;
1560 otplocked = user_regs ? user_locked : 1;
1563 /* return otpinfo */
1564 struct otp_info *otpinfo;
1565 len -= sizeof(*otpinfo);
1568 otpinfo = (struct otp_info *)buf;
1569 otpinfo->start = from;
1570 otpinfo->length = otpsize;
1571 otpinfo->locked = otplocked;
1572 buf += sizeof(*otpinfo);
1573 *retlen += sizeof(*otpinfo);
1575 } else if ((from < otpsize) && (len > 0)) {
1577 size = (len < otpsize - from) ? len : otpsize - from;
1578 ret = action(map, chip, otpoffset + from, size, buf,
1594 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *mtd, size_t len,
1595 size_t *retlen, struct otp_info *buf)
1597 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1601 static int cfi_amdstd_get_user_prot_info(struct mtd_info *mtd, size_t len,
1602 size_t *retlen, struct otp_info *buf)
1604 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1608 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
1609 size_t len, size_t *retlen,
1612 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1613 buf, do_read_secsi_onechip, 0);
1616 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
1617 size_t len, size_t *retlen,
1620 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1621 buf, do_read_secsi_onechip, 1);
1624 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
1625 size_t len, size_t *retlen,
1628 return cfi_amdstd_otp_walk(mtd, from, len, retlen, buf,
1632 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
1636 return cfi_amdstd_otp_walk(mtd, from, len, &retlen, NULL,
1640 static int __xipram do_write_oneword_once(struct map_info *map,
1641 struct flchip *chip,
1642 unsigned long adr, map_word datum,
1643 int mode, struct cfi_private *cfi)
1645 unsigned long timeo = jiffies + HZ;
1647 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1648 * have a max write time of a few hundreds usec). However, we should
1649 * use the maximum timeout value given by the chip at probe time
1650 * instead. Unfortunately, struct flchip does have a field for
1651 * maximum timeout, only for typical which can be far too short
1652 * depending of the conditions. The ' + 1' is to avoid having a
1653 * timeout of 0 jiffies if HZ is smaller than 1000.
1655 unsigned long uWriteTimeout = (HZ / 1000) + 1;
1658 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1659 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1660 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1661 map_write(map, datum, adr);
1664 INVALIDATE_CACHE_UDELAY(map, chip,
1665 adr, map_bankwidth(map),
1666 chip->word_write_time);
1668 /* See comment above for timeout value. */
1669 timeo = jiffies + uWriteTimeout;
1671 if (chip->state != mode) {
1672 /* Someone's suspended the write. Sleep */
1673 DECLARE_WAITQUEUE(wait, current);
1675 set_current_state(TASK_UNINTERRUPTIBLE);
1676 add_wait_queue(&chip->wq, &wait);
1677 mutex_unlock(&chip->mutex);
1679 remove_wait_queue(&chip->wq, &wait);
1680 timeo = jiffies + (HZ / 2); /* FIXME */
1681 mutex_lock(&chip->mutex);
1686 * We check "time_after" and "!chip_good" before checking
1687 * "chip_good" to avoid the failure due to scheduling.
1689 if (time_after(jiffies, timeo) &&
1690 !chip_good(map, chip, adr, &datum)) {
1691 xip_enable(map, chip, adr);
1692 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1693 xip_disable(map, chip, adr);
1698 if (chip_good(map, chip, adr, &datum)) {
1699 if (cfi_check_err_status(map, chip, adr))
1704 /* Latency issues. Drop the lock, wait a while and retry */
1705 UDELAY(map, chip, adr, 1);
1711 static int __xipram do_write_oneword_start(struct map_info *map,
1712 struct flchip *chip,
1713 unsigned long adr, int mode)
1717 mutex_lock(&chip->mutex);
1719 ret = get_chip(map, chip, adr, mode);
1721 mutex_unlock(&chip->mutex);
1725 if (mode == FL_OTP_WRITE)
1726 otp_enter(map, chip, adr, map_bankwidth(map));
1731 static void __xipram do_write_oneword_done(struct map_info *map,
1732 struct flchip *chip,
1733 unsigned long adr, int mode)
1735 if (mode == FL_OTP_WRITE)
1736 otp_exit(map, chip, adr, map_bankwidth(map));
1738 chip->state = FL_READY;
1740 put_chip(map, chip, adr);
1742 mutex_unlock(&chip->mutex);
1745 static int __xipram do_write_oneword_retry(struct map_info *map,
1746 struct flchip *chip,
1747 unsigned long adr, map_word datum,
1750 struct cfi_private *cfi = map->fldrv_priv;
1756 * Check for a NOP for the case when the datum to write is already
1757 * present - it saves time and works around buggy chips that corrupt
1758 * data at other locations when 0xff is written to a location that
1759 * already contains 0xff.
1761 oldd = map_read(map, adr);
1762 if (map_word_equal(map, oldd, datum)) {
1763 pr_debug("MTD %s(): NOP\n", __func__);
1767 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1769 xip_disable(map, chip, adr);
1772 ret = do_write_oneword_once(map, chip, adr, datum, mode, cfi);
1774 /* reset on all failures. */
1775 map_write(map, CMD(0xF0), chip->start);
1776 /* FIXME - should have reset delay before continuing */
1778 if (++retry_cnt <= MAX_RETRIES) {
1783 xip_enable(map, chip, adr);
1788 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1789 unsigned long adr, map_word datum,
1796 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", __func__, adr,
1799 ret = do_write_oneword_start(map, chip, adr, mode);
1803 ret = do_write_oneword_retry(map, chip, adr, datum, mode);
1805 do_write_oneword_done(map, chip, adr, mode);
1811 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1812 size_t *retlen, const u_char *buf)
1814 struct map_info *map = mtd->priv;
1815 struct cfi_private *cfi = map->fldrv_priv;
1818 unsigned long ofs, chipstart;
1819 DECLARE_WAITQUEUE(wait, current);
1821 chipnum = to >> cfi->chipshift;
1822 ofs = to - (chipnum << cfi->chipshift);
1823 chipstart = cfi->chips[chipnum].start;
1825 /* If it's not bus-aligned, do the first byte write */
1826 if (ofs & (map_bankwidth(map)-1)) {
1827 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1828 int i = ofs - bus_ofs;
1833 mutex_lock(&cfi->chips[chipnum].mutex);
1835 if (cfi->chips[chipnum].state != FL_READY) {
1836 set_current_state(TASK_UNINTERRUPTIBLE);
1837 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1839 mutex_unlock(&cfi->chips[chipnum].mutex);
1842 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1846 /* Load 'tmp_buf' with old contents of flash */
1847 tmp_buf = map_read(map, bus_ofs+chipstart);
1849 mutex_unlock(&cfi->chips[chipnum].mutex);
1851 /* Number of bytes to copy from buffer */
1852 n = min_t(int, len, map_bankwidth(map)-i);
1854 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1856 ret = do_write_oneword(map, &cfi->chips[chipnum],
1857 bus_ofs, tmp_buf, FL_WRITING);
1866 if (ofs >> cfi->chipshift) {
1869 if (chipnum == cfi->numchips)
1874 /* We are now aligned, write as much as possible */
1875 while(len >= map_bankwidth(map)) {
1878 datum = map_word_load(map, buf);
1880 ret = do_write_oneword(map, &cfi->chips[chipnum],
1881 ofs, datum, FL_WRITING);
1885 ofs += map_bankwidth(map);
1886 buf += map_bankwidth(map);
1887 (*retlen) += map_bankwidth(map);
1888 len -= map_bankwidth(map);
1890 if (ofs >> cfi->chipshift) {
1893 if (chipnum == cfi->numchips)
1895 chipstart = cfi->chips[chipnum].start;
1899 /* Write the trailing bytes if any */
1900 if (len & (map_bankwidth(map)-1)) {
1904 mutex_lock(&cfi->chips[chipnum].mutex);
1906 if (cfi->chips[chipnum].state != FL_READY) {
1907 set_current_state(TASK_UNINTERRUPTIBLE);
1908 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1910 mutex_unlock(&cfi->chips[chipnum].mutex);
1913 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1917 tmp_buf = map_read(map, ofs + chipstart);
1919 mutex_unlock(&cfi->chips[chipnum].mutex);
1921 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1923 ret = do_write_oneword(map, &cfi->chips[chipnum],
1924 ofs, tmp_buf, FL_WRITING);
1934 #if !FORCE_WORD_WRITE
1935 static int __xipram do_write_buffer_wait(struct map_info *map,
1936 struct flchip *chip, unsigned long adr,
1939 unsigned long timeo;
1940 unsigned long u_write_timeout;
1944 * Timeout is calculated according to CFI data, if available.
1945 * See more comments in cfi_cmdset_0002().
1947 u_write_timeout = usecs_to_jiffies(chip->buffer_write_time_max);
1948 timeo = jiffies + u_write_timeout;
1951 if (chip->state != FL_WRITING) {
1952 /* Someone's suspended the write. Sleep */
1953 DECLARE_WAITQUEUE(wait, current);
1955 set_current_state(TASK_UNINTERRUPTIBLE);
1956 add_wait_queue(&chip->wq, &wait);
1957 mutex_unlock(&chip->mutex);
1959 remove_wait_queue(&chip->wq, &wait);
1960 timeo = jiffies + (HZ / 2); /* FIXME */
1961 mutex_lock(&chip->mutex);
1966 * We check "time_after" and "!chip_good" before checking
1967 * "chip_good" to avoid the failure due to scheduling.
1969 if (time_after(jiffies, timeo) &&
1970 !chip_good(map, chip, adr, &datum)) {
1971 pr_err("MTD %s(): software timeout, address:0x%.8lx.\n",
1977 if (chip_good(map, chip, adr, &datum)) {
1978 if (cfi_check_err_status(map, chip, adr))
1983 /* Latency issues. Drop the lock, wait a while and retry */
1984 UDELAY(map, chip, adr, 1);
1990 static void __xipram do_write_buffer_reset(struct map_info *map,
1991 struct flchip *chip,
1992 struct cfi_private *cfi)
1995 * Recovery from write-buffer programming failures requires
1996 * the write-to-buffer-reset sequence. Since the last part
1997 * of the sequence also works as a normal reset, we can run
1998 * the same commands regardless of why we are here.
2000 * http://www.spansion.com/Support/Application%20Notes/MirrorBit_Write_Buffer_Prog_Page_Buffer_Read_AN.pdf
2002 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2003 cfi->device_type, NULL);
2004 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2005 cfi->device_type, NULL);
2006 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi,
2007 cfi->device_type, NULL);
2009 /* FIXME - should have reset delay before continuing */
2013 * FIXME: interleaved mode not tested, and probably not supported!
2015 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
2016 unsigned long adr, const u_char *buf,
2019 struct cfi_private *cfi = map->fldrv_priv;
2021 unsigned long cmd_adr;
2028 mutex_lock(&chip->mutex);
2029 ret = get_chip(map, chip, adr, FL_WRITING);
2031 mutex_unlock(&chip->mutex);
2035 datum = map_word_load(map, buf);
2037 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
2038 __func__, adr, datum.x[0]);
2040 XIP_INVAL_CACHED_RANGE(map, adr, len);
2042 xip_disable(map, chip, cmd_adr);
2044 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2045 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2047 /* Write Buffer Load */
2048 map_write(map, CMD(0x25), cmd_adr);
2050 chip->state = FL_WRITING_TO_BUFFER;
2052 /* Write length of data to come */
2053 words = len / map_bankwidth(map);
2054 map_write(map, CMD(words - 1), cmd_adr);
2057 while(z < words * map_bankwidth(map)) {
2058 datum = map_word_load(map, buf);
2059 map_write(map, datum, adr + z);
2061 z += map_bankwidth(map);
2062 buf += map_bankwidth(map);
2064 z -= map_bankwidth(map);
2068 /* Write Buffer Program Confirm: GO GO GO */
2069 map_write(map, CMD(0x29), cmd_adr);
2070 chip->state = FL_WRITING;
2072 INVALIDATE_CACHE_UDELAY(map, chip,
2073 adr, map_bankwidth(map),
2074 chip->word_write_time);
2076 ret = do_write_buffer_wait(map, chip, adr, datum);
2078 do_write_buffer_reset(map, chip, cfi);
2080 xip_enable(map, chip, adr);
2082 chip->state = FL_READY;
2084 put_chip(map, chip, adr);
2085 mutex_unlock(&chip->mutex);
2091 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
2092 size_t *retlen, const u_char *buf)
2094 struct map_info *map = mtd->priv;
2095 struct cfi_private *cfi = map->fldrv_priv;
2096 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
2101 chipnum = to >> cfi->chipshift;
2102 ofs = to - (chipnum << cfi->chipshift);
2104 /* If it's not bus-aligned, do the first word write */
2105 if (ofs & (map_bankwidth(map)-1)) {
2106 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
2107 if (local_len > len)
2109 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
2110 local_len, retlen, buf);
2117 if (ofs >> cfi->chipshift) {
2120 if (chipnum == cfi->numchips)
2125 /* Write buffer is worth it only if more than one word to write... */
2126 while (len >= map_bankwidth(map) * 2) {
2127 /* We must not cross write block boundaries */
2128 int size = wbufsize - (ofs & (wbufsize-1));
2132 if (size % map_bankwidth(map))
2133 size -= size % map_bankwidth(map);
2135 ret = do_write_buffer(map, &cfi->chips[chipnum],
2145 if (ofs >> cfi->chipshift) {
2148 if (chipnum == cfi->numchips)
2154 size_t retlen_dregs = 0;
2156 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
2157 len, &retlen_dregs, buf);
2159 *retlen += retlen_dregs;
2165 #endif /* !FORCE_WORD_WRITE */
2168 * Wait for the flash chip to become ready to write data
2170 * This is only called during the panic_write() path. When panic_write()
2171 * is called, the kernel is in the process of a panic, and will soon be
2172 * dead. Therefore we don't take any locks, and attempt to get access
2173 * to the chip as soon as possible.
2175 static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip,
2178 struct cfi_private *cfi = map->fldrv_priv;
2183 * If the driver thinks the chip is idle, and no toggle bits
2184 * are changing, then the chip is actually idle for sure.
2186 if (chip->state == FL_READY && chip_ready(map, chip, adr, NULL))
2190 * Try several times to reset the chip and then wait for it
2191 * to become idle. The upper limit of a few milliseconds of
2192 * delay isn't a big problem: the kernel is dying anyway. It
2193 * is more important to save the messages.
2195 while (retries > 0) {
2196 const unsigned long timeo = (HZ / 1000) + 1;
2198 /* send the reset command */
2199 map_write(map, CMD(0xF0), chip->start);
2201 /* wait for the chip to become ready */
2202 for (i = 0; i < jiffies_to_usecs(timeo); i++) {
2203 if (chip_ready(map, chip, adr, NULL))
2212 /* the chip never became ready */
2217 * Write out one word of data to a single flash chip during a kernel panic
2219 * This is only called during the panic_write() path. When panic_write()
2220 * is called, the kernel is in the process of a panic, and will soon be
2221 * dead. Therefore we don't take any locks, and attempt to get access
2222 * to the chip as soon as possible.
2224 * The implementation of this routine is intentionally similar to
2225 * do_write_oneword(), in order to ease code maintenance.
2227 static int do_panic_write_oneword(struct map_info *map, struct flchip *chip,
2228 unsigned long adr, map_word datum)
2230 const unsigned long uWriteTimeout = (HZ / 1000) + 1;
2231 struct cfi_private *cfi = map->fldrv_priv;
2239 ret = cfi_amdstd_panic_wait(map, chip, adr);
2243 pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n",
2244 __func__, adr, datum.x[0]);
2247 * Check for a NOP for the case when the datum to write is already
2248 * present - it saves time and works around buggy chips that corrupt
2249 * data at other locations when 0xff is written to a location that
2250 * already contains 0xff.
2252 oldd = map_read(map, adr);
2253 if (map_word_equal(map, oldd, datum)) {
2254 pr_debug("MTD %s(): NOP\n", __func__);
2261 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2262 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2263 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2264 map_write(map, datum, adr);
2266 for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) {
2267 if (chip_ready(map, chip, adr, NULL))
2273 if (!chip_ready(map, chip, adr, &datum) ||
2274 cfi_check_err_status(map, chip, adr)) {
2275 /* reset on all failures. */
2276 map_write(map, CMD(0xF0), chip->start);
2277 /* FIXME - should have reset delay before continuing */
2279 if (++retry_cnt <= MAX_RETRIES)
2291 * Write out some data during a kernel panic
2293 * This is used by the mtdoops driver to save the dying messages from a
2294 * kernel which has panic'd.
2296 * This routine ignores all of the locking used throughout the rest of the
2297 * driver, in order to ensure that the data gets written out no matter what
2298 * state this driver (and the flash chip itself) was in when the kernel crashed.
2300 * The implementation of this routine is intentionally similar to
2301 * cfi_amdstd_write_words(), in order to ease code maintenance.
2303 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
2304 size_t *retlen, const u_char *buf)
2306 struct map_info *map = mtd->priv;
2307 struct cfi_private *cfi = map->fldrv_priv;
2308 unsigned long ofs, chipstart;
2312 chipnum = to >> cfi->chipshift;
2313 ofs = to - (chipnum << cfi->chipshift);
2314 chipstart = cfi->chips[chipnum].start;
2316 /* If it's not bus aligned, do the first byte write */
2317 if (ofs & (map_bankwidth(map) - 1)) {
2318 unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1);
2319 int i = ofs - bus_ofs;
2323 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs);
2327 /* Load 'tmp_buf' with old contents of flash */
2328 tmp_buf = map_read(map, bus_ofs + chipstart);
2330 /* Number of bytes to copy from buffer */
2331 n = min_t(int, len, map_bankwidth(map) - i);
2333 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
2335 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2345 if (ofs >> cfi->chipshift) {
2348 if (chipnum == cfi->numchips)
2353 /* We are now aligned, write as much as possible */
2354 while (len >= map_bankwidth(map)) {
2357 datum = map_word_load(map, buf);
2359 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2364 ofs += map_bankwidth(map);
2365 buf += map_bankwidth(map);
2366 (*retlen) += map_bankwidth(map);
2367 len -= map_bankwidth(map);
2369 if (ofs >> cfi->chipshift) {
2372 if (chipnum == cfi->numchips)
2375 chipstart = cfi->chips[chipnum].start;
2379 /* Write the trailing bytes if any */
2380 if (len & (map_bankwidth(map) - 1)) {
2383 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs);
2387 tmp_buf = map_read(map, ofs + chipstart);
2389 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
2391 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2404 * Handle devices with one erase region, that only implement
2405 * the chip erase command.
2407 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
2409 struct cfi_private *cfi = map->fldrv_priv;
2410 unsigned long timeo = jiffies + HZ;
2411 unsigned long int adr;
2412 DECLARE_WAITQUEUE(wait, current);
2415 map_word datum = map_word_ff(map);
2417 adr = cfi->addr_unlock1;
2419 mutex_lock(&chip->mutex);
2420 ret = get_chip(map, chip, adr, FL_ERASING);
2422 mutex_unlock(&chip->mutex);
2426 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2427 __func__, chip->start);
2429 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
2431 xip_disable(map, chip, adr);
2434 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2435 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2436 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2437 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2438 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2439 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2441 chip->state = FL_ERASING;
2442 chip->erase_suspended = 0;
2443 chip->in_progress_block_addr = adr;
2444 chip->in_progress_block_mask = ~(map->size - 1);
2446 INVALIDATE_CACHE_UDELAY(map, chip,
2448 chip->erase_time*500);
2450 timeo = jiffies + (HZ*20);
2453 if (chip->state != FL_ERASING) {
2454 /* Someone's suspended the erase. Sleep */
2455 set_current_state(TASK_UNINTERRUPTIBLE);
2456 add_wait_queue(&chip->wq, &wait);
2457 mutex_unlock(&chip->mutex);
2459 remove_wait_queue(&chip->wq, &wait);
2460 mutex_lock(&chip->mutex);
2463 if (chip->erase_suspended) {
2464 /* This erase was suspended and resumed.
2465 Adjust the timeout */
2466 timeo = jiffies + (HZ*20); /* FIXME */
2467 chip->erase_suspended = 0;
2470 if (chip_ready(map, chip, adr, &datum)) {
2471 if (cfi_check_err_status(map, chip, adr))
2476 if (time_after(jiffies, timeo)) {
2477 printk(KERN_WARNING "MTD %s(): software timeout\n",
2483 /* Latency issues. Drop the lock, wait a while and retry */
2484 UDELAY(map, chip, adr, 1000000/HZ);
2486 /* Did we succeed? */
2488 /* reset on all failures. */
2489 map_write(map, CMD(0xF0), chip->start);
2490 /* FIXME - should have reset delay before continuing */
2492 if (++retry_cnt <= MAX_RETRIES) {
2498 chip->state = FL_READY;
2499 xip_enable(map, chip, adr);
2501 put_chip(map, chip, adr);
2502 mutex_unlock(&chip->mutex);
2508 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
2510 struct cfi_private *cfi = map->fldrv_priv;
2511 unsigned long timeo = jiffies + HZ;
2512 DECLARE_WAITQUEUE(wait, current);
2515 map_word datum = map_word_ff(map);
2519 mutex_lock(&chip->mutex);
2520 ret = get_chip(map, chip, adr, FL_ERASING);
2522 mutex_unlock(&chip->mutex);
2526 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2529 XIP_INVAL_CACHED_RANGE(map, adr, len);
2531 xip_disable(map, chip, adr);
2534 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2535 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2536 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2537 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2538 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2539 map_write(map, cfi->sector_erase_cmd, adr);
2541 chip->state = FL_ERASING;
2542 chip->erase_suspended = 0;
2543 chip->in_progress_block_addr = adr;
2544 chip->in_progress_block_mask = ~(len - 1);
2546 INVALIDATE_CACHE_UDELAY(map, chip,
2548 chip->erase_time*500);
2550 timeo = jiffies + (HZ*20);
2553 if (chip->state != FL_ERASING) {
2554 /* Someone's suspended the erase. Sleep */
2555 set_current_state(TASK_UNINTERRUPTIBLE);
2556 add_wait_queue(&chip->wq, &wait);
2557 mutex_unlock(&chip->mutex);
2559 remove_wait_queue(&chip->wq, &wait);
2560 mutex_lock(&chip->mutex);
2563 if (chip->erase_suspended) {
2564 /* This erase was suspended and resumed.
2565 Adjust the timeout */
2566 timeo = jiffies + (HZ*20); /* FIXME */
2567 chip->erase_suspended = 0;
2570 if (chip_ready(map, chip, adr, &datum)) {
2571 if (cfi_check_err_status(map, chip, adr))
2576 if (time_after(jiffies, timeo)) {
2577 printk(KERN_WARNING "MTD %s(): software timeout\n",
2583 /* Latency issues. Drop the lock, wait a while and retry */
2584 UDELAY(map, chip, adr, 1000000/HZ);
2586 /* Did we succeed? */
2588 /* reset on all failures. */
2589 map_write(map, CMD(0xF0), chip->start);
2590 /* FIXME - should have reset delay before continuing */
2592 if (++retry_cnt <= MAX_RETRIES) {
2598 chip->state = FL_READY;
2599 xip_enable(map, chip, adr);
2601 put_chip(map, chip, adr);
2602 mutex_unlock(&chip->mutex);
2607 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
2609 return cfi_varsize_frob(mtd, do_erase_oneblock, instr->addr,
2614 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
2616 struct map_info *map = mtd->priv;
2617 struct cfi_private *cfi = map->fldrv_priv;
2619 if (instr->addr != 0)
2622 if (instr->len != mtd->size)
2625 return do_erase_chip(map, &cfi->chips[0]);
2628 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
2629 unsigned long adr, int len, void *thunk)
2631 struct cfi_private *cfi = map->fldrv_priv;
2634 mutex_lock(&chip->mutex);
2635 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
2638 chip->state = FL_LOCKING;
2640 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2642 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2643 cfi->device_type, NULL);
2644 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2645 cfi->device_type, NULL);
2646 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
2647 cfi->device_type, NULL);
2648 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2649 cfi->device_type, NULL);
2650 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2651 cfi->device_type, NULL);
2652 map_write(map, CMD(0x40), chip->start + adr);
2654 chip->state = FL_READY;
2655 put_chip(map, chip, adr + chip->start);
2659 mutex_unlock(&chip->mutex);
2663 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
2664 unsigned long adr, int len, void *thunk)
2666 struct cfi_private *cfi = map->fldrv_priv;
2669 mutex_lock(&chip->mutex);
2670 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
2673 chip->state = FL_UNLOCKING;
2675 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2677 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2678 cfi->device_type, NULL);
2679 map_write(map, CMD(0x70), adr);
2681 chip->state = FL_READY;
2682 put_chip(map, chip, adr + chip->start);
2686 mutex_unlock(&chip->mutex);
2690 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2692 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
2695 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2697 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
2701 * Advanced Sector Protection - PPB (Persistent Protection Bit) locking
2705 struct flchip *chip;
2710 #define DO_XXLOCK_ONEBLOCK_LOCK ((void *)1)
2711 #define DO_XXLOCK_ONEBLOCK_UNLOCK ((void *)2)
2712 #define DO_XXLOCK_ONEBLOCK_GETLOCK ((void *)3)
2714 static int __maybe_unused do_ppb_xxlock(struct map_info *map,
2715 struct flchip *chip,
2716 unsigned long adr, int len, void *thunk)
2718 struct cfi_private *cfi = map->fldrv_priv;
2719 unsigned long timeo;
2723 mutex_lock(&chip->mutex);
2724 ret = get_chip(map, chip, adr, FL_LOCKING);
2726 mutex_unlock(&chip->mutex);
2730 pr_debug("MTD %s(): XXLOCK 0x%08lx len %d\n", __func__, adr, len);
2732 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2733 cfi->device_type, NULL);
2734 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2735 cfi->device_type, NULL);
2736 /* PPB entry command */
2737 cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi,
2738 cfi->device_type, NULL);
2740 if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) {
2741 chip->state = FL_LOCKING;
2742 map_write(map, CMD(0xA0), adr);
2743 map_write(map, CMD(0x00), adr);
2744 } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) {
2746 * Unlocking of one specific sector is not supported, so we
2747 * have to unlock all sectors of this device instead
2749 chip->state = FL_UNLOCKING;
2750 map_write(map, CMD(0x80), chip->start);
2751 map_write(map, CMD(0x30), chip->start);
2752 } else if (thunk == DO_XXLOCK_ONEBLOCK_GETLOCK) {
2753 chip->state = FL_JEDEC_QUERY;
2754 /* Return locked status: 0->locked, 1->unlocked */
2755 ret = !cfi_read_query(map, adr);
2760 * Wait for some time as unlocking of all sectors takes quite long
2762 timeo = jiffies + msecs_to_jiffies(2000); /* 2s max (un)locking */
2764 if (chip_ready(map, chip, adr, NULL))
2767 if (time_after(jiffies, timeo)) {
2768 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
2773 UDELAY(map, chip, adr, 1);
2776 /* Exit BC commands */
2777 map_write(map, CMD(0x90), chip->start);
2778 map_write(map, CMD(0x00), chip->start);
2780 chip->state = FL_READY;
2781 put_chip(map, chip, adr);
2782 mutex_unlock(&chip->mutex);
2787 static int __maybe_unused cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs,
2790 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2791 DO_XXLOCK_ONEBLOCK_LOCK);
2794 static int __maybe_unused cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs,
2797 struct mtd_erase_region_info *regions = mtd->eraseregions;
2798 struct map_info *map = mtd->priv;
2799 struct cfi_private *cfi = map->fldrv_priv;
2800 struct ppb_lock *sect;
2811 * PPB unlocking always unlocks all sectors of the flash chip.
2812 * We need to re-lock all previously locked sectors. So lets
2813 * first check the locking status of all sectors and save
2814 * it for future use.
2817 for (i = 0; i < mtd->numeraseregions; i++)
2818 max_sectors += regions[i].numblocks;
2820 sect = kcalloc(max_sectors, sizeof(struct ppb_lock), GFP_KERNEL);
2825 * This code to walk all sectors is a slightly modified version
2826 * of the cfi_varsize_frob() code.
2836 int size = regions[i].erasesize;
2839 * Only test sectors that shall not be unlocked. The other
2840 * sectors shall be unlocked, so lets keep their locking
2841 * status at "unlocked" (locked=0) for the final re-locking.
2843 if ((offset < ofs) || (offset >= (ofs + len))) {
2844 sect[sectors].chip = &cfi->chips[chipnum];
2845 sect[sectors].adr = adr;
2846 sect[sectors].locked = do_ppb_xxlock(
2847 map, &cfi->chips[chipnum], adr, 0,
2848 DO_XXLOCK_ONEBLOCK_GETLOCK);
2855 if (offset == regions[i].offset + size * regions[i].numblocks)
2858 if (adr >> cfi->chipshift) {
2859 if (offset >= (ofs + len))
2864 if (chipnum >= cfi->numchips)
2869 if (sectors >= max_sectors) {
2870 printk(KERN_ERR "Only %d sectors for PPB locking supported!\n",
2877 /* Now unlock the whole chip */
2878 ret = cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2879 DO_XXLOCK_ONEBLOCK_UNLOCK);
2886 * PPB unlocking always unlocks all sectors of the flash chip.
2887 * We need to re-lock all previously locked sectors.
2889 for (i = 0; i < sectors; i++) {
2891 do_ppb_xxlock(map, sect[i].chip, sect[i].adr, 0,
2892 DO_XXLOCK_ONEBLOCK_LOCK);
2899 static int __maybe_unused cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs,
2902 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2903 DO_XXLOCK_ONEBLOCK_GETLOCK) ? 1 : 0;
2906 static void cfi_amdstd_sync (struct mtd_info *mtd)
2908 struct map_info *map = mtd->priv;
2909 struct cfi_private *cfi = map->fldrv_priv;
2911 struct flchip *chip;
2913 DECLARE_WAITQUEUE(wait, current);
2915 for (i=0; !ret && i<cfi->numchips; i++) {
2916 chip = &cfi->chips[i];
2919 mutex_lock(&chip->mutex);
2921 switch(chip->state) {
2925 case FL_JEDEC_QUERY:
2926 chip->oldstate = chip->state;
2927 chip->state = FL_SYNCING;
2928 /* No need to wake_up() on this state change -
2929 * as the whole point is that nobody can do anything
2930 * with the chip now anyway.
2934 mutex_unlock(&chip->mutex);
2938 /* Not an idle state */
2939 set_current_state(TASK_UNINTERRUPTIBLE);
2940 add_wait_queue(&chip->wq, &wait);
2942 mutex_unlock(&chip->mutex);
2946 remove_wait_queue(&chip->wq, &wait);
2952 /* Unlock the chips again */
2954 for (i--; i >=0; i--) {
2955 chip = &cfi->chips[i];
2957 mutex_lock(&chip->mutex);
2959 if (chip->state == FL_SYNCING) {
2960 chip->state = chip->oldstate;
2963 mutex_unlock(&chip->mutex);
2968 static int cfi_amdstd_suspend(struct mtd_info *mtd)
2970 struct map_info *map = mtd->priv;
2971 struct cfi_private *cfi = map->fldrv_priv;
2973 struct flchip *chip;
2976 for (i=0; !ret && i<cfi->numchips; i++) {
2977 chip = &cfi->chips[i];
2979 mutex_lock(&chip->mutex);
2981 switch(chip->state) {
2985 case FL_JEDEC_QUERY:
2986 chip->oldstate = chip->state;
2987 chip->state = FL_PM_SUSPENDED;
2988 /* No need to wake_up() on this state change -
2989 * as the whole point is that nobody can do anything
2990 * with the chip now anyway.
2992 case FL_PM_SUSPENDED:
2999 mutex_unlock(&chip->mutex);
3002 /* Unlock the chips again */
3005 for (i--; i >=0; i--) {
3006 chip = &cfi->chips[i];
3008 mutex_lock(&chip->mutex);
3010 if (chip->state == FL_PM_SUSPENDED) {
3011 chip->state = chip->oldstate;
3014 mutex_unlock(&chip->mutex);
3022 static void cfi_amdstd_resume(struct mtd_info *mtd)
3024 struct map_info *map = mtd->priv;
3025 struct cfi_private *cfi = map->fldrv_priv;
3027 struct flchip *chip;
3029 for (i=0; i<cfi->numchips; i++) {
3031 chip = &cfi->chips[i];
3033 mutex_lock(&chip->mutex);
3035 if (chip->state == FL_PM_SUSPENDED) {
3036 chip->state = FL_READY;
3037 map_write(map, CMD(0xF0), chip->start);
3041 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
3043 mutex_unlock(&chip->mutex);
3049 * Ensure that the flash device is put back into read array mode before
3050 * unloading the driver or rebooting. On some systems, rebooting while
3051 * the flash is in query/program/erase mode will prevent the CPU from
3052 * fetching the bootloader code, requiring a hard reset or power cycle.
3054 static int cfi_amdstd_reset(struct mtd_info *mtd)
3056 struct map_info *map = mtd->priv;
3057 struct cfi_private *cfi = map->fldrv_priv;
3059 struct flchip *chip;
3061 for (i = 0; i < cfi->numchips; i++) {
3063 chip = &cfi->chips[i];
3065 mutex_lock(&chip->mutex);
3067 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
3069 map_write(map, CMD(0xF0), chip->start);
3070 chip->state = FL_SHUTDOWN;
3071 put_chip(map, chip, chip->start);
3074 mutex_unlock(&chip->mutex);
3081 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
3084 struct mtd_info *mtd;
3086 mtd = container_of(nb, struct mtd_info, reboot_notifier);
3087 cfi_amdstd_reset(mtd);
3092 static void cfi_amdstd_destroy(struct mtd_info *mtd)
3094 struct map_info *map = mtd->priv;
3095 struct cfi_private *cfi = map->fldrv_priv;
3097 cfi_amdstd_reset(mtd);
3098 unregister_reboot_notifier(&mtd->reboot_notifier);
3099 kfree(cfi->cmdset_priv);
3102 kfree(mtd->eraseregions);
3105 MODULE_LICENSE("GPL");
3106 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
3107 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
3108 MODULE_ALIAS("cfi_cmdset_0006");
3109 MODULE_ALIAS("cfi_cmdset_0701");