2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
28 #include <asm/byteorder.h>
30 #include <linux/errno.h>
31 #include <linux/slab.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/reboot.h>
36 #include <linux/of_platform.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
47 #define SST49LF004B 0x0060
48 #define SST49LF040B 0x0050
49 #define SST49LF008A 0x005a
50 #define AT49BV6416 0x00d6
53 CFI_QUIRK_DQ_TRUE_DATA = BIT(0),
56 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
57 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
58 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
59 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
60 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
61 static void cfi_amdstd_sync (struct mtd_info *);
62 static int cfi_amdstd_suspend (struct mtd_info *);
63 static void cfi_amdstd_resume (struct mtd_info *);
64 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
65 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *, size_t,
66 size_t *, struct otp_info *);
67 static int cfi_amdstd_get_user_prot_info(struct mtd_info *, size_t,
68 size_t *, struct otp_info *);
69 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
70 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *, loff_t, size_t,
72 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *, loff_t, size_t,
74 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *, loff_t, size_t,
76 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *, loff_t, size_t);
78 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
79 size_t *retlen, const u_char *buf);
81 static void cfi_amdstd_destroy(struct mtd_info *);
83 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
84 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
86 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
87 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
90 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
91 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
93 static int cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
94 static int cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
95 static int cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
97 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
98 .probe = NULL, /* Not usable directly */
99 .destroy = cfi_amdstd_destroy,
100 .name = "cfi_cmdset_0002",
101 .module = THIS_MODULE
105 /* #define DEBUG_CFI_FEATURES */
108 #ifdef DEBUG_CFI_FEATURES
109 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
111 const char* erase_suspend[3] = {
112 "Not supported", "Read only", "Read/write"
114 const char* top_bottom[6] = {
115 "No WP", "8x8KiB sectors at top & bottom, no WP",
116 "Bottom boot", "Top boot",
117 "Uniform, Bottom WP", "Uniform, Top WP"
120 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
121 printk(" Address sensitive unlock: %s\n",
122 (extp->SiliconRevision & 1) ? "Not required" : "Required");
124 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
125 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
127 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
129 if (extp->BlkProt == 0)
130 printk(" Block protection: Not supported\n");
132 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
135 printk(" Temporary block unprotect: %s\n",
136 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
137 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
138 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
139 printk(" Burst mode: %s\n",
140 extp->BurstMode ? "Supported" : "Not supported");
141 if (extp->PageMode == 0)
142 printk(" Page mode: Not supported\n");
144 printk(" Page mode: %d word page\n", extp->PageMode << 2);
146 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
147 extp->VppMin >> 4, extp->VppMin & 0xf);
148 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
149 extp->VppMax >> 4, extp->VppMax & 0xf);
151 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
152 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
154 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
158 #ifdef AMD_BOOTLOC_BUG
159 /* Wheee. Bring me the head of someone at AMD. */
160 static void fixup_amd_bootblock(struct mtd_info *mtd)
162 struct map_info *map = mtd->priv;
163 struct cfi_private *cfi = map->fldrv_priv;
164 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
165 __u8 major = extp->MajorVersion;
166 __u8 minor = extp->MinorVersion;
168 if (((major << 8) | minor) < 0x3131) {
169 /* CFI version 1.0 => don't trust bootloc */
171 pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
172 map->name, cfi->mfr, cfi->id);
174 /* AFAICS all 29LV400 with a bottom boot block have a device ID
175 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
176 * These were badly detected as they have the 0x80 bit set
177 * so treat them as a special case.
179 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
181 /* Macronix added CFI to their 2nd generation
182 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
183 * Fujitsu, Spansion, EON, ESI and older Macronix)
186 * Therefore also check the manufacturer.
187 * This reduces the risk of false detection due to
188 * the 8-bit device ID.
190 (cfi->mfr == CFI_MFR_MACRONIX)) {
191 pr_debug("%s: Macronix MX29LV400C with bottom boot block"
192 " detected\n", map->name);
193 extp->TopBottom = 2; /* bottom boot */
195 if (cfi->id & 0x80) {
196 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
197 extp->TopBottom = 3; /* top boot */
199 extp->TopBottom = 2; /* bottom boot */
202 pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;"
203 " deduced %s from Device ID\n", map->name, major, minor,
204 extp->TopBottom == 2 ? "bottom" : "top");
209 static void fixup_use_write_buffers(struct mtd_info *mtd)
211 struct map_info *map = mtd->priv;
212 struct cfi_private *cfi = map->fldrv_priv;
213 if (cfi->cfiq->BufWriteTimeoutTyp) {
214 pr_debug("Using buffer write method\n" );
215 mtd->_write = cfi_amdstd_write_buffers;
219 /* Atmel chips don't use the same PRI format as AMD chips */
220 static void fixup_convert_atmel_pri(struct mtd_info *mtd)
222 struct map_info *map = mtd->priv;
223 struct cfi_private *cfi = map->fldrv_priv;
224 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
225 struct cfi_pri_atmel atmel_pri;
227 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
228 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
230 if (atmel_pri.Features & 0x02)
231 extp->EraseSuspend = 2;
233 /* Some chips got it backwards... */
234 if (cfi->id == AT49BV6416) {
235 if (atmel_pri.BottomBoot)
240 if (atmel_pri.BottomBoot)
246 /* burst write mode not supported */
247 cfi->cfiq->BufWriteTimeoutTyp = 0;
248 cfi->cfiq->BufWriteTimeoutMax = 0;
251 static void fixup_use_secsi(struct mtd_info *mtd)
253 /* Setup for chips with a secsi area */
254 mtd->_read_user_prot_reg = cfi_amdstd_secsi_read;
255 mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read;
258 static void fixup_use_erase_chip(struct mtd_info *mtd)
260 struct map_info *map = mtd->priv;
261 struct cfi_private *cfi = map->fldrv_priv;
262 if ((cfi->cfiq->NumEraseRegions == 1) &&
263 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
264 mtd->_erase = cfi_amdstd_erase_chip;
270 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
273 static void fixup_use_atmel_lock(struct mtd_info *mtd)
275 mtd->_lock = cfi_atmel_lock;
276 mtd->_unlock = cfi_atmel_unlock;
277 mtd->flags |= MTD_POWERUP_LOCK;
280 static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
282 struct map_info *map = mtd->priv;
283 struct cfi_private *cfi = map->fldrv_priv;
286 * These flashes report two separate eraseblock regions based on the
287 * sector_erase-size and block_erase-size, although they both operate on the
288 * same memory. This is not allowed according to CFI, so we just pick the
291 cfi->cfiq->NumEraseRegions = 1;
294 static void fixup_sst39vf(struct mtd_info *mtd)
296 struct map_info *map = mtd->priv;
297 struct cfi_private *cfi = map->fldrv_priv;
299 fixup_old_sst_eraseregion(mtd);
301 cfi->addr_unlock1 = 0x5555;
302 cfi->addr_unlock2 = 0x2AAA;
305 static void fixup_sst39vf_rev_b(struct mtd_info *mtd)
307 struct map_info *map = mtd->priv;
308 struct cfi_private *cfi = map->fldrv_priv;
310 fixup_old_sst_eraseregion(mtd);
312 cfi->addr_unlock1 = 0x555;
313 cfi->addr_unlock2 = 0x2AA;
315 cfi->sector_erase_cmd = CMD(0x50);
318 static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd)
320 struct map_info *map = mtd->priv;
321 struct cfi_private *cfi = map->fldrv_priv;
323 fixup_sst39vf_rev_b(mtd);
326 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where
327 * it should report a size of 8KBytes (0x0020*256).
329 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff;
330 pr_warning("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n", mtd->name);
333 static void fixup_s29gl064n_sectors(struct mtd_info *mtd)
335 struct map_info *map = mtd->priv;
336 struct cfi_private *cfi = map->fldrv_priv;
338 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
339 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
340 pr_warning("%s: Bad S29GL064N CFI data; adjust from 64 to 128 sectors\n", mtd->name);
344 static void fixup_s29gl032n_sectors(struct mtd_info *mtd)
346 struct map_info *map = mtd->priv;
347 struct cfi_private *cfi = map->fldrv_priv;
349 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
350 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
351 pr_warning("%s: Bad S29GL032N CFI data; adjust from 127 to 63 sectors\n", mtd->name);
355 static void fixup_s29ns512p_sectors(struct mtd_info *mtd)
357 struct map_info *map = mtd->priv;
358 struct cfi_private *cfi = map->fldrv_priv;
361 * S29NS512P flash uses more than 8bits to report number of sectors,
362 * which is not permitted by CFI.
364 cfi->cfiq->EraseRegionInfo[0] = 0x020001ff;
365 pr_warning("%s: Bad S29NS512P CFI data; adjust to 512 sectors\n", mtd->name);
368 static void fixup_quirks(struct mtd_info *mtd)
370 struct map_info *map = mtd->priv;
371 struct cfi_private *cfi = map->fldrv_priv;
373 if (cfi->mfr == CFI_MFR_AMD && cfi->id == 0x0c01)
374 cfi->quirks |= CFI_QUIRK_DQ_TRUE_DATA;
377 /* Used to fix CFI-Tables of chips without Extended Query Tables */
378 static struct cfi_fixup cfi_nopri_fixup_table[] = {
379 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */
380 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */
381 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */
382 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */
383 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */
384 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */
385 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */
386 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */
390 static struct cfi_fixup cfi_fixup_table[] = {
391 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri },
392 #ifdef AMD_BOOTLOC_BUG
393 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock },
394 { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock },
395 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock },
397 { CFI_MFR_AMD, 0x0050, fixup_use_secsi },
398 { CFI_MFR_AMD, 0x0053, fixup_use_secsi },
399 { CFI_MFR_AMD, 0x0055, fixup_use_secsi },
400 { CFI_MFR_AMD, 0x0056, fixup_use_secsi },
401 { CFI_MFR_AMD, 0x005C, fixup_use_secsi },
402 { CFI_MFR_AMD, 0x005F, fixup_use_secsi },
403 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors },
404 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors },
405 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors },
406 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors },
407 { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors },
408 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */
409 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */
410 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */
411 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */
412 #if !FORCE_WORD_WRITE
413 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers },
415 { CFI_MFR_ANY, CFI_ID_ANY, fixup_quirks },
418 static struct cfi_fixup jedec_fixup_table[] = {
419 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock },
420 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock },
421 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock },
425 static struct cfi_fixup fixup_table[] = {
426 /* The CFI vendor ids and the JEDEC vendor IDs appear
427 * to be common. It is like the devices id's are as
428 * well. This table is to pick all cases where
429 * we know that is the case.
431 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip },
432 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock },
437 static void cfi_fixup_major_minor(struct cfi_private *cfi,
438 struct cfi_pri_amdstd *extp)
440 if (cfi->mfr == CFI_MFR_SAMSUNG) {
441 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') ||
442 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) {
444 * Samsung K8P2815UQB and K8D6x16UxM chips
445 * report major=0 / minor=0.
446 * K8D3x16UxC chips report major=3 / minor=3.
448 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu"
449 " Extended Query version to 1.%c\n",
451 extp->MajorVersion = '1';
456 * SST 38VF640x chips report major=0xFF / minor=0xFF.
458 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) {
459 extp->MajorVersion = '1';
460 extp->MinorVersion = '0';
464 static int is_m29ew(struct cfi_private *cfi)
466 if (cfi->mfr == CFI_MFR_INTEL &&
467 ((cfi->device_type == CFI_DEVICETYPE_X8 && (cfi->id & 0xff) == 0x7e) ||
468 (cfi->device_type == CFI_DEVICETYPE_X16 && cfi->id == 0x227e)))
474 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 20:
475 * Some revisions of the M29EW suffer from erase suspend hang ups. In
476 * particular, it can occur when the sequence
477 * Erase Confirm -> Suspend -> Program -> Resume
478 * causes a lockup due to internal timing issues. The consequence is that the
479 * erase cannot be resumed without inserting a dummy command after programming
480 * and prior to resuming. [...] The work-around is to issue a dummy write cycle
481 * that writes an F0 command code before the RESUME command.
483 static void cfi_fixup_m29ew_erase_suspend(struct map_info *map,
486 struct cfi_private *cfi = map->fldrv_priv;
487 /* before resume, insert a dummy 0xF0 cycle for Micron M29EW devices */
489 map_write(map, CMD(0xF0), adr);
493 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 22:
495 * Some revisions of the M29EW (for example, A1 and A2 step revisions)
496 * are affected by a problem that could cause a hang up when an ERASE SUSPEND
497 * command is issued after an ERASE RESUME operation without waiting for a
498 * minimum delay. The result is that once the ERASE seems to be completed
499 * (no bits are toggling), the contents of the Flash memory block on which
500 * the erase was ongoing could be inconsistent with the expected values
501 * (typically, the array value is stuck to the 0xC0, 0xC4, 0x80, or 0x84
502 * values), causing a consequent failure of the ERASE operation.
503 * The occurrence of this issue could be high, especially when file system
504 * operations on the Flash are intensive. As a result, it is recommended
505 * that a patch be applied. Intensive file system operations can cause many
506 * calls to the garbage routine to free Flash space (also by erasing physical
507 * Flash blocks) and as a result, many consecutive SUSPEND and RESUME
508 * commands can occur. The problem disappears when a delay is inserted after
509 * the RESUME command by using the udelay() function available in Linux.
510 * The DELAY value must be tuned based on the customer's platform.
511 * The maximum value that fixes the problem in all cases is 500us.
512 * But, in our experience, a delay of 30 µs to 50 µs is sufficient
514 * We have chosen 500µs because this latency is acceptable.
516 static void cfi_fixup_m29ew_delay_after_resume(struct cfi_private *cfi)
519 * Resolving the Delay After Resume Issue see Micron TN-13-07
520 * Worst case delay must be 500µs but 30-50µs should be ok as well
526 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
528 struct cfi_private *cfi = map->fldrv_priv;
529 struct device_node __maybe_unused *np = map->device_node;
530 struct mtd_info *mtd;
533 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
537 mtd->type = MTD_NORFLASH;
539 /* Fill in the default mtd operations */
540 mtd->_erase = cfi_amdstd_erase_varsize;
541 mtd->_write = cfi_amdstd_write_words;
542 mtd->_read = cfi_amdstd_read;
543 mtd->_sync = cfi_amdstd_sync;
544 mtd->_suspend = cfi_amdstd_suspend;
545 mtd->_resume = cfi_amdstd_resume;
546 mtd->_read_user_prot_reg = cfi_amdstd_read_user_prot_reg;
547 mtd->_read_fact_prot_reg = cfi_amdstd_read_fact_prot_reg;
548 mtd->_get_fact_prot_info = cfi_amdstd_get_fact_prot_info;
549 mtd->_get_user_prot_info = cfi_amdstd_get_user_prot_info;
550 mtd->_write_user_prot_reg = cfi_amdstd_write_user_prot_reg;
551 mtd->_lock_user_prot_reg = cfi_amdstd_lock_user_prot_reg;
552 mtd->flags = MTD_CAP_NORFLASH;
553 mtd->name = map->name;
555 mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
557 pr_debug("MTD %s(): write buffer size %d\n", __func__,
560 mtd->_panic_write = cfi_amdstd_panic_write;
561 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
563 if (cfi->cfi_mode==CFI_MODE_CFI){
564 unsigned char bootloc;
565 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
566 struct cfi_pri_amdstd *extp;
568 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
571 * It's a real CFI chip, not one for which the probe
572 * routine faked a CFI structure.
574 cfi_fixup_major_minor(cfi, extp);
577 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5
578 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19
579 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf
580 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf
581 * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf
583 if (extp->MajorVersion != '1' ||
584 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) {
585 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
586 "version %c.%c (%#02x/%#02x).\n",
587 extp->MajorVersion, extp->MinorVersion,
588 extp->MajorVersion, extp->MinorVersion);
594 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n",
595 extp->MajorVersion, extp->MinorVersion);
597 /* Install our own private info structure */
598 cfi->cmdset_priv = extp;
600 /* Apply cfi device specific fixups */
601 cfi_fixup(mtd, cfi_fixup_table);
603 #ifdef DEBUG_CFI_FEATURES
604 /* Tell the user about it in lots of lovely detail */
605 cfi_tell_features(extp);
609 if (np && of_property_read_bool(
610 np, "use-advanced-sector-protection")
611 && extp->BlkProtUnprot == 8) {
612 printk(KERN_INFO " Advanced Sector Protection (PPB Locking) supported\n");
613 mtd->_lock = cfi_ppb_lock;
614 mtd->_unlock = cfi_ppb_unlock;
615 mtd->_is_locked = cfi_ppb_is_locked;
619 bootloc = extp->TopBottom;
620 if ((bootloc < 2) || (bootloc > 5)) {
621 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
622 "bank location (%d). Assuming bottom.\n",
627 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
628 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
630 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
631 int j = (cfi->cfiq->NumEraseRegions-1)-i;
633 swap(cfi->cfiq->EraseRegionInfo[i],
634 cfi->cfiq->EraseRegionInfo[j]);
637 /* Set the default CFI lock/unlock addresses */
638 cfi->addr_unlock1 = 0x555;
639 cfi->addr_unlock2 = 0x2aa;
641 cfi_fixup(mtd, cfi_nopri_fixup_table);
643 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
649 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
650 /* Apply jedec specific fixups */
651 cfi_fixup(mtd, jedec_fixup_table);
653 /* Apply generic fixups */
654 cfi_fixup(mtd, fixup_table);
656 for (i=0; i< cfi->numchips; i++) {
657 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
658 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
659 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
661 * First calculate the timeout max according to timeout field
662 * of struct cfi_ident that probed from chip's CFI aera, if
663 * available. Specify a minimum of 2000us, in case the CFI data
666 if (cfi->cfiq->BufWriteTimeoutTyp &&
667 cfi->cfiq->BufWriteTimeoutMax)
668 cfi->chips[i].buffer_write_time_max =
669 1 << (cfi->cfiq->BufWriteTimeoutTyp +
670 cfi->cfiq->BufWriteTimeoutMax);
672 cfi->chips[i].buffer_write_time_max = 0;
674 cfi->chips[i].buffer_write_time_max =
675 max(cfi->chips[i].buffer_write_time_max, 2000);
677 cfi->chips[i].ref_point_counter = 0;
678 init_waitqueue_head(&(cfi->chips[i].wq));
681 map->fldrv = &cfi_amdstd_chipdrv;
683 return cfi_amdstd_setup(mtd);
685 struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
686 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
687 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
688 EXPORT_SYMBOL_GPL(cfi_cmdset_0006);
689 EXPORT_SYMBOL_GPL(cfi_cmdset_0701);
691 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
693 struct map_info *map = mtd->priv;
694 struct cfi_private *cfi = map->fldrv_priv;
695 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
696 unsigned long offset = 0;
699 printk(KERN_NOTICE "number of %s chips: %d\n",
700 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
701 /* Select the correct geometry setup */
702 mtd->size = devsize * cfi->numchips;
704 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
705 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
706 * mtd->numeraseregions, GFP_KERNEL);
707 if (!mtd->eraseregions)
710 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
711 unsigned long ernum, ersize;
712 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
713 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
715 if (mtd->erasesize < ersize) {
716 mtd->erasesize = ersize;
718 for (j=0; j<cfi->numchips; j++) {
719 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
720 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
721 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
723 offset += (ersize * ernum);
725 if (offset != devsize) {
727 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
731 __module_get(THIS_MODULE);
732 register_reboot_notifier(&mtd->reboot_notifier);
736 kfree(mtd->eraseregions);
738 kfree(cfi->cmdset_priv);
743 * Return true if the chip is ready and has the correct value.
745 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
746 * non-suspended sector) and is indicated by no toggle bits toggling.
748 * Error are indicated by toggling bits or bits held with the wrong value,
749 * or with bits toggling.
751 * Note that anything more complicated than checking if no bits are toggling
752 * (including checking DQ5 for an error status) is tricky to get working
753 * correctly and is therefore not done (particularly with interleaved chips
754 * as each chip must be checked independently of the others).
756 static int __xipram chip_ready(struct map_info *map, unsigned long addr,
762 d = map_read(map, addr);
763 t = map_read(map, addr);
765 ret = map_word_equal(map, d, t);
767 if (!ret || !expected)
770 return map_word_equal(map, t, *expected);
773 static int __xipram chip_good(struct map_info *map, unsigned long addr,
776 struct cfi_private *cfi = map->fldrv_priv;
777 map_word *datum = expected;
779 if (cfi->quirks & CFI_QUIRK_DQ_TRUE_DATA)
782 return chip_ready(map, addr, datum);
785 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
787 DECLARE_WAITQUEUE(wait, current);
788 struct cfi_private *cfi = map->fldrv_priv;
790 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
793 timeo = jiffies + HZ;
795 switch (chip->state) {
799 if (chip_ready(map, adr, NULL))
802 if (time_after(jiffies, timeo)) {
803 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
806 mutex_unlock(&chip->mutex);
808 mutex_lock(&chip->mutex);
809 /* Someone else might have been playing with it. */
819 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
820 !(mode == FL_READY || mode == FL_POINT ||
821 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
824 /* Do not allow suspend iff read/write to EB address */
825 if ((adr & chip->in_progress_block_mask) ==
826 chip->in_progress_block_addr)
830 /* It's harmless to issue the Erase-Suspend and Erase-Resume
831 * commands when the erase algorithm isn't in progress. */
832 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
833 chip->oldstate = FL_ERASING;
834 chip->state = FL_ERASE_SUSPENDING;
835 chip->erase_suspended = 1;
837 if (chip_ready(map, adr, NULL))
840 if (time_after(jiffies, timeo)) {
841 /* Should have suspended the erase by now.
842 * Send an Erase-Resume command as either
843 * there was an error (so leave the erase
844 * routine to recover from it) or we trying to
845 * use the erase-in-progress sector. */
846 put_chip(map, chip, adr);
847 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
851 mutex_unlock(&chip->mutex);
853 mutex_lock(&chip->mutex);
854 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
855 So we can just loop here. */
857 chip->state = FL_READY;
860 case FL_XIP_WHILE_ERASING:
861 if (mode != FL_READY && mode != FL_POINT &&
862 (!cfip || !(cfip->EraseSuspend&2)))
864 chip->oldstate = chip->state;
865 chip->state = FL_READY;
869 /* The machine is rebooting */
873 /* Only if there's no operation suspended... */
874 if (mode == FL_READY && chip->oldstate == FL_READY)
879 set_current_state(TASK_UNINTERRUPTIBLE);
880 add_wait_queue(&chip->wq, &wait);
881 mutex_unlock(&chip->mutex);
883 remove_wait_queue(&chip->wq, &wait);
884 mutex_lock(&chip->mutex);
890 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
892 struct cfi_private *cfi = map->fldrv_priv;
894 switch(chip->oldstate) {
896 cfi_fixup_m29ew_erase_suspend(map,
897 chip->in_progress_block_addr);
898 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
899 cfi_fixup_m29ew_delay_after_resume(cfi);
900 chip->oldstate = FL_READY;
901 chip->state = FL_ERASING;
904 case FL_XIP_WHILE_ERASING:
905 chip->state = chip->oldstate;
906 chip->oldstate = FL_READY;
913 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
918 #ifdef CONFIG_MTD_XIP
921 * No interrupt what so ever can be serviced while the flash isn't in array
922 * mode. This is ensured by the xip_disable() and xip_enable() functions
923 * enclosing any code path where the flash is known not to be in array mode.
924 * And within a XIP disabled code path, only functions marked with __xipram
925 * may be called and nothing else (it's a good thing to inspect generated
926 * assembly to make sure inline functions were actually inlined and that gcc
927 * didn't emit calls to its own support functions). Also configuring MTD CFI
928 * support to a single buswidth and a single interleave is also recommended.
931 static void xip_disable(struct map_info *map, struct flchip *chip,
934 /* TODO: chips with no XIP use should ignore and return */
935 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
939 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
942 struct cfi_private *cfi = map->fldrv_priv;
944 if (chip->state != FL_POINT && chip->state != FL_READY) {
945 map_write(map, CMD(0xf0), adr);
946 chip->state = FL_READY;
948 (void) map_read(map, adr);
954 * When a delay is required for the flash operation to complete, the
955 * xip_udelay() function is polling for both the given timeout and pending
956 * (but still masked) hardware interrupts. Whenever there is an interrupt
957 * pending then the flash erase operation is suspended, array mode restored
958 * and interrupts unmasked. Task scheduling might also happen at that
959 * point. The CPU eventually returns from the interrupt or the call to
960 * schedule() and the suspended flash operation is resumed for the remaining
961 * of the delay period.
963 * Warning: this function _will_ fool interrupt latency tracing tools.
966 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
967 unsigned long adr, int usec)
969 struct cfi_private *cfi = map->fldrv_priv;
970 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
971 map_word status, OK = CMD(0x80);
972 unsigned long suspended, start = xip_currtime();
977 if (xip_irqpending() && extp &&
978 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
979 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
981 * Let's suspend the erase operation when supported.
982 * Note that we currently don't try to suspend
983 * interleaved chips if there is already another
984 * operation suspended (imagine what happens
985 * when one chip was already done with the current
986 * operation while another chip suspended it, then
987 * we resume the whole thing at once). Yes, it
990 map_write(map, CMD(0xb0), adr);
991 usec -= xip_elapsed_since(start);
992 suspended = xip_currtime();
994 if (xip_elapsed_since(suspended) > 100000) {
996 * The chip doesn't want to suspend
997 * after waiting for 100 msecs.
998 * This is a critical error but there
999 * is not much we can do here.
1003 status = map_read(map, adr);
1004 } while (!map_word_andequal(map, status, OK, OK));
1006 /* Suspend succeeded */
1007 oldstate = chip->state;
1008 if (!map_word_bitsset(map, status, CMD(0x40)))
1010 chip->state = FL_XIP_WHILE_ERASING;
1011 chip->erase_suspended = 1;
1012 map_write(map, CMD(0xf0), adr);
1013 (void) map_read(map, adr);
1016 mutex_unlock(&chip->mutex);
1021 * We're back. However someone else might have
1022 * decided to go write to the chip if we are in
1023 * a suspended erase state. If so let's wait
1026 mutex_lock(&chip->mutex);
1027 while (chip->state != FL_XIP_WHILE_ERASING) {
1028 DECLARE_WAITQUEUE(wait, current);
1029 set_current_state(TASK_UNINTERRUPTIBLE);
1030 add_wait_queue(&chip->wq, &wait);
1031 mutex_unlock(&chip->mutex);
1033 remove_wait_queue(&chip->wq, &wait);
1034 mutex_lock(&chip->mutex);
1036 /* Disallow XIP again */
1037 local_irq_disable();
1039 /* Correct Erase Suspend Hangups for M29EW */
1040 cfi_fixup_m29ew_erase_suspend(map, adr);
1041 /* Resume the write or erase operation */
1042 map_write(map, cfi->sector_erase_cmd, adr);
1043 chip->state = oldstate;
1044 start = xip_currtime();
1045 } else if (usec >= 1000000/HZ) {
1047 * Try to save on CPU power when waiting delay
1048 * is at least a system timer tick period.
1049 * No need to be extremely accurate here.
1053 status = map_read(map, adr);
1054 } while (!map_word_andequal(map, status, OK, OK)
1055 && xip_elapsed_since(start) < usec);
1058 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
1061 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
1062 * the flash is actively programming or erasing since we have to poll for
1063 * the operation to complete anyway. We can't do that in a generic way with
1064 * a XIP setup so do it before the actual flash operation in this case
1065 * and stub it out from INVALIDATE_CACHE_UDELAY.
1067 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
1068 INVALIDATE_CACHED_RANGE(map, from, size)
1070 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1071 UDELAY(map, chip, adr, usec)
1076 * Activating this XIP support changes the way the code works a bit. For
1077 * example the code to suspend the current process when concurrent access
1078 * happens is never executed because xip_udelay() will always return with the
1079 * same chip state as it was entered with. This is why there is no care for
1080 * the presence of add_wait_queue() or schedule() calls from within a couple
1081 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
1082 * The queueing and scheduling are always happening within xip_udelay().
1084 * Similarly, get_chip() and put_chip() just happen to always be executed
1085 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
1086 * is in array mode, therefore never executing many cases therein and not
1087 * causing any problem with XIP.
1092 #define xip_disable(map, chip, adr)
1093 #define xip_enable(map, chip, adr)
1094 #define XIP_INVAL_CACHED_RANGE(x...)
1096 #define UDELAY(map, chip, adr, usec) \
1098 mutex_unlock(&chip->mutex); \
1100 mutex_lock(&chip->mutex); \
1103 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1105 mutex_unlock(&chip->mutex); \
1106 INVALIDATE_CACHED_RANGE(map, adr, len); \
1108 mutex_lock(&chip->mutex); \
1113 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1115 unsigned long cmd_addr;
1116 struct cfi_private *cfi = map->fldrv_priv;
1121 /* Ensure cmd read/writes are aligned. */
1122 cmd_addr = adr & ~(map_bankwidth(map)-1);
1124 mutex_lock(&chip->mutex);
1125 ret = get_chip(map, chip, cmd_addr, FL_READY);
1127 mutex_unlock(&chip->mutex);
1131 if (chip->state != FL_POINT && chip->state != FL_READY) {
1132 map_write(map, CMD(0xf0), cmd_addr);
1133 chip->state = FL_READY;
1136 map_copy_from(map, buf, adr, len);
1138 put_chip(map, chip, cmd_addr);
1140 mutex_unlock(&chip->mutex);
1145 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1147 struct map_info *map = mtd->priv;
1148 struct cfi_private *cfi = map->fldrv_priv;
1153 /* ofs: offset within the first chip that the first read should start */
1154 chipnum = (from >> cfi->chipshift);
1155 ofs = from - (chipnum << cfi->chipshift);
1158 unsigned long thislen;
1160 if (chipnum >= cfi->numchips)
1163 if ((len + ofs -1) >> cfi->chipshift)
1164 thislen = (1<<cfi->chipshift) - ofs;
1168 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1182 typedef int (*otp_op_t)(struct map_info *map, struct flchip *chip,
1183 loff_t adr, size_t len, u_char *buf, size_t grouplen);
1185 static inline void otp_enter(struct map_info *map, struct flchip *chip,
1186 loff_t adr, size_t len)
1188 struct cfi_private *cfi = map->fldrv_priv;
1190 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1191 cfi->device_type, NULL);
1192 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1193 cfi->device_type, NULL);
1194 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi,
1195 cfi->device_type, NULL);
1197 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1200 static inline void otp_exit(struct map_info *map, struct flchip *chip,
1201 loff_t adr, size_t len)
1203 struct cfi_private *cfi = map->fldrv_priv;
1205 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1206 cfi->device_type, NULL);
1207 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1208 cfi->device_type, NULL);
1209 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi,
1210 cfi->device_type, NULL);
1211 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi,
1212 cfi->device_type, NULL);
1214 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1217 static inline int do_read_secsi_onechip(struct map_info *map,
1218 struct flchip *chip, loff_t adr,
1219 size_t len, u_char *buf,
1222 DECLARE_WAITQUEUE(wait, current);
1223 unsigned long timeo = jiffies + HZ;
1226 mutex_lock(&chip->mutex);
1228 if (chip->state != FL_READY){
1229 set_current_state(TASK_UNINTERRUPTIBLE);
1230 add_wait_queue(&chip->wq, &wait);
1232 mutex_unlock(&chip->mutex);
1235 remove_wait_queue(&chip->wq, &wait);
1236 timeo = jiffies + HZ;
1243 chip->state = FL_READY;
1245 otp_enter(map, chip, adr, len);
1246 map_copy_from(map, buf, adr, len);
1247 otp_exit(map, chip, adr, len);
1250 mutex_unlock(&chip->mutex);
1255 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1257 struct map_info *map = mtd->priv;
1258 struct cfi_private *cfi = map->fldrv_priv;
1263 /* ofs: offset within the first chip that the first read should start */
1264 /* 8 secsi bytes per chip */
1269 unsigned long thislen;
1271 if (chipnum >= cfi->numchips)
1274 if ((len + ofs -1) >> 3)
1275 thislen = (1<<3) - ofs;
1279 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs,
1294 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1295 unsigned long adr, map_word datum,
1298 static int do_otp_write(struct map_info *map, struct flchip *chip, loff_t adr,
1299 size_t len, u_char *buf, size_t grouplen)
1303 unsigned long bus_ofs = adr & ~(map_bankwidth(map)-1);
1304 int gap = adr - bus_ofs;
1305 int n = min_t(int, len, map_bankwidth(map) - gap);
1306 map_word datum = map_word_ff(map);
1308 if (n != map_bankwidth(map)) {
1309 /* partial write of a word, load old contents */
1310 otp_enter(map, chip, bus_ofs, map_bankwidth(map));
1311 datum = map_read(map, bus_ofs);
1312 otp_exit(map, chip, bus_ofs, map_bankwidth(map));
1315 datum = map_word_load_partial(map, datum, buf, gap, n);
1316 ret = do_write_oneword(map, chip, bus_ofs, datum, FL_OTP_WRITE);
1328 static int do_otp_lock(struct map_info *map, struct flchip *chip, loff_t adr,
1329 size_t len, u_char *buf, size_t grouplen)
1331 struct cfi_private *cfi = map->fldrv_priv;
1333 unsigned long timeo;
1336 /* make sure area matches group boundaries */
1337 if ((adr != 0) || (len != grouplen))
1340 mutex_lock(&chip->mutex);
1341 ret = get_chip(map, chip, chip->start, FL_LOCKING);
1343 mutex_unlock(&chip->mutex);
1346 chip->state = FL_LOCKING;
1348 /* Enter lock register command */
1349 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1350 cfi->device_type, NULL);
1351 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1352 cfi->device_type, NULL);
1353 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi,
1354 cfi->device_type, NULL);
1356 /* read lock register */
1357 lockreg = cfi_read_query(map, 0);
1359 /* set bit 0 to protect extended memory block */
1362 /* set bit 0 to protect extended memory block */
1363 /* write lock register */
1364 map_write(map, CMD(0xA0), chip->start);
1365 map_write(map, CMD(lockreg), chip->start);
1367 /* wait for chip to become ready */
1368 timeo = jiffies + msecs_to_jiffies(2);
1370 if (chip_ready(map, adr, NULL))
1373 if (time_after(jiffies, timeo)) {
1374 pr_err("Waiting for chip to be ready timed out.\n");
1378 UDELAY(map, chip, 0, 1);
1381 /* exit protection commands */
1382 map_write(map, CMD(0x90), chip->start);
1383 map_write(map, CMD(0x00), chip->start);
1385 chip->state = FL_READY;
1386 put_chip(map, chip, chip->start);
1387 mutex_unlock(&chip->mutex);
1392 static int cfi_amdstd_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
1393 size_t *retlen, u_char *buf,
1394 otp_op_t action, int user_regs)
1396 struct map_info *map = mtd->priv;
1397 struct cfi_private *cfi = map->fldrv_priv;
1398 int ofs_factor = cfi->interleave * cfi->device_type;
1401 struct flchip *chip;
1402 uint8_t otp, lockreg;
1405 size_t user_size, factory_size, otpsize;
1406 loff_t user_offset, factory_offset, otpoffset;
1407 int user_locked = 0, otplocked;
1411 for (chipnum = 0; chipnum < cfi->numchips; chipnum++) {
1412 chip = &cfi->chips[chipnum];
1416 /* Micron M29EW family */
1417 if (is_m29ew(cfi)) {
1420 /* check whether secsi area is factory locked
1422 mutex_lock(&chip->mutex);
1423 ret = get_chip(map, chip, base, FL_CFI_QUERY);
1425 mutex_unlock(&chip->mutex);
1428 cfi_qry_mode_on(base, map, cfi);
1429 otp = cfi_read_query(map, base + 0x3 * ofs_factor);
1430 cfi_qry_mode_off(base, map, cfi);
1431 put_chip(map, chip, base);
1432 mutex_unlock(&chip->mutex);
1435 /* factory locked */
1437 factory_size = 0x100;
1439 /* customer lockable */
1443 mutex_lock(&chip->mutex);
1444 ret = get_chip(map, chip, base, FL_LOCKING);
1446 mutex_unlock(&chip->mutex);
1450 /* Enter lock register command */
1451 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1,
1452 chip->start, map, cfi,
1453 cfi->device_type, NULL);
1454 cfi_send_gen_cmd(0x55, cfi->addr_unlock2,
1455 chip->start, map, cfi,
1456 cfi->device_type, NULL);
1457 cfi_send_gen_cmd(0x40, cfi->addr_unlock1,
1458 chip->start, map, cfi,
1459 cfi->device_type, NULL);
1460 /* read lock register */
1461 lockreg = cfi_read_query(map, 0);
1462 /* exit protection commands */
1463 map_write(map, CMD(0x90), chip->start);
1464 map_write(map, CMD(0x00), chip->start);
1465 put_chip(map, chip, chip->start);
1466 mutex_unlock(&chip->mutex);
1468 user_locked = ((lockreg & 0x01) == 0x00);
1472 otpsize = user_regs ? user_size : factory_size;
1475 otpoffset = user_regs ? user_offset : factory_offset;
1476 otplocked = user_regs ? user_locked : 1;
1479 /* return otpinfo */
1480 struct otp_info *otpinfo;
1481 len -= sizeof(*otpinfo);
1484 otpinfo = (struct otp_info *)buf;
1485 otpinfo->start = from;
1486 otpinfo->length = otpsize;
1487 otpinfo->locked = otplocked;
1488 buf += sizeof(*otpinfo);
1489 *retlen += sizeof(*otpinfo);
1491 } else if ((from < otpsize) && (len > 0)) {
1493 size = (len < otpsize - from) ? len : otpsize - from;
1494 ret = action(map, chip, otpoffset + from, size, buf,
1510 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *mtd, size_t len,
1511 size_t *retlen, struct otp_info *buf)
1513 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1517 static int cfi_amdstd_get_user_prot_info(struct mtd_info *mtd, size_t len,
1518 size_t *retlen, struct otp_info *buf)
1520 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1524 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
1525 size_t len, size_t *retlen,
1528 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1529 buf, do_read_secsi_onechip, 0);
1532 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
1533 size_t len, size_t *retlen,
1536 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1537 buf, do_read_secsi_onechip, 1);
1540 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
1541 size_t len, size_t *retlen,
1544 return cfi_amdstd_otp_walk(mtd, from, len, retlen, buf,
1548 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
1552 return cfi_amdstd_otp_walk(mtd, from, len, &retlen, NULL,
1556 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1557 unsigned long adr, map_word datum,
1560 struct cfi_private *cfi = map->fldrv_priv;
1561 unsigned long timeo = jiffies + HZ;
1563 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1564 * have a max write time of a few hundreds usec). However, we should
1565 * use the maximum timeout value given by the chip at probe time
1566 * instead. Unfortunately, struct flchip does have a field for
1567 * maximum timeout, only for typical which can be far too short
1568 * depending of the conditions. The ' + 1' is to avoid having a
1569 * timeout of 0 jiffies if HZ is smaller than 1000.
1571 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1578 mutex_lock(&chip->mutex);
1579 ret = get_chip(map, chip, adr, mode);
1581 mutex_unlock(&chip->mutex);
1585 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1586 __func__, adr, datum.x[0] );
1588 if (mode == FL_OTP_WRITE)
1589 otp_enter(map, chip, adr, map_bankwidth(map));
1592 * Check for a NOP for the case when the datum to write is already
1593 * present - it saves time and works around buggy chips that corrupt
1594 * data at other locations when 0xff is written to a location that
1595 * already contains 0xff.
1597 oldd = map_read(map, adr);
1598 if (map_word_equal(map, oldd, datum)) {
1599 pr_debug("MTD %s(): NOP\n",
1604 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1606 xip_disable(map, chip, adr);
1609 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1610 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1611 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1612 map_write(map, datum, adr);
1615 INVALIDATE_CACHE_UDELAY(map, chip,
1616 adr, map_bankwidth(map),
1617 chip->word_write_time);
1619 /* See comment above for timeout value. */
1620 timeo = jiffies + uWriteTimeout;
1622 if (chip->state != mode) {
1623 /* Someone's suspended the write. Sleep */
1624 DECLARE_WAITQUEUE(wait, current);
1626 set_current_state(TASK_UNINTERRUPTIBLE);
1627 add_wait_queue(&chip->wq, &wait);
1628 mutex_unlock(&chip->mutex);
1630 remove_wait_queue(&chip->wq, &wait);
1631 timeo = jiffies + (HZ / 2); /* FIXME */
1632 mutex_lock(&chip->mutex);
1637 * We check "time_after" and "!chip_good" before checking
1638 * "chip_good" to avoid the failure due to scheduling.
1640 if (time_after(jiffies, timeo) &&
1641 !chip_good(map, adr, &datum)) {
1642 xip_enable(map, chip, adr);
1643 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1644 xip_disable(map, chip, adr);
1649 if (chip_good(map, adr, &datum))
1652 /* Latency issues. Drop the lock, wait a while and retry */
1653 UDELAY(map, chip, adr, 1);
1656 /* Did we succeed? */
1658 /* reset on all failures. */
1659 map_write( map, CMD(0xF0), chip->start );
1660 /* FIXME - should have reset delay before continuing */
1662 if (++retry_cnt <= MAX_RETRIES) {
1667 xip_enable(map, chip, adr);
1669 if (mode == FL_OTP_WRITE)
1670 otp_exit(map, chip, adr, map_bankwidth(map));
1671 chip->state = FL_READY;
1673 put_chip(map, chip, adr);
1674 mutex_unlock(&chip->mutex);
1680 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1681 size_t *retlen, const u_char *buf)
1683 struct map_info *map = mtd->priv;
1684 struct cfi_private *cfi = map->fldrv_priv;
1687 unsigned long ofs, chipstart;
1688 DECLARE_WAITQUEUE(wait, current);
1690 chipnum = to >> cfi->chipshift;
1691 ofs = to - (chipnum << cfi->chipshift);
1692 chipstart = cfi->chips[chipnum].start;
1694 /* If it's not bus-aligned, do the first byte write */
1695 if (ofs & (map_bankwidth(map)-1)) {
1696 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1697 int i = ofs - bus_ofs;
1702 mutex_lock(&cfi->chips[chipnum].mutex);
1704 if (cfi->chips[chipnum].state != FL_READY) {
1705 set_current_state(TASK_UNINTERRUPTIBLE);
1706 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1708 mutex_unlock(&cfi->chips[chipnum].mutex);
1711 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1715 /* Load 'tmp_buf' with old contents of flash */
1716 tmp_buf = map_read(map, bus_ofs+chipstart);
1718 mutex_unlock(&cfi->chips[chipnum].mutex);
1720 /* Number of bytes to copy from buffer */
1721 n = min_t(int, len, map_bankwidth(map)-i);
1723 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1725 ret = do_write_oneword(map, &cfi->chips[chipnum],
1726 bus_ofs, tmp_buf, FL_WRITING);
1735 if (ofs >> cfi->chipshift) {
1738 if (chipnum == cfi->numchips)
1743 /* We are now aligned, write as much as possible */
1744 while(len >= map_bankwidth(map)) {
1747 datum = map_word_load(map, buf);
1749 ret = do_write_oneword(map, &cfi->chips[chipnum],
1750 ofs, datum, FL_WRITING);
1754 ofs += map_bankwidth(map);
1755 buf += map_bankwidth(map);
1756 (*retlen) += map_bankwidth(map);
1757 len -= map_bankwidth(map);
1759 if (ofs >> cfi->chipshift) {
1762 if (chipnum == cfi->numchips)
1764 chipstart = cfi->chips[chipnum].start;
1768 /* Write the trailing bytes if any */
1769 if (len & (map_bankwidth(map)-1)) {
1773 mutex_lock(&cfi->chips[chipnum].mutex);
1775 if (cfi->chips[chipnum].state != FL_READY) {
1776 set_current_state(TASK_UNINTERRUPTIBLE);
1777 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1779 mutex_unlock(&cfi->chips[chipnum].mutex);
1782 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1786 tmp_buf = map_read(map, ofs + chipstart);
1788 mutex_unlock(&cfi->chips[chipnum].mutex);
1790 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1792 ret = do_write_oneword(map, &cfi->chips[chipnum],
1793 ofs, tmp_buf, FL_WRITING);
1805 * FIXME: interleaved mode not tested, and probably not supported!
1807 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1808 unsigned long adr, const u_char *buf,
1811 struct cfi_private *cfi = map->fldrv_priv;
1812 unsigned long timeo = jiffies + HZ;
1814 * Timeout is calculated according to CFI data, if available.
1815 * See more comments in cfi_cmdset_0002().
1817 unsigned long uWriteTimeout =
1818 usecs_to_jiffies(chip->buffer_write_time_max);
1820 unsigned long cmd_adr;
1827 mutex_lock(&chip->mutex);
1828 ret = get_chip(map, chip, adr, FL_WRITING);
1830 mutex_unlock(&chip->mutex);
1834 datum = map_word_load(map, buf);
1836 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1837 __func__, adr, datum.x[0] );
1839 XIP_INVAL_CACHED_RANGE(map, adr, len);
1841 xip_disable(map, chip, cmd_adr);
1843 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1844 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1846 /* Write Buffer Load */
1847 map_write(map, CMD(0x25), cmd_adr);
1849 chip->state = FL_WRITING_TO_BUFFER;
1851 /* Write length of data to come */
1852 words = len / map_bankwidth(map);
1853 map_write(map, CMD(words - 1), cmd_adr);
1856 while(z < words * map_bankwidth(map)) {
1857 datum = map_word_load(map, buf);
1858 map_write(map, datum, adr + z);
1860 z += map_bankwidth(map);
1861 buf += map_bankwidth(map);
1863 z -= map_bankwidth(map);
1867 /* Write Buffer Program Confirm: GO GO GO */
1868 map_write(map, CMD(0x29), cmd_adr);
1869 chip->state = FL_WRITING;
1871 INVALIDATE_CACHE_UDELAY(map, chip,
1872 adr, map_bankwidth(map),
1873 chip->word_write_time);
1875 timeo = jiffies + uWriteTimeout;
1878 if (chip->state != FL_WRITING) {
1879 /* Someone's suspended the write. Sleep */
1880 DECLARE_WAITQUEUE(wait, current);
1882 set_current_state(TASK_UNINTERRUPTIBLE);
1883 add_wait_queue(&chip->wq, &wait);
1884 mutex_unlock(&chip->mutex);
1886 remove_wait_queue(&chip->wq, &wait);
1887 timeo = jiffies + (HZ / 2); /* FIXME */
1888 mutex_lock(&chip->mutex);
1893 * We check "time_after" and "!chip_good" before checking
1894 * "chip_good" to avoid the failure due to scheduling.
1896 if (time_after(jiffies, timeo) && !chip_good(map, adr, &datum))
1899 if (chip_good(map, adr, &datum)) {
1900 xip_enable(map, chip, adr);
1904 /* Latency issues. Drop the lock, wait a while and retry */
1905 UDELAY(map, chip, adr, 1);
1909 * Recovery from write-buffer programming failures requires
1910 * the write-to-buffer-reset sequence. Since the last part
1911 * of the sequence also works as a normal reset, we can run
1912 * the same commands regardless of why we are here.
1914 * http://www.spansion.com/Support/Application%20Notes/MirrorBit_Write_Buffer_Prog_Page_Buffer_Read_AN.pdf
1916 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1917 cfi->device_type, NULL);
1918 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1919 cfi->device_type, NULL);
1920 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi,
1921 cfi->device_type, NULL);
1922 xip_enable(map, chip, adr);
1923 /* FIXME - should have reset delay before continuing */
1925 printk(KERN_WARNING "MTD %s(): software timeout, address:0x%.8lx.\n",
1930 chip->state = FL_READY;
1932 put_chip(map, chip, adr);
1933 mutex_unlock(&chip->mutex);
1939 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1940 size_t *retlen, const u_char *buf)
1942 struct map_info *map = mtd->priv;
1943 struct cfi_private *cfi = map->fldrv_priv;
1944 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1949 chipnum = to >> cfi->chipshift;
1950 ofs = to - (chipnum << cfi->chipshift);
1952 /* If it's not bus-aligned, do the first word write */
1953 if (ofs & (map_bankwidth(map)-1)) {
1954 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1955 if (local_len > len)
1957 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1958 local_len, retlen, buf);
1965 if (ofs >> cfi->chipshift) {
1968 if (chipnum == cfi->numchips)
1973 /* Write buffer is worth it only if more than one word to write... */
1974 while (len >= map_bankwidth(map) * 2) {
1975 /* We must not cross write block boundaries */
1976 int size = wbufsize - (ofs & (wbufsize-1));
1980 if (size % map_bankwidth(map))
1981 size -= size % map_bankwidth(map);
1983 ret = do_write_buffer(map, &cfi->chips[chipnum],
1993 if (ofs >> cfi->chipshift) {
1996 if (chipnum == cfi->numchips)
2002 size_t retlen_dregs = 0;
2004 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
2005 len, &retlen_dregs, buf);
2007 *retlen += retlen_dregs;
2015 * Wait for the flash chip to become ready to write data
2017 * This is only called during the panic_write() path. When panic_write()
2018 * is called, the kernel is in the process of a panic, and will soon be
2019 * dead. Therefore we don't take any locks, and attempt to get access
2020 * to the chip as soon as possible.
2022 static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip,
2025 struct cfi_private *cfi = map->fldrv_priv;
2030 * If the driver thinks the chip is idle, and no toggle bits
2031 * are changing, then the chip is actually idle for sure.
2033 if (chip->state == FL_READY && chip_ready(map, adr, NULL))
2037 * Try several times to reset the chip and then wait for it
2038 * to become idle. The upper limit of a few milliseconds of
2039 * delay isn't a big problem: the kernel is dying anyway. It
2040 * is more important to save the messages.
2042 while (retries > 0) {
2043 const unsigned long timeo = (HZ / 1000) + 1;
2045 /* send the reset command */
2046 map_write(map, CMD(0xF0), chip->start);
2048 /* wait for the chip to become ready */
2049 for (i = 0; i < jiffies_to_usecs(timeo); i++) {
2050 if (chip_ready(map, adr, NULL))
2059 /* the chip never became ready */
2064 * Write out one word of data to a single flash chip during a kernel panic
2066 * This is only called during the panic_write() path. When panic_write()
2067 * is called, the kernel is in the process of a panic, and will soon be
2068 * dead. Therefore we don't take any locks, and attempt to get access
2069 * to the chip as soon as possible.
2071 * The implementation of this routine is intentionally similar to
2072 * do_write_oneword(), in order to ease code maintenance.
2074 static int do_panic_write_oneword(struct map_info *map, struct flchip *chip,
2075 unsigned long adr, map_word datum)
2077 const unsigned long uWriteTimeout = (HZ / 1000) + 1;
2078 struct cfi_private *cfi = map->fldrv_priv;
2086 ret = cfi_amdstd_panic_wait(map, chip, adr);
2090 pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n",
2091 __func__, adr, datum.x[0]);
2094 * Check for a NOP for the case when the datum to write is already
2095 * present - it saves time and works around buggy chips that corrupt
2096 * data at other locations when 0xff is written to a location that
2097 * already contains 0xff.
2099 oldd = map_read(map, adr);
2100 if (map_word_equal(map, oldd, datum)) {
2101 pr_debug("MTD %s(): NOP\n", __func__);
2108 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2109 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2110 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2111 map_write(map, datum, adr);
2113 for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) {
2114 if (chip_ready(map, adr, NULL))
2120 if (!chip_ready(map, adr, &datum)) {
2121 /* reset on all failures. */
2122 map_write(map, CMD(0xF0), chip->start);
2123 /* FIXME - should have reset delay before continuing */
2125 if (++retry_cnt <= MAX_RETRIES)
2137 * Write out some data during a kernel panic
2139 * This is used by the mtdoops driver to save the dying messages from a
2140 * kernel which has panic'd.
2142 * This routine ignores all of the locking used throughout the rest of the
2143 * driver, in order to ensure that the data gets written out no matter what
2144 * state this driver (and the flash chip itself) was in when the kernel crashed.
2146 * The implementation of this routine is intentionally similar to
2147 * cfi_amdstd_write_words(), in order to ease code maintenance.
2149 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
2150 size_t *retlen, const u_char *buf)
2152 struct map_info *map = mtd->priv;
2153 struct cfi_private *cfi = map->fldrv_priv;
2154 unsigned long ofs, chipstart;
2158 chipnum = to >> cfi->chipshift;
2159 ofs = to - (chipnum << cfi->chipshift);
2160 chipstart = cfi->chips[chipnum].start;
2162 /* If it's not bus aligned, do the first byte write */
2163 if (ofs & (map_bankwidth(map) - 1)) {
2164 unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1);
2165 int i = ofs - bus_ofs;
2169 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs);
2173 /* Load 'tmp_buf' with old contents of flash */
2174 tmp_buf = map_read(map, bus_ofs + chipstart);
2176 /* Number of bytes to copy from buffer */
2177 n = min_t(int, len, map_bankwidth(map) - i);
2179 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
2181 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2191 if (ofs >> cfi->chipshift) {
2194 if (chipnum == cfi->numchips)
2199 /* We are now aligned, write as much as possible */
2200 while (len >= map_bankwidth(map)) {
2203 datum = map_word_load(map, buf);
2205 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2210 ofs += map_bankwidth(map);
2211 buf += map_bankwidth(map);
2212 (*retlen) += map_bankwidth(map);
2213 len -= map_bankwidth(map);
2215 if (ofs >> cfi->chipshift) {
2218 if (chipnum == cfi->numchips)
2221 chipstart = cfi->chips[chipnum].start;
2225 /* Write the trailing bytes if any */
2226 if (len & (map_bankwidth(map) - 1)) {
2229 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs);
2233 tmp_buf = map_read(map, ofs + chipstart);
2235 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
2237 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2250 * Handle devices with one erase region, that only implement
2251 * the chip erase command.
2253 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
2255 struct cfi_private *cfi = map->fldrv_priv;
2256 unsigned long timeo = jiffies + HZ;
2257 unsigned long int adr;
2258 DECLARE_WAITQUEUE(wait, current);
2261 map_word datum = map_word_ff(map);
2263 adr = cfi->addr_unlock1;
2265 mutex_lock(&chip->mutex);
2266 ret = get_chip(map, chip, adr, FL_WRITING);
2268 mutex_unlock(&chip->mutex);
2272 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2273 __func__, chip->start );
2275 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
2277 xip_disable(map, chip, adr);
2280 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2281 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2282 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2283 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2284 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2285 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2287 chip->state = FL_ERASING;
2288 chip->erase_suspended = 0;
2289 chip->in_progress_block_addr = adr;
2290 chip->in_progress_block_mask = ~(map->size - 1);
2292 INVALIDATE_CACHE_UDELAY(map, chip,
2294 chip->erase_time*500);
2296 timeo = jiffies + (HZ*20);
2299 if (chip->state != FL_ERASING) {
2300 /* Someone's suspended the erase. Sleep */
2301 set_current_state(TASK_UNINTERRUPTIBLE);
2302 add_wait_queue(&chip->wq, &wait);
2303 mutex_unlock(&chip->mutex);
2305 remove_wait_queue(&chip->wq, &wait);
2306 mutex_lock(&chip->mutex);
2309 if (chip->erase_suspended) {
2310 /* This erase was suspended and resumed.
2311 Adjust the timeout */
2312 timeo = jiffies + (HZ*20); /* FIXME */
2313 chip->erase_suspended = 0;
2316 if (chip_ready(map, adr, &datum))
2319 if (time_after(jiffies, timeo)) {
2320 printk(KERN_WARNING "MTD %s(): software timeout\n",
2326 /* Latency issues. Drop the lock, wait a while and retry */
2327 UDELAY(map, chip, adr, 1000000/HZ);
2329 /* Did we succeed? */
2331 /* reset on all failures. */
2332 map_write( map, CMD(0xF0), chip->start );
2333 /* FIXME - should have reset delay before continuing */
2335 if (++retry_cnt <= MAX_RETRIES) {
2341 chip->state = FL_READY;
2342 xip_enable(map, chip, adr);
2344 put_chip(map, chip, adr);
2345 mutex_unlock(&chip->mutex);
2351 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
2353 struct cfi_private *cfi = map->fldrv_priv;
2354 unsigned long timeo = jiffies + HZ;
2355 DECLARE_WAITQUEUE(wait, current);
2358 map_word datum = map_word_ff(map);
2362 mutex_lock(&chip->mutex);
2363 ret = get_chip(map, chip, adr, FL_ERASING);
2365 mutex_unlock(&chip->mutex);
2369 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2372 XIP_INVAL_CACHED_RANGE(map, adr, len);
2374 xip_disable(map, chip, adr);
2377 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2378 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2379 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2380 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2381 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2382 map_write(map, cfi->sector_erase_cmd, adr);
2384 chip->state = FL_ERASING;
2385 chip->erase_suspended = 0;
2386 chip->in_progress_block_addr = adr;
2387 chip->in_progress_block_mask = ~(len - 1);
2389 INVALIDATE_CACHE_UDELAY(map, chip,
2391 chip->erase_time*500);
2393 timeo = jiffies + (HZ*20);
2396 if (chip->state != FL_ERASING) {
2397 /* Someone's suspended the erase. Sleep */
2398 set_current_state(TASK_UNINTERRUPTIBLE);
2399 add_wait_queue(&chip->wq, &wait);
2400 mutex_unlock(&chip->mutex);
2402 remove_wait_queue(&chip->wq, &wait);
2403 mutex_lock(&chip->mutex);
2406 if (chip->erase_suspended) {
2407 /* This erase was suspended and resumed.
2408 Adjust the timeout */
2409 timeo = jiffies + (HZ*20); /* FIXME */
2410 chip->erase_suspended = 0;
2413 if (chip_ready(map, adr, &datum)) {
2414 xip_enable(map, chip, adr);
2418 if (time_after(jiffies, timeo)) {
2419 xip_enable(map, chip, adr);
2420 printk(KERN_WARNING "MTD %s(): software timeout\n",
2426 /* Latency issues. Drop the lock, wait a while and retry */
2427 UDELAY(map, chip, adr, 1000000/HZ);
2429 /* Did we succeed? */
2431 /* reset on all failures. */
2432 map_write( map, CMD(0xF0), chip->start );
2433 /* FIXME - should have reset delay before continuing */
2435 if (++retry_cnt <= MAX_RETRIES) {
2441 chip->state = FL_READY;
2443 put_chip(map, chip, adr);
2444 mutex_unlock(&chip->mutex);
2449 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
2451 unsigned long ofs, len;
2457 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
2461 instr->state = MTD_ERASE_DONE;
2462 mtd_erase_callback(instr);
2468 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
2470 struct map_info *map = mtd->priv;
2471 struct cfi_private *cfi = map->fldrv_priv;
2474 if (instr->addr != 0)
2477 if (instr->len != mtd->size)
2480 ret = do_erase_chip(map, &cfi->chips[0]);
2484 instr->state = MTD_ERASE_DONE;
2485 mtd_erase_callback(instr);
2490 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
2491 unsigned long adr, int len, void *thunk)
2493 struct cfi_private *cfi = map->fldrv_priv;
2496 mutex_lock(&chip->mutex);
2497 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
2500 chip->state = FL_LOCKING;
2502 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2504 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2505 cfi->device_type, NULL);
2506 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2507 cfi->device_type, NULL);
2508 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
2509 cfi->device_type, NULL);
2510 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2511 cfi->device_type, NULL);
2512 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2513 cfi->device_type, NULL);
2514 map_write(map, CMD(0x40), chip->start + adr);
2516 chip->state = FL_READY;
2517 put_chip(map, chip, adr + chip->start);
2521 mutex_unlock(&chip->mutex);
2525 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
2526 unsigned long adr, int len, void *thunk)
2528 struct cfi_private *cfi = map->fldrv_priv;
2531 mutex_lock(&chip->mutex);
2532 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
2535 chip->state = FL_UNLOCKING;
2537 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2539 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2540 cfi->device_type, NULL);
2541 map_write(map, CMD(0x70), adr);
2543 chip->state = FL_READY;
2544 put_chip(map, chip, adr + chip->start);
2548 mutex_unlock(&chip->mutex);
2552 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2554 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
2557 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2559 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
2563 * Advanced Sector Protection - PPB (Persistent Protection Bit) locking
2567 struct flchip *chip;
2572 #define MAX_SECTORS 512
2574 #define DO_XXLOCK_ONEBLOCK_LOCK ((void *)1)
2575 #define DO_XXLOCK_ONEBLOCK_UNLOCK ((void *)2)
2576 #define DO_XXLOCK_ONEBLOCK_GETLOCK ((void *)3)
2578 static int __maybe_unused do_ppb_xxlock(struct map_info *map,
2579 struct flchip *chip,
2580 unsigned long adr, int len, void *thunk)
2582 struct cfi_private *cfi = map->fldrv_priv;
2583 unsigned long timeo;
2587 mutex_lock(&chip->mutex);
2588 ret = get_chip(map, chip, adr, FL_LOCKING);
2590 mutex_unlock(&chip->mutex);
2594 pr_debug("MTD %s(): XXLOCK 0x%08lx len %d\n", __func__, adr, len);
2596 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2597 cfi->device_type, NULL);
2598 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2599 cfi->device_type, NULL);
2600 /* PPB entry command */
2601 cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi,
2602 cfi->device_type, NULL);
2604 if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) {
2605 chip->state = FL_LOCKING;
2606 map_write(map, CMD(0xA0), adr);
2607 map_write(map, CMD(0x00), adr);
2608 } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) {
2610 * Unlocking of one specific sector is not supported, so we
2611 * have to unlock all sectors of this device instead
2613 chip->state = FL_UNLOCKING;
2614 map_write(map, CMD(0x80), chip->start);
2615 map_write(map, CMD(0x30), chip->start);
2616 } else if (thunk == DO_XXLOCK_ONEBLOCK_GETLOCK) {
2617 chip->state = FL_JEDEC_QUERY;
2618 /* Return locked status: 0->locked, 1->unlocked */
2619 ret = !cfi_read_query(map, adr);
2624 * Wait for some time as unlocking of all sectors takes quite long
2626 timeo = jiffies + msecs_to_jiffies(2000); /* 2s max (un)locking */
2628 if (chip_ready(map, adr, NULL))
2631 if (time_after(jiffies, timeo)) {
2632 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
2637 UDELAY(map, chip, adr, 1);
2640 /* Exit BC commands */
2641 map_write(map, CMD(0x90), chip->start);
2642 map_write(map, CMD(0x00), chip->start);
2644 chip->state = FL_READY;
2645 put_chip(map, chip, adr);
2646 mutex_unlock(&chip->mutex);
2651 static int __maybe_unused cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs,
2654 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2655 DO_XXLOCK_ONEBLOCK_LOCK);
2658 static int __maybe_unused cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs,
2661 struct mtd_erase_region_info *regions = mtd->eraseregions;
2662 struct map_info *map = mtd->priv;
2663 struct cfi_private *cfi = map->fldrv_priv;
2664 struct ppb_lock *sect;
2674 * PPB unlocking always unlocks all sectors of the flash chip.
2675 * We need to re-lock all previously locked sectors. So lets
2676 * first check the locking status of all sectors and save
2677 * it for future use.
2679 sect = kzalloc(MAX_SECTORS * sizeof(struct ppb_lock), GFP_KERNEL);
2684 * This code to walk all sectors is a slightly modified version
2685 * of the cfi_varsize_frob() code.
2695 int size = regions[i].erasesize;
2698 * Only test sectors that shall not be unlocked. The other
2699 * sectors shall be unlocked, so lets keep their locking
2700 * status at "unlocked" (locked=0) for the final re-locking.
2702 if ((offset < ofs) || (offset >= (ofs + len))) {
2703 sect[sectors].chip = &cfi->chips[chipnum];
2704 sect[sectors].adr = adr;
2705 sect[sectors].locked = do_ppb_xxlock(
2706 map, &cfi->chips[chipnum], adr, 0,
2707 DO_XXLOCK_ONEBLOCK_GETLOCK);
2714 if (offset == regions[i].offset + size * regions[i].numblocks)
2717 if (adr >> cfi->chipshift) {
2718 if (offset >= (ofs + len))
2723 if (chipnum >= cfi->numchips)
2728 if (sectors >= MAX_SECTORS) {
2729 printk(KERN_ERR "Only %d sectors for PPB locking supported!\n",
2736 /* Now unlock the whole chip */
2737 ret = cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2738 DO_XXLOCK_ONEBLOCK_UNLOCK);
2745 * PPB unlocking always unlocks all sectors of the flash chip.
2746 * We need to re-lock all previously locked sectors.
2748 for (i = 0; i < sectors; i++) {
2750 do_ppb_xxlock(map, sect[i].chip, sect[i].adr, 0,
2751 DO_XXLOCK_ONEBLOCK_LOCK);
2758 static int __maybe_unused cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs,
2761 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2762 DO_XXLOCK_ONEBLOCK_GETLOCK) ? 1 : 0;
2765 static void cfi_amdstd_sync (struct mtd_info *mtd)
2767 struct map_info *map = mtd->priv;
2768 struct cfi_private *cfi = map->fldrv_priv;
2770 struct flchip *chip;
2772 DECLARE_WAITQUEUE(wait, current);
2774 for (i=0; !ret && i<cfi->numchips; i++) {
2775 chip = &cfi->chips[i];
2778 mutex_lock(&chip->mutex);
2780 switch(chip->state) {
2784 case FL_JEDEC_QUERY:
2785 chip->oldstate = chip->state;
2786 chip->state = FL_SYNCING;
2787 /* No need to wake_up() on this state change -
2788 * as the whole point is that nobody can do anything
2789 * with the chip now anyway.
2792 mutex_unlock(&chip->mutex);
2796 /* Not an idle state */
2797 set_current_state(TASK_UNINTERRUPTIBLE);
2798 add_wait_queue(&chip->wq, &wait);
2800 mutex_unlock(&chip->mutex);
2804 remove_wait_queue(&chip->wq, &wait);
2810 /* Unlock the chips again */
2812 for (i--; i >=0; i--) {
2813 chip = &cfi->chips[i];
2815 mutex_lock(&chip->mutex);
2817 if (chip->state == FL_SYNCING) {
2818 chip->state = chip->oldstate;
2821 mutex_unlock(&chip->mutex);
2826 static int cfi_amdstd_suspend(struct mtd_info *mtd)
2828 struct map_info *map = mtd->priv;
2829 struct cfi_private *cfi = map->fldrv_priv;
2831 struct flchip *chip;
2834 for (i=0; !ret && i<cfi->numchips; i++) {
2835 chip = &cfi->chips[i];
2837 mutex_lock(&chip->mutex);
2839 switch(chip->state) {
2843 case FL_JEDEC_QUERY:
2844 chip->oldstate = chip->state;
2845 chip->state = FL_PM_SUSPENDED;
2846 /* No need to wake_up() on this state change -
2847 * as the whole point is that nobody can do anything
2848 * with the chip now anyway.
2850 case FL_PM_SUSPENDED:
2857 mutex_unlock(&chip->mutex);
2860 /* Unlock the chips again */
2863 for (i--; i >=0; i--) {
2864 chip = &cfi->chips[i];
2866 mutex_lock(&chip->mutex);
2868 if (chip->state == FL_PM_SUSPENDED) {
2869 chip->state = chip->oldstate;
2872 mutex_unlock(&chip->mutex);
2880 static void cfi_amdstd_resume(struct mtd_info *mtd)
2882 struct map_info *map = mtd->priv;
2883 struct cfi_private *cfi = map->fldrv_priv;
2885 struct flchip *chip;
2887 for (i=0; i<cfi->numchips; i++) {
2889 chip = &cfi->chips[i];
2891 mutex_lock(&chip->mutex);
2893 if (chip->state == FL_PM_SUSPENDED) {
2894 chip->state = FL_READY;
2895 map_write(map, CMD(0xF0), chip->start);
2899 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
2901 mutex_unlock(&chip->mutex);
2907 * Ensure that the flash device is put back into read array mode before
2908 * unloading the driver or rebooting. On some systems, rebooting while
2909 * the flash is in query/program/erase mode will prevent the CPU from
2910 * fetching the bootloader code, requiring a hard reset or power cycle.
2912 static int cfi_amdstd_reset(struct mtd_info *mtd)
2914 struct map_info *map = mtd->priv;
2915 struct cfi_private *cfi = map->fldrv_priv;
2917 struct flchip *chip;
2919 for (i = 0; i < cfi->numchips; i++) {
2921 chip = &cfi->chips[i];
2923 mutex_lock(&chip->mutex);
2925 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
2927 map_write(map, CMD(0xF0), chip->start);
2928 chip->state = FL_SHUTDOWN;
2929 put_chip(map, chip, chip->start);
2932 mutex_unlock(&chip->mutex);
2939 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
2942 struct mtd_info *mtd;
2944 mtd = container_of(nb, struct mtd_info, reboot_notifier);
2945 cfi_amdstd_reset(mtd);
2950 static void cfi_amdstd_destroy(struct mtd_info *mtd)
2952 struct map_info *map = mtd->priv;
2953 struct cfi_private *cfi = map->fldrv_priv;
2955 cfi_amdstd_reset(mtd);
2956 unregister_reboot_notifier(&mtd->reboot_notifier);
2957 kfree(cfi->cmdset_priv);
2960 kfree(mtd->eraseregions);
2963 MODULE_LICENSE("GPL");
2964 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
2965 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
2966 MODULE_ALIAS("cfi_cmdset_0006");
2967 MODULE_ALIAS("cfi_cmdset_0701");