2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
28 #include <asm/byteorder.h>
30 #include <linux/errno.h>
31 #include <linux/slab.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/reboot.h>
36 #include <linux/of_platform.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
47 #define SST49LF004B 0x0060
48 #define SST49LF040B 0x0050
49 #define SST49LF008A 0x005a
50 #define AT49BV6416 0x00d6
52 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
53 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
54 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
55 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
56 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
57 static void cfi_amdstd_sync (struct mtd_info *);
58 static int cfi_amdstd_suspend (struct mtd_info *);
59 static void cfi_amdstd_resume (struct mtd_info *);
60 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
61 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *, size_t,
62 size_t *, struct otp_info *);
63 static int cfi_amdstd_get_user_prot_info(struct mtd_info *, size_t,
64 size_t *, struct otp_info *);
65 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
66 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *, loff_t, size_t,
68 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *, loff_t, size_t,
70 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *, loff_t, size_t,
72 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *, loff_t, size_t);
74 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
75 size_t *retlen, const u_char *buf);
77 static void cfi_amdstd_destroy(struct mtd_info *);
79 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
80 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
82 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
83 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
86 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
87 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
89 static int cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
90 static int cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
91 static int cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
93 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
94 .probe = NULL, /* Not usable directly */
95 .destroy = cfi_amdstd_destroy,
96 .name = "cfi_cmdset_0002",
101 /* #define DEBUG_CFI_FEATURES */
104 #ifdef DEBUG_CFI_FEATURES
105 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
107 const char* erase_suspend[3] = {
108 "Not supported", "Read only", "Read/write"
110 const char* top_bottom[6] = {
111 "No WP", "8x8KiB sectors at top & bottom, no WP",
112 "Bottom boot", "Top boot",
113 "Uniform, Bottom WP", "Uniform, Top WP"
116 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
117 printk(" Address sensitive unlock: %s\n",
118 (extp->SiliconRevision & 1) ? "Not required" : "Required");
120 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
121 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
123 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
125 if (extp->BlkProt == 0)
126 printk(" Block protection: Not supported\n");
128 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
131 printk(" Temporary block unprotect: %s\n",
132 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
133 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
134 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
135 printk(" Burst mode: %s\n",
136 extp->BurstMode ? "Supported" : "Not supported");
137 if (extp->PageMode == 0)
138 printk(" Page mode: Not supported\n");
140 printk(" Page mode: %d word page\n", extp->PageMode << 2);
142 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
143 extp->VppMin >> 4, extp->VppMin & 0xf);
144 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
145 extp->VppMax >> 4, extp->VppMax & 0xf);
147 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
148 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
150 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
154 #ifdef AMD_BOOTLOC_BUG
155 /* Wheee. Bring me the head of someone at AMD. */
156 static void fixup_amd_bootblock(struct mtd_info *mtd)
158 struct map_info *map = mtd->priv;
159 struct cfi_private *cfi = map->fldrv_priv;
160 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
161 __u8 major = extp->MajorVersion;
162 __u8 minor = extp->MinorVersion;
164 if (((major << 8) | minor) < 0x3131) {
165 /* CFI version 1.0 => don't trust bootloc */
167 pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
168 map->name, cfi->mfr, cfi->id);
170 /* AFAICS all 29LV400 with a bottom boot block have a device ID
171 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
172 * These were badly detected as they have the 0x80 bit set
173 * so treat them as a special case.
175 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
177 /* Macronix added CFI to their 2nd generation
178 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
179 * Fujitsu, Spansion, EON, ESI and older Macronix)
182 * Therefore also check the manufacturer.
183 * This reduces the risk of false detection due to
184 * the 8-bit device ID.
186 (cfi->mfr == CFI_MFR_MACRONIX)) {
187 pr_debug("%s: Macronix MX29LV400C with bottom boot block"
188 " detected\n", map->name);
189 extp->TopBottom = 2; /* bottom boot */
191 if (cfi->id & 0x80) {
192 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
193 extp->TopBottom = 3; /* top boot */
195 extp->TopBottom = 2; /* bottom boot */
198 pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;"
199 " deduced %s from Device ID\n", map->name, major, minor,
200 extp->TopBottom == 2 ? "bottom" : "top");
205 static void fixup_use_write_buffers(struct mtd_info *mtd)
207 struct map_info *map = mtd->priv;
208 struct cfi_private *cfi = map->fldrv_priv;
209 if (cfi->cfiq->BufWriteTimeoutTyp) {
210 pr_debug("Using buffer write method\n" );
211 mtd->_write = cfi_amdstd_write_buffers;
215 /* Atmel chips don't use the same PRI format as AMD chips */
216 static void fixup_convert_atmel_pri(struct mtd_info *mtd)
218 struct map_info *map = mtd->priv;
219 struct cfi_private *cfi = map->fldrv_priv;
220 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
221 struct cfi_pri_atmel atmel_pri;
223 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
224 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
226 if (atmel_pri.Features & 0x02)
227 extp->EraseSuspend = 2;
229 /* Some chips got it backwards... */
230 if (cfi->id == AT49BV6416) {
231 if (atmel_pri.BottomBoot)
236 if (atmel_pri.BottomBoot)
242 /* burst write mode not supported */
243 cfi->cfiq->BufWriteTimeoutTyp = 0;
244 cfi->cfiq->BufWriteTimeoutMax = 0;
247 static void fixup_use_secsi(struct mtd_info *mtd)
249 /* Setup for chips with a secsi area */
250 mtd->_read_user_prot_reg = cfi_amdstd_secsi_read;
251 mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read;
254 static void fixup_use_erase_chip(struct mtd_info *mtd)
256 struct map_info *map = mtd->priv;
257 struct cfi_private *cfi = map->fldrv_priv;
258 if ((cfi->cfiq->NumEraseRegions == 1) &&
259 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
260 mtd->_erase = cfi_amdstd_erase_chip;
266 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
269 static void fixup_use_atmel_lock(struct mtd_info *mtd)
271 mtd->_lock = cfi_atmel_lock;
272 mtd->_unlock = cfi_atmel_unlock;
273 mtd->flags |= MTD_POWERUP_LOCK;
276 static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
278 struct map_info *map = mtd->priv;
279 struct cfi_private *cfi = map->fldrv_priv;
282 * These flashes report two separate eraseblock regions based on the
283 * sector_erase-size and block_erase-size, although they both operate on the
284 * same memory. This is not allowed according to CFI, so we just pick the
287 cfi->cfiq->NumEraseRegions = 1;
290 static void fixup_sst39vf(struct mtd_info *mtd)
292 struct map_info *map = mtd->priv;
293 struct cfi_private *cfi = map->fldrv_priv;
295 fixup_old_sst_eraseregion(mtd);
297 cfi->addr_unlock1 = 0x5555;
298 cfi->addr_unlock2 = 0x2AAA;
301 static void fixup_sst39vf_rev_b(struct mtd_info *mtd)
303 struct map_info *map = mtd->priv;
304 struct cfi_private *cfi = map->fldrv_priv;
306 fixup_old_sst_eraseregion(mtd);
308 cfi->addr_unlock1 = 0x555;
309 cfi->addr_unlock2 = 0x2AA;
311 cfi->sector_erase_cmd = CMD(0x50);
314 static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd)
316 struct map_info *map = mtd->priv;
317 struct cfi_private *cfi = map->fldrv_priv;
319 fixup_sst39vf_rev_b(mtd);
322 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where
323 * it should report a size of 8KBytes (0x0020*256).
325 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff;
326 pr_warning("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n", mtd->name);
329 static void fixup_s29gl064n_sectors(struct mtd_info *mtd)
331 struct map_info *map = mtd->priv;
332 struct cfi_private *cfi = map->fldrv_priv;
334 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
335 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
336 pr_warning("%s: Bad S29GL064N CFI data; adjust from 64 to 128 sectors\n", mtd->name);
340 static void fixup_s29gl032n_sectors(struct mtd_info *mtd)
342 struct map_info *map = mtd->priv;
343 struct cfi_private *cfi = map->fldrv_priv;
345 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
346 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
347 pr_warning("%s: Bad S29GL032N CFI data; adjust from 127 to 63 sectors\n", mtd->name);
351 static void fixup_s29ns512p_sectors(struct mtd_info *mtd)
353 struct map_info *map = mtd->priv;
354 struct cfi_private *cfi = map->fldrv_priv;
357 * S29NS512P flash uses more than 8bits to report number of sectors,
358 * which is not permitted by CFI.
360 cfi->cfiq->EraseRegionInfo[0] = 0x020001ff;
361 pr_warning("%s: Bad S29NS512P CFI data; adjust to 512 sectors\n", mtd->name);
364 /* Used to fix CFI-Tables of chips without Extended Query Tables */
365 static struct cfi_fixup cfi_nopri_fixup_table[] = {
366 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */
367 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */
368 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */
369 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */
370 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */
371 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */
372 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */
373 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */
377 static struct cfi_fixup cfi_fixup_table[] = {
378 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri },
379 #ifdef AMD_BOOTLOC_BUG
380 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock },
381 { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock },
382 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock },
384 { CFI_MFR_AMD, 0x0050, fixup_use_secsi },
385 { CFI_MFR_AMD, 0x0053, fixup_use_secsi },
386 { CFI_MFR_AMD, 0x0055, fixup_use_secsi },
387 { CFI_MFR_AMD, 0x0056, fixup_use_secsi },
388 { CFI_MFR_AMD, 0x005C, fixup_use_secsi },
389 { CFI_MFR_AMD, 0x005F, fixup_use_secsi },
390 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors },
391 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors },
392 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors },
393 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors },
394 { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors },
395 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */
396 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */
397 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */
398 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */
399 #if !FORCE_WORD_WRITE
400 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers },
404 static struct cfi_fixup jedec_fixup_table[] = {
405 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock },
406 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock },
407 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock },
411 static struct cfi_fixup fixup_table[] = {
412 /* The CFI vendor ids and the JEDEC vendor IDs appear
413 * to be common. It is like the devices id's are as
414 * well. This table is to pick all cases where
415 * we know that is the case.
417 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip },
418 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock },
423 static void cfi_fixup_major_minor(struct cfi_private *cfi,
424 struct cfi_pri_amdstd *extp)
426 if (cfi->mfr == CFI_MFR_SAMSUNG) {
427 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') ||
428 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) {
430 * Samsung K8P2815UQB and K8D6x16UxM chips
431 * report major=0 / minor=0.
432 * K8D3x16UxC chips report major=3 / minor=3.
434 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu"
435 " Extended Query version to 1.%c\n",
437 extp->MajorVersion = '1';
442 * SST 38VF640x chips report major=0xFF / minor=0xFF.
444 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) {
445 extp->MajorVersion = '1';
446 extp->MinorVersion = '0';
450 static int is_m29ew(struct cfi_private *cfi)
452 if (cfi->mfr == CFI_MFR_INTEL &&
453 ((cfi->device_type == CFI_DEVICETYPE_X8 && (cfi->id & 0xff) == 0x7e) ||
454 (cfi->device_type == CFI_DEVICETYPE_X16 && cfi->id == 0x227e)))
460 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 20:
461 * Some revisions of the M29EW suffer from erase suspend hang ups. In
462 * particular, it can occur when the sequence
463 * Erase Confirm -> Suspend -> Program -> Resume
464 * causes a lockup due to internal timing issues. The consequence is that the
465 * erase cannot be resumed without inserting a dummy command after programming
466 * and prior to resuming. [...] The work-around is to issue a dummy write cycle
467 * that writes an F0 command code before the RESUME command.
469 static void cfi_fixup_m29ew_erase_suspend(struct map_info *map,
472 struct cfi_private *cfi = map->fldrv_priv;
473 /* before resume, insert a dummy 0xF0 cycle for Micron M29EW devices */
475 map_write(map, CMD(0xF0), adr);
479 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 22:
481 * Some revisions of the M29EW (for example, A1 and A2 step revisions)
482 * are affected by a problem that could cause a hang up when an ERASE SUSPEND
483 * command is issued after an ERASE RESUME operation without waiting for a
484 * minimum delay. The result is that once the ERASE seems to be completed
485 * (no bits are toggling), the contents of the Flash memory block on which
486 * the erase was ongoing could be inconsistent with the expected values
487 * (typically, the array value is stuck to the 0xC0, 0xC4, 0x80, or 0x84
488 * values), causing a consequent failure of the ERASE operation.
489 * The occurrence of this issue could be high, especially when file system
490 * operations on the Flash are intensive. As a result, it is recommended
491 * that a patch be applied. Intensive file system operations can cause many
492 * calls to the garbage routine to free Flash space (also by erasing physical
493 * Flash blocks) and as a result, many consecutive SUSPEND and RESUME
494 * commands can occur. The problem disappears when a delay is inserted after
495 * the RESUME command by using the udelay() function available in Linux.
496 * The DELAY value must be tuned based on the customer's platform.
497 * The maximum value that fixes the problem in all cases is 500us.
498 * But, in our experience, a delay of 30 µs to 50 µs is sufficient
500 * We have chosen 500µs because this latency is acceptable.
502 static void cfi_fixup_m29ew_delay_after_resume(struct cfi_private *cfi)
505 * Resolving the Delay After Resume Issue see Micron TN-13-07
506 * Worst case delay must be 500µs but 30-50µs should be ok as well
512 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
514 struct cfi_private *cfi = map->fldrv_priv;
515 struct device_node __maybe_unused *np = map->device_node;
516 struct mtd_info *mtd;
519 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
523 mtd->type = MTD_NORFLASH;
525 /* Fill in the default mtd operations */
526 mtd->_erase = cfi_amdstd_erase_varsize;
527 mtd->_write = cfi_amdstd_write_words;
528 mtd->_read = cfi_amdstd_read;
529 mtd->_sync = cfi_amdstd_sync;
530 mtd->_suspend = cfi_amdstd_suspend;
531 mtd->_resume = cfi_amdstd_resume;
532 mtd->_read_user_prot_reg = cfi_amdstd_read_user_prot_reg;
533 mtd->_read_fact_prot_reg = cfi_amdstd_read_fact_prot_reg;
534 mtd->_get_fact_prot_info = cfi_amdstd_get_fact_prot_info;
535 mtd->_get_user_prot_info = cfi_amdstd_get_user_prot_info;
536 mtd->_write_user_prot_reg = cfi_amdstd_write_user_prot_reg;
537 mtd->_lock_user_prot_reg = cfi_amdstd_lock_user_prot_reg;
538 mtd->flags = MTD_CAP_NORFLASH;
539 mtd->name = map->name;
541 mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
543 pr_debug("MTD %s(): write buffer size %d\n", __func__,
546 mtd->_panic_write = cfi_amdstd_panic_write;
547 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
549 if (cfi->cfi_mode==CFI_MODE_CFI){
550 unsigned char bootloc;
551 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
552 struct cfi_pri_amdstd *extp;
554 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
557 * It's a real CFI chip, not one for which the probe
558 * routine faked a CFI structure.
560 cfi_fixup_major_minor(cfi, extp);
563 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5
564 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19
565 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf
566 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf
567 * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf
569 if (extp->MajorVersion != '1' ||
570 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) {
571 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
572 "version %c.%c (%#02x/%#02x).\n",
573 extp->MajorVersion, extp->MinorVersion,
574 extp->MajorVersion, extp->MinorVersion);
580 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n",
581 extp->MajorVersion, extp->MinorVersion);
583 /* Install our own private info structure */
584 cfi->cmdset_priv = extp;
586 /* Apply cfi device specific fixups */
587 cfi_fixup(mtd, cfi_fixup_table);
589 #ifdef DEBUG_CFI_FEATURES
590 /* Tell the user about it in lots of lovely detail */
591 cfi_tell_features(extp);
595 if (np && of_property_read_bool(
596 np, "use-advanced-sector-protection")
597 && extp->BlkProtUnprot == 8) {
598 printk(KERN_INFO " Advanced Sector Protection (PPB Locking) supported\n");
599 mtd->_lock = cfi_ppb_lock;
600 mtd->_unlock = cfi_ppb_unlock;
601 mtd->_is_locked = cfi_ppb_is_locked;
605 bootloc = extp->TopBottom;
606 if ((bootloc < 2) || (bootloc > 5)) {
607 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
608 "bank location (%d). Assuming bottom.\n",
613 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
614 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
616 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
617 int j = (cfi->cfiq->NumEraseRegions-1)-i;
620 swap = cfi->cfiq->EraseRegionInfo[i];
621 cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j];
622 cfi->cfiq->EraseRegionInfo[j] = swap;
625 /* Set the default CFI lock/unlock addresses */
626 cfi->addr_unlock1 = 0x555;
627 cfi->addr_unlock2 = 0x2aa;
629 cfi_fixup(mtd, cfi_nopri_fixup_table);
631 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
637 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
638 /* Apply jedec specific fixups */
639 cfi_fixup(mtd, jedec_fixup_table);
641 /* Apply generic fixups */
642 cfi_fixup(mtd, fixup_table);
644 for (i=0; i< cfi->numchips; i++) {
645 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
646 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
647 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
649 * First calculate the timeout max according to timeout field
650 * of struct cfi_ident that probed from chip's CFI aera, if
651 * available. Specify a minimum of 2000us, in case the CFI data
654 if (cfi->cfiq->BufWriteTimeoutTyp &&
655 cfi->cfiq->BufWriteTimeoutMax)
656 cfi->chips[i].buffer_write_time_max =
657 1 << (cfi->cfiq->BufWriteTimeoutTyp +
658 cfi->cfiq->BufWriteTimeoutMax);
660 cfi->chips[i].buffer_write_time_max = 0;
662 cfi->chips[i].buffer_write_time_max =
663 max(cfi->chips[i].buffer_write_time_max, 2000);
665 cfi->chips[i].ref_point_counter = 0;
666 init_waitqueue_head(&(cfi->chips[i].wq));
669 map->fldrv = &cfi_amdstd_chipdrv;
671 return cfi_amdstd_setup(mtd);
673 struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
674 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
675 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
676 EXPORT_SYMBOL_GPL(cfi_cmdset_0006);
677 EXPORT_SYMBOL_GPL(cfi_cmdset_0701);
679 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
681 struct map_info *map = mtd->priv;
682 struct cfi_private *cfi = map->fldrv_priv;
683 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
684 unsigned long offset = 0;
687 printk(KERN_NOTICE "number of %s chips: %d\n",
688 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
689 /* Select the correct geometry setup */
690 mtd->size = devsize * cfi->numchips;
692 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
693 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
694 * mtd->numeraseregions, GFP_KERNEL);
695 if (!mtd->eraseregions)
698 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
699 unsigned long ernum, ersize;
700 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
701 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
703 if (mtd->erasesize < ersize) {
704 mtd->erasesize = ersize;
706 for (j=0; j<cfi->numchips; j++) {
707 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
708 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
709 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
711 offset += (ersize * ernum);
713 if (offset != devsize) {
715 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
719 __module_get(THIS_MODULE);
720 register_reboot_notifier(&mtd->reboot_notifier);
724 kfree(mtd->eraseregions);
726 kfree(cfi->cmdset_priv);
731 * Return true if the chip is ready.
733 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
734 * non-suspended sector) and is indicated by no toggle bits toggling.
736 * Note that anything more complicated than checking if no bits are toggling
737 * (including checking DQ5 for an error status) is tricky to get working
738 * correctly and is therefore not done (particularly with interleaved chips
739 * as each chip must be checked independently of the others).
741 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
745 d = map_read(map, addr);
746 t = map_read(map, addr);
748 return map_word_equal(map, d, t);
752 * Return true if the chip is ready and has the correct value.
754 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
755 * non-suspended sector) and it is indicated by no bits toggling.
757 * Error are indicated by toggling bits or bits held with the wrong value,
758 * or with bits toggling.
760 * Note that anything more complicated than checking if no bits are toggling
761 * (including checking DQ5 for an error status) is tricky to get working
762 * correctly and is therefore not done (particularly with interleaved chips
763 * as each chip must be checked independently of the others).
766 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
770 oldd = map_read(map, addr);
771 curd = map_read(map, addr);
773 return map_word_equal(map, oldd, curd) &&
774 map_word_equal(map, curd, expected);
777 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
779 DECLARE_WAITQUEUE(wait, current);
780 struct cfi_private *cfi = map->fldrv_priv;
782 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
785 timeo = jiffies + HZ;
787 switch (chip->state) {
791 if (chip_ready(map, adr))
794 if (time_after(jiffies, timeo)) {
795 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
798 mutex_unlock(&chip->mutex);
800 mutex_lock(&chip->mutex);
801 /* Someone else might have been playing with it. */
811 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
812 !(mode == FL_READY || mode == FL_POINT ||
813 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
816 /* Do not allow suspend iff read/write to EB address */
817 if ((adr & chip->in_progress_block_mask) ==
818 chip->in_progress_block_addr)
822 /* It's harmless to issue the Erase-Suspend and Erase-Resume
823 * commands when the erase algorithm isn't in progress. */
824 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
825 chip->oldstate = FL_ERASING;
826 chip->state = FL_ERASE_SUSPENDING;
827 chip->erase_suspended = 1;
829 if (chip_ready(map, adr))
832 if (time_after(jiffies, timeo)) {
833 /* Should have suspended the erase by now.
834 * Send an Erase-Resume command as either
835 * there was an error (so leave the erase
836 * routine to recover from it) or we trying to
837 * use the erase-in-progress sector. */
838 put_chip(map, chip, adr);
839 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
843 mutex_unlock(&chip->mutex);
845 mutex_lock(&chip->mutex);
846 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
847 So we can just loop here. */
849 chip->state = FL_READY;
852 case FL_XIP_WHILE_ERASING:
853 if (mode != FL_READY && mode != FL_POINT &&
854 (!cfip || !(cfip->EraseSuspend&2)))
856 chip->oldstate = chip->state;
857 chip->state = FL_READY;
861 /* The machine is rebooting */
865 /* Only if there's no operation suspended... */
866 if (mode == FL_READY && chip->oldstate == FL_READY)
871 set_current_state(TASK_UNINTERRUPTIBLE);
872 add_wait_queue(&chip->wq, &wait);
873 mutex_unlock(&chip->mutex);
875 remove_wait_queue(&chip->wq, &wait);
876 mutex_lock(&chip->mutex);
882 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
884 struct cfi_private *cfi = map->fldrv_priv;
886 switch(chip->oldstate) {
888 cfi_fixup_m29ew_erase_suspend(map,
889 chip->in_progress_block_addr);
890 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
891 cfi_fixup_m29ew_delay_after_resume(cfi);
892 chip->oldstate = FL_READY;
893 chip->state = FL_ERASING;
896 case FL_XIP_WHILE_ERASING:
897 chip->state = chip->oldstate;
898 chip->oldstate = FL_READY;
905 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
910 #ifdef CONFIG_MTD_XIP
913 * No interrupt what so ever can be serviced while the flash isn't in array
914 * mode. This is ensured by the xip_disable() and xip_enable() functions
915 * enclosing any code path where the flash is known not to be in array mode.
916 * And within a XIP disabled code path, only functions marked with __xipram
917 * may be called and nothing else (it's a good thing to inspect generated
918 * assembly to make sure inline functions were actually inlined and that gcc
919 * didn't emit calls to its own support functions). Also configuring MTD CFI
920 * support to a single buswidth and a single interleave is also recommended.
923 static void xip_disable(struct map_info *map, struct flchip *chip,
926 /* TODO: chips with no XIP use should ignore and return */
927 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
931 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
934 struct cfi_private *cfi = map->fldrv_priv;
936 if (chip->state != FL_POINT && chip->state != FL_READY) {
937 map_write(map, CMD(0xf0), adr);
938 chip->state = FL_READY;
940 (void) map_read(map, adr);
946 * When a delay is required for the flash operation to complete, the
947 * xip_udelay() function is polling for both the given timeout and pending
948 * (but still masked) hardware interrupts. Whenever there is an interrupt
949 * pending then the flash erase operation is suspended, array mode restored
950 * and interrupts unmasked. Task scheduling might also happen at that
951 * point. The CPU eventually returns from the interrupt or the call to
952 * schedule() and the suspended flash operation is resumed for the remaining
953 * of the delay period.
955 * Warning: this function _will_ fool interrupt latency tracing tools.
958 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
959 unsigned long adr, int usec)
961 struct cfi_private *cfi = map->fldrv_priv;
962 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
963 map_word status, OK = CMD(0x80);
964 unsigned long suspended, start = xip_currtime();
969 if (xip_irqpending() && extp &&
970 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
971 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
973 * Let's suspend the erase operation when supported.
974 * Note that we currently don't try to suspend
975 * interleaved chips if there is already another
976 * operation suspended (imagine what happens
977 * when one chip was already done with the current
978 * operation while another chip suspended it, then
979 * we resume the whole thing at once). Yes, it
982 map_write(map, CMD(0xb0), adr);
983 usec -= xip_elapsed_since(start);
984 suspended = xip_currtime();
986 if (xip_elapsed_since(suspended) > 100000) {
988 * The chip doesn't want to suspend
989 * after waiting for 100 msecs.
990 * This is a critical error but there
991 * is not much we can do here.
995 status = map_read(map, adr);
996 } while (!map_word_andequal(map, status, OK, OK));
998 /* Suspend succeeded */
999 oldstate = chip->state;
1000 if (!map_word_bitsset(map, status, CMD(0x40)))
1002 chip->state = FL_XIP_WHILE_ERASING;
1003 chip->erase_suspended = 1;
1004 map_write(map, CMD(0xf0), adr);
1005 (void) map_read(map, adr);
1008 mutex_unlock(&chip->mutex);
1013 * We're back. However someone else might have
1014 * decided to go write to the chip if we are in
1015 * a suspended erase state. If so let's wait
1018 mutex_lock(&chip->mutex);
1019 while (chip->state != FL_XIP_WHILE_ERASING) {
1020 DECLARE_WAITQUEUE(wait, current);
1021 set_current_state(TASK_UNINTERRUPTIBLE);
1022 add_wait_queue(&chip->wq, &wait);
1023 mutex_unlock(&chip->mutex);
1025 remove_wait_queue(&chip->wq, &wait);
1026 mutex_lock(&chip->mutex);
1028 /* Disallow XIP again */
1029 local_irq_disable();
1031 /* Correct Erase Suspend Hangups for M29EW */
1032 cfi_fixup_m29ew_erase_suspend(map, adr);
1033 /* Resume the write or erase operation */
1034 map_write(map, cfi->sector_erase_cmd, adr);
1035 chip->state = oldstate;
1036 start = xip_currtime();
1037 } else if (usec >= 1000000/HZ) {
1039 * Try to save on CPU power when waiting delay
1040 * is at least a system timer tick period.
1041 * No need to be extremely accurate here.
1045 status = map_read(map, adr);
1046 } while (!map_word_andequal(map, status, OK, OK)
1047 && xip_elapsed_since(start) < usec);
1050 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
1053 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
1054 * the flash is actively programming or erasing since we have to poll for
1055 * the operation to complete anyway. We can't do that in a generic way with
1056 * a XIP setup so do it before the actual flash operation in this case
1057 * and stub it out from INVALIDATE_CACHE_UDELAY.
1059 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
1060 INVALIDATE_CACHED_RANGE(map, from, size)
1062 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1063 UDELAY(map, chip, adr, usec)
1068 * Activating this XIP support changes the way the code works a bit. For
1069 * example the code to suspend the current process when concurrent access
1070 * happens is never executed because xip_udelay() will always return with the
1071 * same chip state as it was entered with. This is why there is no care for
1072 * the presence of add_wait_queue() or schedule() calls from within a couple
1073 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
1074 * The queueing and scheduling are always happening within xip_udelay().
1076 * Similarly, get_chip() and put_chip() just happen to always be executed
1077 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
1078 * is in array mode, therefore never executing many cases therein and not
1079 * causing any problem with XIP.
1084 #define xip_disable(map, chip, adr)
1085 #define xip_enable(map, chip, adr)
1086 #define XIP_INVAL_CACHED_RANGE(x...)
1088 #define UDELAY(map, chip, adr, usec) \
1090 mutex_unlock(&chip->mutex); \
1092 mutex_lock(&chip->mutex); \
1095 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1097 mutex_unlock(&chip->mutex); \
1098 INVALIDATE_CACHED_RANGE(map, adr, len); \
1100 mutex_lock(&chip->mutex); \
1105 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1107 unsigned long cmd_addr;
1108 struct cfi_private *cfi = map->fldrv_priv;
1113 /* Ensure cmd read/writes are aligned. */
1114 cmd_addr = adr & ~(map_bankwidth(map)-1);
1116 mutex_lock(&chip->mutex);
1117 ret = get_chip(map, chip, cmd_addr, FL_READY);
1119 mutex_unlock(&chip->mutex);
1123 if (chip->state != FL_POINT && chip->state != FL_READY) {
1124 map_write(map, CMD(0xf0), cmd_addr);
1125 chip->state = FL_READY;
1128 map_copy_from(map, buf, adr, len);
1130 put_chip(map, chip, cmd_addr);
1132 mutex_unlock(&chip->mutex);
1137 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1139 struct map_info *map = mtd->priv;
1140 struct cfi_private *cfi = map->fldrv_priv;
1145 /* ofs: offset within the first chip that the first read should start */
1146 chipnum = (from >> cfi->chipshift);
1147 ofs = from - (chipnum << cfi->chipshift);
1150 unsigned long thislen;
1152 if (chipnum >= cfi->numchips)
1155 if ((len + ofs -1) >> cfi->chipshift)
1156 thislen = (1<<cfi->chipshift) - ofs;
1160 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1174 typedef int (*otp_op_t)(struct map_info *map, struct flchip *chip,
1175 loff_t adr, size_t len, u_char *buf, size_t grouplen);
1177 static inline void otp_enter(struct map_info *map, struct flchip *chip,
1178 loff_t adr, size_t len)
1180 struct cfi_private *cfi = map->fldrv_priv;
1182 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1183 cfi->device_type, NULL);
1184 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1185 cfi->device_type, NULL);
1186 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi,
1187 cfi->device_type, NULL);
1189 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1192 static inline void otp_exit(struct map_info *map, struct flchip *chip,
1193 loff_t adr, size_t len)
1195 struct cfi_private *cfi = map->fldrv_priv;
1197 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1198 cfi->device_type, NULL);
1199 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1200 cfi->device_type, NULL);
1201 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi,
1202 cfi->device_type, NULL);
1203 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi,
1204 cfi->device_type, NULL);
1206 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1209 static inline int do_read_secsi_onechip(struct map_info *map,
1210 struct flchip *chip, loff_t adr,
1211 size_t len, u_char *buf,
1214 DECLARE_WAITQUEUE(wait, current);
1215 unsigned long timeo = jiffies + HZ;
1218 mutex_lock(&chip->mutex);
1220 if (chip->state != FL_READY){
1221 set_current_state(TASK_UNINTERRUPTIBLE);
1222 add_wait_queue(&chip->wq, &wait);
1224 mutex_unlock(&chip->mutex);
1227 remove_wait_queue(&chip->wq, &wait);
1228 timeo = jiffies + HZ;
1235 chip->state = FL_READY;
1237 otp_enter(map, chip, adr, len);
1238 map_copy_from(map, buf, adr, len);
1239 otp_exit(map, chip, adr, len);
1242 mutex_unlock(&chip->mutex);
1247 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1249 struct map_info *map = mtd->priv;
1250 struct cfi_private *cfi = map->fldrv_priv;
1255 /* ofs: offset within the first chip that the first read should start */
1256 /* 8 secsi bytes per chip */
1261 unsigned long thislen;
1263 if (chipnum >= cfi->numchips)
1266 if ((len + ofs -1) >> 3)
1267 thislen = (1<<3) - ofs;
1271 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs,
1286 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1287 unsigned long adr, map_word datum,
1290 static int do_otp_write(struct map_info *map, struct flchip *chip, loff_t adr,
1291 size_t len, u_char *buf, size_t grouplen)
1295 unsigned long bus_ofs = adr & ~(map_bankwidth(map)-1);
1296 int gap = adr - bus_ofs;
1297 int n = min_t(int, len, map_bankwidth(map) - gap);
1298 map_word datum = map_word_ff(map);
1300 if (n != map_bankwidth(map)) {
1301 /* partial write of a word, load old contents */
1302 otp_enter(map, chip, bus_ofs, map_bankwidth(map));
1303 datum = map_read(map, bus_ofs);
1304 otp_exit(map, chip, bus_ofs, map_bankwidth(map));
1307 datum = map_word_load_partial(map, datum, buf, gap, n);
1308 ret = do_write_oneword(map, chip, bus_ofs, datum, FL_OTP_WRITE);
1320 static int do_otp_lock(struct map_info *map, struct flchip *chip, loff_t adr,
1321 size_t len, u_char *buf, size_t grouplen)
1323 struct cfi_private *cfi = map->fldrv_priv;
1325 unsigned long timeo;
1328 /* make sure area matches group boundaries */
1329 if ((adr != 0) || (len != grouplen))
1332 mutex_lock(&chip->mutex);
1333 ret = get_chip(map, chip, chip->start, FL_LOCKING);
1335 mutex_unlock(&chip->mutex);
1338 chip->state = FL_LOCKING;
1340 /* Enter lock register command */
1341 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1342 cfi->device_type, NULL);
1343 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1344 cfi->device_type, NULL);
1345 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi,
1346 cfi->device_type, NULL);
1348 /* read lock register */
1349 lockreg = cfi_read_query(map, 0);
1351 /* set bit 0 to protect extended memory block */
1354 /* set bit 0 to protect extended memory block */
1355 /* write lock register */
1356 map_write(map, CMD(0xA0), chip->start);
1357 map_write(map, CMD(lockreg), chip->start);
1359 /* wait for chip to become ready */
1360 timeo = jiffies + msecs_to_jiffies(2);
1362 if (chip_ready(map, adr))
1365 if (time_after(jiffies, timeo)) {
1366 pr_err("Waiting for chip to be ready timed out.\n");
1370 UDELAY(map, chip, 0, 1);
1373 /* exit protection commands */
1374 map_write(map, CMD(0x90), chip->start);
1375 map_write(map, CMD(0x00), chip->start);
1377 chip->state = FL_READY;
1378 put_chip(map, chip, chip->start);
1379 mutex_unlock(&chip->mutex);
1384 static int cfi_amdstd_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
1385 size_t *retlen, u_char *buf,
1386 otp_op_t action, int user_regs)
1388 struct map_info *map = mtd->priv;
1389 struct cfi_private *cfi = map->fldrv_priv;
1390 int ofs_factor = cfi->interleave * cfi->device_type;
1393 struct flchip *chip;
1394 uint8_t otp, lockreg;
1397 size_t user_size, factory_size, otpsize;
1398 loff_t user_offset, factory_offset, otpoffset;
1399 int user_locked = 0, otplocked;
1403 for (chipnum = 0; chipnum < cfi->numchips; chipnum++) {
1404 chip = &cfi->chips[chipnum];
1408 /* Micron M29EW family */
1409 if (is_m29ew(cfi)) {
1412 /* check whether secsi area is factory locked
1414 mutex_lock(&chip->mutex);
1415 ret = get_chip(map, chip, base, FL_CFI_QUERY);
1417 mutex_unlock(&chip->mutex);
1420 cfi_qry_mode_on(base, map, cfi);
1421 otp = cfi_read_query(map, base + 0x3 * ofs_factor);
1422 cfi_qry_mode_off(base, map, cfi);
1423 put_chip(map, chip, base);
1424 mutex_unlock(&chip->mutex);
1427 /* factory locked */
1429 factory_size = 0x100;
1431 /* customer lockable */
1435 mutex_lock(&chip->mutex);
1436 ret = get_chip(map, chip, base, FL_LOCKING);
1438 mutex_unlock(&chip->mutex);
1442 /* Enter lock register command */
1443 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1,
1444 chip->start, map, cfi,
1445 cfi->device_type, NULL);
1446 cfi_send_gen_cmd(0x55, cfi->addr_unlock2,
1447 chip->start, map, cfi,
1448 cfi->device_type, NULL);
1449 cfi_send_gen_cmd(0x40, cfi->addr_unlock1,
1450 chip->start, map, cfi,
1451 cfi->device_type, NULL);
1452 /* read lock register */
1453 lockreg = cfi_read_query(map, 0);
1454 /* exit protection commands */
1455 map_write(map, CMD(0x90), chip->start);
1456 map_write(map, CMD(0x00), chip->start);
1457 put_chip(map, chip, chip->start);
1458 mutex_unlock(&chip->mutex);
1460 user_locked = ((lockreg & 0x01) == 0x00);
1464 otpsize = user_regs ? user_size : factory_size;
1467 otpoffset = user_regs ? user_offset : factory_offset;
1468 otplocked = user_regs ? user_locked : 1;
1471 /* return otpinfo */
1472 struct otp_info *otpinfo;
1473 len -= sizeof(*otpinfo);
1476 otpinfo = (struct otp_info *)buf;
1477 otpinfo->start = from;
1478 otpinfo->length = otpsize;
1479 otpinfo->locked = otplocked;
1480 buf += sizeof(*otpinfo);
1481 *retlen += sizeof(*otpinfo);
1483 } else if ((from < otpsize) && (len > 0)) {
1485 size = (len < otpsize - from) ? len : otpsize - from;
1486 ret = action(map, chip, otpoffset + from, size, buf,
1502 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *mtd, size_t len,
1503 size_t *retlen, struct otp_info *buf)
1505 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1509 static int cfi_amdstd_get_user_prot_info(struct mtd_info *mtd, size_t len,
1510 size_t *retlen, struct otp_info *buf)
1512 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1516 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
1517 size_t len, size_t *retlen,
1520 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1521 buf, do_read_secsi_onechip, 0);
1524 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
1525 size_t len, size_t *retlen,
1528 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1529 buf, do_read_secsi_onechip, 1);
1532 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
1533 size_t len, size_t *retlen,
1536 return cfi_amdstd_otp_walk(mtd, from, len, retlen, buf,
1540 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
1544 return cfi_amdstd_otp_walk(mtd, from, len, &retlen, NULL,
1548 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1549 unsigned long adr, map_word datum,
1552 struct cfi_private *cfi = map->fldrv_priv;
1553 unsigned long timeo = jiffies + HZ;
1555 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1556 * have a max write time of a few hundreds usec). However, we should
1557 * use the maximum timeout value given by the chip at probe time
1558 * instead. Unfortunately, struct flchip does have a field for
1559 * maximum timeout, only for typical which can be far too short
1560 * depending of the conditions. The ' + 1' is to avoid having a
1561 * timeout of 0 jiffies if HZ is smaller than 1000.
1563 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1570 mutex_lock(&chip->mutex);
1571 ret = get_chip(map, chip, adr, mode);
1573 mutex_unlock(&chip->mutex);
1577 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1578 __func__, adr, datum.x[0] );
1580 if (mode == FL_OTP_WRITE)
1581 otp_enter(map, chip, adr, map_bankwidth(map));
1584 * Check for a NOP for the case when the datum to write is already
1585 * present - it saves time and works around buggy chips that corrupt
1586 * data at other locations when 0xff is written to a location that
1587 * already contains 0xff.
1589 oldd = map_read(map, adr);
1590 if (map_word_equal(map, oldd, datum)) {
1591 pr_debug("MTD %s(): NOP\n",
1596 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1598 xip_disable(map, chip, adr);
1601 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1602 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1603 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1604 map_write(map, datum, adr);
1607 INVALIDATE_CACHE_UDELAY(map, chip,
1608 adr, map_bankwidth(map),
1609 chip->word_write_time);
1611 /* See comment above for timeout value. */
1612 timeo = jiffies + uWriteTimeout;
1614 if (chip->state != mode) {
1615 /* Someone's suspended the write. Sleep */
1616 DECLARE_WAITQUEUE(wait, current);
1618 set_current_state(TASK_UNINTERRUPTIBLE);
1619 add_wait_queue(&chip->wq, &wait);
1620 mutex_unlock(&chip->mutex);
1622 remove_wait_queue(&chip->wq, &wait);
1623 timeo = jiffies + (HZ / 2); /* FIXME */
1624 mutex_lock(&chip->mutex);
1629 * We check "time_after" and "!chip_good" before checking
1630 * "chip_good" to avoid the failure due to scheduling.
1632 if (time_after(jiffies, timeo) && !chip_good(map, adr, datum)) {
1633 xip_enable(map, chip, adr);
1634 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1635 xip_disable(map, chip, adr);
1640 if (chip_good(map, adr, datum))
1643 /* Latency issues. Drop the lock, wait a while and retry */
1644 UDELAY(map, chip, adr, 1);
1647 /* Did we succeed? */
1649 /* reset on all failures. */
1650 map_write( map, CMD(0xF0), chip->start );
1651 /* FIXME - should have reset delay before continuing */
1653 if (++retry_cnt <= MAX_RETRIES) {
1658 xip_enable(map, chip, adr);
1660 if (mode == FL_OTP_WRITE)
1661 otp_exit(map, chip, adr, map_bankwidth(map));
1662 chip->state = FL_READY;
1664 put_chip(map, chip, adr);
1665 mutex_unlock(&chip->mutex);
1671 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1672 size_t *retlen, const u_char *buf)
1674 struct map_info *map = mtd->priv;
1675 struct cfi_private *cfi = map->fldrv_priv;
1678 unsigned long ofs, chipstart;
1679 DECLARE_WAITQUEUE(wait, current);
1681 chipnum = to >> cfi->chipshift;
1682 ofs = to - (chipnum << cfi->chipshift);
1683 chipstart = cfi->chips[chipnum].start;
1685 /* If it's not bus-aligned, do the first byte write */
1686 if (ofs & (map_bankwidth(map)-1)) {
1687 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1688 int i = ofs - bus_ofs;
1693 mutex_lock(&cfi->chips[chipnum].mutex);
1695 if (cfi->chips[chipnum].state != FL_READY) {
1696 set_current_state(TASK_UNINTERRUPTIBLE);
1697 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1699 mutex_unlock(&cfi->chips[chipnum].mutex);
1702 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1706 /* Load 'tmp_buf' with old contents of flash */
1707 tmp_buf = map_read(map, bus_ofs+chipstart);
1709 mutex_unlock(&cfi->chips[chipnum].mutex);
1711 /* Number of bytes to copy from buffer */
1712 n = min_t(int, len, map_bankwidth(map)-i);
1714 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1716 ret = do_write_oneword(map, &cfi->chips[chipnum],
1717 bus_ofs, tmp_buf, FL_WRITING);
1726 if (ofs >> cfi->chipshift) {
1729 if (chipnum == cfi->numchips)
1734 /* We are now aligned, write as much as possible */
1735 while(len >= map_bankwidth(map)) {
1738 datum = map_word_load(map, buf);
1740 ret = do_write_oneword(map, &cfi->chips[chipnum],
1741 ofs, datum, FL_WRITING);
1745 ofs += map_bankwidth(map);
1746 buf += map_bankwidth(map);
1747 (*retlen) += map_bankwidth(map);
1748 len -= map_bankwidth(map);
1750 if (ofs >> cfi->chipshift) {
1753 if (chipnum == cfi->numchips)
1755 chipstart = cfi->chips[chipnum].start;
1759 /* Write the trailing bytes if any */
1760 if (len & (map_bankwidth(map)-1)) {
1764 mutex_lock(&cfi->chips[chipnum].mutex);
1766 if (cfi->chips[chipnum].state != FL_READY) {
1767 set_current_state(TASK_UNINTERRUPTIBLE);
1768 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1770 mutex_unlock(&cfi->chips[chipnum].mutex);
1773 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1777 tmp_buf = map_read(map, ofs + chipstart);
1779 mutex_unlock(&cfi->chips[chipnum].mutex);
1781 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1783 ret = do_write_oneword(map, &cfi->chips[chipnum],
1784 ofs, tmp_buf, FL_WRITING);
1796 * FIXME: interleaved mode not tested, and probably not supported!
1798 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1799 unsigned long adr, const u_char *buf,
1802 struct cfi_private *cfi = map->fldrv_priv;
1803 unsigned long timeo = jiffies + HZ;
1805 * Timeout is calculated according to CFI data, if available.
1806 * See more comments in cfi_cmdset_0002().
1808 unsigned long uWriteTimeout =
1809 usecs_to_jiffies(chip->buffer_write_time_max);
1811 unsigned long cmd_adr;
1818 mutex_lock(&chip->mutex);
1819 ret = get_chip(map, chip, adr, FL_WRITING);
1821 mutex_unlock(&chip->mutex);
1825 datum = map_word_load(map, buf);
1827 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1828 __func__, adr, datum.x[0] );
1830 XIP_INVAL_CACHED_RANGE(map, adr, len);
1832 xip_disable(map, chip, cmd_adr);
1834 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1835 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1837 /* Write Buffer Load */
1838 map_write(map, CMD(0x25), cmd_adr);
1840 chip->state = FL_WRITING_TO_BUFFER;
1842 /* Write length of data to come */
1843 words = len / map_bankwidth(map);
1844 map_write(map, CMD(words - 1), cmd_adr);
1847 while(z < words * map_bankwidth(map)) {
1848 datum = map_word_load(map, buf);
1849 map_write(map, datum, adr + z);
1851 z += map_bankwidth(map);
1852 buf += map_bankwidth(map);
1854 z -= map_bankwidth(map);
1858 /* Write Buffer Program Confirm: GO GO GO */
1859 map_write(map, CMD(0x29), cmd_adr);
1860 chip->state = FL_WRITING;
1862 INVALIDATE_CACHE_UDELAY(map, chip,
1863 adr, map_bankwidth(map),
1864 chip->word_write_time);
1866 timeo = jiffies + uWriteTimeout;
1869 if (chip->state != FL_WRITING) {
1870 /* Someone's suspended the write. Sleep */
1871 DECLARE_WAITQUEUE(wait, current);
1873 set_current_state(TASK_UNINTERRUPTIBLE);
1874 add_wait_queue(&chip->wq, &wait);
1875 mutex_unlock(&chip->mutex);
1877 remove_wait_queue(&chip->wq, &wait);
1878 timeo = jiffies + (HZ / 2); /* FIXME */
1879 mutex_lock(&chip->mutex);
1884 * We check "time_after" and "!chip_good" before checking "chip_good" to avoid
1885 * the failure due to scheduling.
1887 if (time_after(jiffies, timeo) && !chip_good(map, adr, datum))
1890 if (chip_good(map, adr, datum)) {
1891 xip_enable(map, chip, adr);
1895 /* Latency issues. Drop the lock, wait a while and retry */
1896 UDELAY(map, chip, adr, 1);
1900 * Recovery from write-buffer programming failures requires
1901 * the write-to-buffer-reset sequence. Since the last part
1902 * of the sequence also works as a normal reset, we can run
1903 * the same commands regardless of why we are here.
1905 * http://www.spansion.com/Support/Application%20Notes/MirrorBit_Write_Buffer_Prog_Page_Buffer_Read_AN.pdf
1907 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1908 cfi->device_type, NULL);
1909 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1910 cfi->device_type, NULL);
1911 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi,
1912 cfi->device_type, NULL);
1913 xip_enable(map, chip, adr);
1914 /* FIXME - should have reset delay before continuing */
1916 printk(KERN_WARNING "MTD %s(): software timeout, address:0x%.8lx.\n",
1921 chip->state = FL_READY;
1923 put_chip(map, chip, adr);
1924 mutex_unlock(&chip->mutex);
1930 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1931 size_t *retlen, const u_char *buf)
1933 struct map_info *map = mtd->priv;
1934 struct cfi_private *cfi = map->fldrv_priv;
1935 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1940 chipnum = to >> cfi->chipshift;
1941 ofs = to - (chipnum << cfi->chipshift);
1943 /* If it's not bus-aligned, do the first word write */
1944 if (ofs & (map_bankwidth(map)-1)) {
1945 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1946 if (local_len > len)
1948 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1949 local_len, retlen, buf);
1956 if (ofs >> cfi->chipshift) {
1959 if (chipnum == cfi->numchips)
1964 /* Write buffer is worth it only if more than one word to write... */
1965 while (len >= map_bankwidth(map) * 2) {
1966 /* We must not cross write block boundaries */
1967 int size = wbufsize - (ofs & (wbufsize-1));
1971 if (size % map_bankwidth(map))
1972 size -= size % map_bankwidth(map);
1974 ret = do_write_buffer(map, &cfi->chips[chipnum],
1984 if (ofs >> cfi->chipshift) {
1987 if (chipnum == cfi->numchips)
1993 size_t retlen_dregs = 0;
1995 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1996 len, &retlen_dregs, buf);
1998 *retlen += retlen_dregs;
2006 * Wait for the flash chip to become ready to write data
2008 * This is only called during the panic_write() path. When panic_write()
2009 * is called, the kernel is in the process of a panic, and will soon be
2010 * dead. Therefore we don't take any locks, and attempt to get access
2011 * to the chip as soon as possible.
2013 static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip,
2016 struct cfi_private *cfi = map->fldrv_priv;
2021 * If the driver thinks the chip is idle, and no toggle bits
2022 * are changing, then the chip is actually idle for sure.
2024 if (chip->state == FL_READY && chip_ready(map, adr))
2028 * Try several times to reset the chip and then wait for it
2029 * to become idle. The upper limit of a few milliseconds of
2030 * delay isn't a big problem: the kernel is dying anyway. It
2031 * is more important to save the messages.
2033 while (retries > 0) {
2034 const unsigned long timeo = (HZ / 1000) + 1;
2036 /* send the reset command */
2037 map_write(map, CMD(0xF0), chip->start);
2039 /* wait for the chip to become ready */
2040 for (i = 0; i < jiffies_to_usecs(timeo); i++) {
2041 if (chip_ready(map, adr))
2050 /* the chip never became ready */
2055 * Write out one word of data to a single flash chip during a kernel panic
2057 * This is only called during the panic_write() path. When panic_write()
2058 * is called, the kernel is in the process of a panic, and will soon be
2059 * dead. Therefore we don't take any locks, and attempt to get access
2060 * to the chip as soon as possible.
2062 * The implementation of this routine is intentionally similar to
2063 * do_write_oneword(), in order to ease code maintenance.
2065 static int do_panic_write_oneword(struct map_info *map, struct flchip *chip,
2066 unsigned long adr, map_word datum)
2068 const unsigned long uWriteTimeout = (HZ / 1000) + 1;
2069 struct cfi_private *cfi = map->fldrv_priv;
2077 ret = cfi_amdstd_panic_wait(map, chip, adr);
2081 pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n",
2082 __func__, adr, datum.x[0]);
2085 * Check for a NOP for the case when the datum to write is already
2086 * present - it saves time and works around buggy chips that corrupt
2087 * data at other locations when 0xff is written to a location that
2088 * already contains 0xff.
2090 oldd = map_read(map, adr);
2091 if (map_word_equal(map, oldd, datum)) {
2092 pr_debug("MTD %s(): NOP\n", __func__);
2099 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2100 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2101 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2102 map_write(map, datum, adr);
2104 for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) {
2105 if (chip_ready(map, adr))
2111 if (!chip_good(map, adr, datum)) {
2112 /* reset on all failures. */
2113 map_write(map, CMD(0xF0), chip->start);
2114 /* FIXME - should have reset delay before continuing */
2116 if (++retry_cnt <= MAX_RETRIES)
2128 * Write out some data during a kernel panic
2130 * This is used by the mtdoops driver to save the dying messages from a
2131 * kernel which has panic'd.
2133 * This routine ignores all of the locking used throughout the rest of the
2134 * driver, in order to ensure that the data gets written out no matter what
2135 * state this driver (and the flash chip itself) was in when the kernel crashed.
2137 * The implementation of this routine is intentionally similar to
2138 * cfi_amdstd_write_words(), in order to ease code maintenance.
2140 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
2141 size_t *retlen, const u_char *buf)
2143 struct map_info *map = mtd->priv;
2144 struct cfi_private *cfi = map->fldrv_priv;
2145 unsigned long ofs, chipstart;
2149 chipnum = to >> cfi->chipshift;
2150 ofs = to - (chipnum << cfi->chipshift);
2151 chipstart = cfi->chips[chipnum].start;
2153 /* If it's not bus aligned, do the first byte write */
2154 if (ofs & (map_bankwidth(map) - 1)) {
2155 unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1);
2156 int i = ofs - bus_ofs;
2160 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs);
2164 /* Load 'tmp_buf' with old contents of flash */
2165 tmp_buf = map_read(map, bus_ofs + chipstart);
2167 /* Number of bytes to copy from buffer */
2168 n = min_t(int, len, map_bankwidth(map) - i);
2170 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
2172 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2182 if (ofs >> cfi->chipshift) {
2185 if (chipnum == cfi->numchips)
2190 /* We are now aligned, write as much as possible */
2191 while (len >= map_bankwidth(map)) {
2194 datum = map_word_load(map, buf);
2196 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2201 ofs += map_bankwidth(map);
2202 buf += map_bankwidth(map);
2203 (*retlen) += map_bankwidth(map);
2204 len -= map_bankwidth(map);
2206 if (ofs >> cfi->chipshift) {
2209 if (chipnum == cfi->numchips)
2212 chipstart = cfi->chips[chipnum].start;
2216 /* Write the trailing bytes if any */
2217 if (len & (map_bankwidth(map) - 1)) {
2220 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs);
2224 tmp_buf = map_read(map, ofs + chipstart);
2226 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
2228 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2241 * Handle devices with one erase region, that only implement
2242 * the chip erase command.
2244 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
2246 struct cfi_private *cfi = map->fldrv_priv;
2247 unsigned long timeo = jiffies + HZ;
2248 unsigned long int adr;
2249 DECLARE_WAITQUEUE(wait, current);
2253 adr = cfi->addr_unlock1;
2255 mutex_lock(&chip->mutex);
2256 ret = get_chip(map, chip, adr, FL_WRITING);
2258 mutex_unlock(&chip->mutex);
2262 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2263 __func__, chip->start );
2265 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
2267 xip_disable(map, chip, adr);
2270 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2271 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2272 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2273 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2274 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2275 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2277 chip->state = FL_ERASING;
2278 chip->erase_suspended = 0;
2279 chip->in_progress_block_addr = adr;
2280 chip->in_progress_block_mask = ~(map->size - 1);
2282 INVALIDATE_CACHE_UDELAY(map, chip,
2284 chip->erase_time*500);
2286 timeo = jiffies + (HZ*20);
2289 if (chip->state != FL_ERASING) {
2290 /* Someone's suspended the erase. Sleep */
2291 set_current_state(TASK_UNINTERRUPTIBLE);
2292 add_wait_queue(&chip->wq, &wait);
2293 mutex_unlock(&chip->mutex);
2295 remove_wait_queue(&chip->wq, &wait);
2296 mutex_lock(&chip->mutex);
2299 if (chip->erase_suspended) {
2300 /* This erase was suspended and resumed.
2301 Adjust the timeout */
2302 timeo = jiffies + (HZ*20); /* FIXME */
2303 chip->erase_suspended = 0;
2306 if (chip_good(map, adr, map_word_ff(map)))
2309 if (time_after(jiffies, timeo)) {
2310 printk(KERN_WARNING "MTD %s(): software timeout\n",
2316 /* Latency issues. Drop the lock, wait a while and retry */
2317 UDELAY(map, chip, adr, 1000000/HZ);
2319 /* Did we succeed? */
2321 /* reset on all failures. */
2322 map_write( map, CMD(0xF0), chip->start );
2323 /* FIXME - should have reset delay before continuing */
2325 if (++retry_cnt <= MAX_RETRIES) {
2331 chip->state = FL_READY;
2332 xip_enable(map, chip, adr);
2334 put_chip(map, chip, adr);
2335 mutex_unlock(&chip->mutex);
2341 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
2343 struct cfi_private *cfi = map->fldrv_priv;
2344 unsigned long timeo = jiffies + HZ;
2345 DECLARE_WAITQUEUE(wait, current);
2351 mutex_lock(&chip->mutex);
2352 ret = get_chip(map, chip, adr, FL_ERASING);
2354 mutex_unlock(&chip->mutex);
2358 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2361 XIP_INVAL_CACHED_RANGE(map, adr, len);
2363 xip_disable(map, chip, adr);
2366 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2367 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2368 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2369 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2370 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2371 map_write(map, cfi->sector_erase_cmd, adr);
2373 chip->state = FL_ERASING;
2374 chip->erase_suspended = 0;
2375 chip->in_progress_block_addr = adr;
2376 chip->in_progress_block_mask = ~(len - 1);
2378 INVALIDATE_CACHE_UDELAY(map, chip,
2380 chip->erase_time*500);
2382 timeo = jiffies + (HZ*20);
2385 if (chip->state != FL_ERASING) {
2386 /* Someone's suspended the erase. Sleep */
2387 set_current_state(TASK_UNINTERRUPTIBLE);
2388 add_wait_queue(&chip->wq, &wait);
2389 mutex_unlock(&chip->mutex);
2391 remove_wait_queue(&chip->wq, &wait);
2392 mutex_lock(&chip->mutex);
2395 if (chip->erase_suspended) {
2396 /* This erase was suspended and resumed.
2397 Adjust the timeout */
2398 timeo = jiffies + (HZ*20); /* FIXME */
2399 chip->erase_suspended = 0;
2402 if (chip_good(map, adr, map_word_ff(map))) {
2403 xip_enable(map, chip, adr);
2407 if (time_after(jiffies, timeo)) {
2408 xip_enable(map, chip, adr);
2409 printk(KERN_WARNING "MTD %s(): software timeout\n",
2415 /* Latency issues. Drop the lock, wait a while and retry */
2416 UDELAY(map, chip, adr, 1000000/HZ);
2418 /* Did we succeed? */
2420 /* reset on all failures. */
2421 map_write( map, CMD(0xF0), chip->start );
2422 /* FIXME - should have reset delay before continuing */
2424 if (++retry_cnt <= MAX_RETRIES) {
2430 chip->state = FL_READY;
2432 put_chip(map, chip, adr);
2433 mutex_unlock(&chip->mutex);
2438 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
2440 unsigned long ofs, len;
2446 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
2450 instr->state = MTD_ERASE_DONE;
2451 mtd_erase_callback(instr);
2457 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
2459 struct map_info *map = mtd->priv;
2460 struct cfi_private *cfi = map->fldrv_priv;
2463 if (instr->addr != 0)
2466 if (instr->len != mtd->size)
2469 ret = do_erase_chip(map, &cfi->chips[0]);
2473 instr->state = MTD_ERASE_DONE;
2474 mtd_erase_callback(instr);
2479 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
2480 unsigned long adr, int len, void *thunk)
2482 struct cfi_private *cfi = map->fldrv_priv;
2485 mutex_lock(&chip->mutex);
2486 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
2489 chip->state = FL_LOCKING;
2491 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2493 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2494 cfi->device_type, NULL);
2495 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2496 cfi->device_type, NULL);
2497 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
2498 cfi->device_type, NULL);
2499 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2500 cfi->device_type, NULL);
2501 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2502 cfi->device_type, NULL);
2503 map_write(map, CMD(0x40), chip->start + adr);
2505 chip->state = FL_READY;
2506 put_chip(map, chip, adr + chip->start);
2510 mutex_unlock(&chip->mutex);
2514 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
2515 unsigned long adr, int len, void *thunk)
2517 struct cfi_private *cfi = map->fldrv_priv;
2520 mutex_lock(&chip->mutex);
2521 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
2524 chip->state = FL_UNLOCKING;
2526 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2528 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2529 cfi->device_type, NULL);
2530 map_write(map, CMD(0x70), adr);
2532 chip->state = FL_READY;
2533 put_chip(map, chip, adr + chip->start);
2537 mutex_unlock(&chip->mutex);
2541 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2543 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
2546 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2548 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
2552 * Advanced Sector Protection - PPB (Persistent Protection Bit) locking
2556 struct flchip *chip;
2561 #define MAX_SECTORS 512
2563 #define DO_XXLOCK_ONEBLOCK_LOCK ((void *)1)
2564 #define DO_XXLOCK_ONEBLOCK_UNLOCK ((void *)2)
2565 #define DO_XXLOCK_ONEBLOCK_GETLOCK ((void *)3)
2567 static int __maybe_unused do_ppb_xxlock(struct map_info *map,
2568 struct flchip *chip,
2569 unsigned long adr, int len, void *thunk)
2571 struct cfi_private *cfi = map->fldrv_priv;
2572 unsigned long timeo;
2576 mutex_lock(&chip->mutex);
2577 ret = get_chip(map, chip, adr, FL_LOCKING);
2579 mutex_unlock(&chip->mutex);
2583 pr_debug("MTD %s(): XXLOCK 0x%08lx len %d\n", __func__, adr, len);
2585 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2586 cfi->device_type, NULL);
2587 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2588 cfi->device_type, NULL);
2589 /* PPB entry command */
2590 cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi,
2591 cfi->device_type, NULL);
2593 if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) {
2594 chip->state = FL_LOCKING;
2595 map_write(map, CMD(0xA0), adr);
2596 map_write(map, CMD(0x00), adr);
2597 } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) {
2599 * Unlocking of one specific sector is not supported, so we
2600 * have to unlock all sectors of this device instead
2602 chip->state = FL_UNLOCKING;
2603 map_write(map, CMD(0x80), chip->start);
2604 map_write(map, CMD(0x30), chip->start);
2605 } else if (thunk == DO_XXLOCK_ONEBLOCK_GETLOCK) {
2606 chip->state = FL_JEDEC_QUERY;
2607 /* Return locked status: 0->locked, 1->unlocked */
2608 ret = !cfi_read_query(map, adr);
2613 * Wait for some time as unlocking of all sectors takes quite long
2615 timeo = jiffies + msecs_to_jiffies(2000); /* 2s max (un)locking */
2617 if (chip_ready(map, adr))
2620 if (time_after(jiffies, timeo)) {
2621 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
2626 UDELAY(map, chip, adr, 1);
2629 /* Exit BC commands */
2630 map_write(map, CMD(0x90), chip->start);
2631 map_write(map, CMD(0x00), chip->start);
2633 chip->state = FL_READY;
2634 put_chip(map, chip, adr);
2635 mutex_unlock(&chip->mutex);
2640 static int __maybe_unused cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs,
2643 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2644 DO_XXLOCK_ONEBLOCK_LOCK);
2647 static int __maybe_unused cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs,
2650 struct mtd_erase_region_info *regions = mtd->eraseregions;
2651 struct map_info *map = mtd->priv;
2652 struct cfi_private *cfi = map->fldrv_priv;
2653 struct ppb_lock *sect;
2663 * PPB unlocking always unlocks all sectors of the flash chip.
2664 * We need to re-lock all previously locked sectors. So lets
2665 * first check the locking status of all sectors and save
2666 * it for future use.
2668 sect = kzalloc(MAX_SECTORS * sizeof(struct ppb_lock), GFP_KERNEL);
2673 * This code to walk all sectors is a slightly modified version
2674 * of the cfi_varsize_frob() code.
2684 int size = regions[i].erasesize;
2687 * Only test sectors that shall not be unlocked. The other
2688 * sectors shall be unlocked, so lets keep their locking
2689 * status at "unlocked" (locked=0) for the final re-locking.
2691 if ((offset < ofs) || (offset >= (ofs + len))) {
2692 sect[sectors].chip = &cfi->chips[chipnum];
2693 sect[sectors].adr = adr;
2694 sect[sectors].locked = do_ppb_xxlock(
2695 map, &cfi->chips[chipnum], adr, 0,
2696 DO_XXLOCK_ONEBLOCK_GETLOCK);
2703 if (offset == regions[i].offset + size * regions[i].numblocks)
2706 if (adr >> cfi->chipshift) {
2707 if (offset >= (ofs + len))
2712 if (chipnum >= cfi->numchips)
2717 if (sectors >= MAX_SECTORS) {
2718 printk(KERN_ERR "Only %d sectors for PPB locking supported!\n",
2725 /* Now unlock the whole chip */
2726 ret = cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2727 DO_XXLOCK_ONEBLOCK_UNLOCK);
2734 * PPB unlocking always unlocks all sectors of the flash chip.
2735 * We need to re-lock all previously locked sectors.
2737 for (i = 0; i < sectors; i++) {
2739 do_ppb_xxlock(map, sect[i].chip, sect[i].adr, 0,
2740 DO_XXLOCK_ONEBLOCK_LOCK);
2747 static int __maybe_unused cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs,
2750 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2751 DO_XXLOCK_ONEBLOCK_GETLOCK) ? 1 : 0;
2754 static void cfi_amdstd_sync (struct mtd_info *mtd)
2756 struct map_info *map = mtd->priv;
2757 struct cfi_private *cfi = map->fldrv_priv;
2759 struct flchip *chip;
2761 DECLARE_WAITQUEUE(wait, current);
2763 for (i=0; !ret && i<cfi->numchips; i++) {
2764 chip = &cfi->chips[i];
2767 mutex_lock(&chip->mutex);
2769 switch(chip->state) {
2773 case FL_JEDEC_QUERY:
2774 chip->oldstate = chip->state;
2775 chip->state = FL_SYNCING;
2776 /* No need to wake_up() on this state change -
2777 * as the whole point is that nobody can do anything
2778 * with the chip now anyway.
2781 mutex_unlock(&chip->mutex);
2785 /* Not an idle state */
2786 set_current_state(TASK_UNINTERRUPTIBLE);
2787 add_wait_queue(&chip->wq, &wait);
2789 mutex_unlock(&chip->mutex);
2793 remove_wait_queue(&chip->wq, &wait);
2799 /* Unlock the chips again */
2801 for (i--; i >=0; i--) {
2802 chip = &cfi->chips[i];
2804 mutex_lock(&chip->mutex);
2806 if (chip->state == FL_SYNCING) {
2807 chip->state = chip->oldstate;
2810 mutex_unlock(&chip->mutex);
2815 static int cfi_amdstd_suspend(struct mtd_info *mtd)
2817 struct map_info *map = mtd->priv;
2818 struct cfi_private *cfi = map->fldrv_priv;
2820 struct flchip *chip;
2823 for (i=0; !ret && i<cfi->numchips; i++) {
2824 chip = &cfi->chips[i];
2826 mutex_lock(&chip->mutex);
2828 switch(chip->state) {
2832 case FL_JEDEC_QUERY:
2833 chip->oldstate = chip->state;
2834 chip->state = FL_PM_SUSPENDED;
2835 /* No need to wake_up() on this state change -
2836 * as the whole point is that nobody can do anything
2837 * with the chip now anyway.
2839 case FL_PM_SUSPENDED:
2846 mutex_unlock(&chip->mutex);
2849 /* Unlock the chips again */
2852 for (i--; i >=0; i--) {
2853 chip = &cfi->chips[i];
2855 mutex_lock(&chip->mutex);
2857 if (chip->state == FL_PM_SUSPENDED) {
2858 chip->state = chip->oldstate;
2861 mutex_unlock(&chip->mutex);
2869 static void cfi_amdstd_resume(struct mtd_info *mtd)
2871 struct map_info *map = mtd->priv;
2872 struct cfi_private *cfi = map->fldrv_priv;
2874 struct flchip *chip;
2876 for (i=0; i<cfi->numchips; i++) {
2878 chip = &cfi->chips[i];
2880 mutex_lock(&chip->mutex);
2882 if (chip->state == FL_PM_SUSPENDED) {
2883 chip->state = FL_READY;
2884 map_write(map, CMD(0xF0), chip->start);
2888 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
2890 mutex_unlock(&chip->mutex);
2896 * Ensure that the flash device is put back into read array mode before
2897 * unloading the driver or rebooting. On some systems, rebooting while
2898 * the flash is in query/program/erase mode will prevent the CPU from
2899 * fetching the bootloader code, requiring a hard reset or power cycle.
2901 static int cfi_amdstd_reset(struct mtd_info *mtd)
2903 struct map_info *map = mtd->priv;
2904 struct cfi_private *cfi = map->fldrv_priv;
2906 struct flchip *chip;
2908 for (i = 0; i < cfi->numchips; i++) {
2910 chip = &cfi->chips[i];
2912 mutex_lock(&chip->mutex);
2914 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
2916 map_write(map, CMD(0xF0), chip->start);
2917 chip->state = FL_SHUTDOWN;
2918 put_chip(map, chip, chip->start);
2921 mutex_unlock(&chip->mutex);
2928 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
2931 struct mtd_info *mtd;
2933 mtd = container_of(nb, struct mtd_info, reboot_notifier);
2934 cfi_amdstd_reset(mtd);
2939 static void cfi_amdstd_destroy(struct mtd_info *mtd)
2941 struct map_info *map = mtd->priv;
2942 struct cfi_private *cfi = map->fldrv_priv;
2944 cfi_amdstd_reset(mtd);
2945 unregister_reboot_notifier(&mtd->reboot_notifier);
2946 kfree(cfi->cmdset_priv);
2949 kfree(mtd->eraseregions);
2952 MODULE_LICENSE("GPL");
2953 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
2954 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
2955 MODULE_ALIAS("cfi_cmdset_0006");
2956 MODULE_ALIAS("cfi_cmdset_0701");