2 * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver
3 * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
11 #include <linux/pci.h>
12 #include <linux/module.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/highmem.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
18 #include <linux/mmc/host.h>
20 #define DRV_NAME "via_sdmmc"
22 #define PCI_DEVICE_ID_VIA_9530 0x9530
24 #define VIA_CRDR_SDC_OFF 0x200
25 #define VIA_CRDR_DDMA_OFF 0x400
26 #define VIA_CRDR_PCICTRL_OFF 0x600
28 #define VIA_CRDR_MIN_CLOCK 375000
29 #define VIA_CRDR_MAX_CLOCK 48000000
35 #define VIA_CRDR_PCI_WORK_MODE 0x40
36 #define VIA_CRDR_PCI_DBG_MODE 0x41
42 #define VIA_CRDR_SDCTRL 0x0
43 #define VIA_CRDR_SDCTRL_START 0x01
44 #define VIA_CRDR_SDCTRL_WRITE 0x04
45 #define VIA_CRDR_SDCTRL_SINGLE_WR 0x10
46 #define VIA_CRDR_SDCTRL_SINGLE_RD 0x20
47 #define VIA_CRDR_SDCTRL_MULTI_WR 0x30
48 #define VIA_CRDR_SDCTRL_MULTI_RD 0x40
49 #define VIA_CRDR_SDCTRL_STOP 0x70
51 #define VIA_CRDR_SDCTRL_RSP_NONE 0x0
52 #define VIA_CRDR_SDCTRL_RSP_R1 0x10000
53 #define VIA_CRDR_SDCTRL_RSP_R2 0x20000
54 #define VIA_CRDR_SDCTRL_RSP_R3 0x30000
55 #define VIA_CRDR_SDCTRL_RSP_R1B 0x90000
57 #define VIA_CRDR_SDCARG 0x4
59 #define VIA_CRDR_SDBUSMODE 0x8
60 #define VIA_CRDR_SDMODE_4BIT 0x02
61 #define VIA_CRDR_SDMODE_CLK_ON 0x40
63 #define VIA_CRDR_SDBLKLEN 0xc
65 * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048.
66 * Bit 11 - Bit 13 : Reserved.
67 * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design.
68 * INTEN : Enable SD host interrupt.
69 * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536.
71 #define VIA_CRDR_SDBLKLEN_GPIDET 0x2000
72 #define VIA_CRDR_SDBLKLEN_INTEN 0x8000
73 #define VIA_CRDR_MAX_BLOCK_COUNT 65536
74 #define VIA_CRDR_MAX_BLOCK_LENGTH 2048
76 #define VIA_CRDR_SDRESP0 0x10
77 #define VIA_CRDR_SDRESP1 0x14
78 #define VIA_CRDR_SDRESP2 0x18
79 #define VIA_CRDR_SDRESP3 0x1c
81 #define VIA_CRDR_SDCURBLKCNT 0x20
83 #define VIA_CRDR_SDINTMASK 0x24
85 * MBDIE : Multiple Blocks transfer Done Interrupt Enable
86 * BDDIE : Block Data transfer Done Interrupt Enable
87 * CIRIE : Card Insertion or Removal Interrupt Enable
88 * CRDIE : Command-Response transfer Done Interrupt Enable
89 * CRTOIE : Command-Response response TimeOut Interrupt Enable
90 * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable
91 * DTIE : Data access Timeout Interrupt Enable
92 * SCIE : reSponse CRC error Interrupt Enable
93 * RCIE : Read data CRC error Interrupt Enable
94 * WCIE : Write data CRC error Interrupt Enable
96 #define VIA_CRDR_SDINTMASK_MBDIE 0x10
97 #define VIA_CRDR_SDINTMASK_BDDIE 0x20
98 #define VIA_CRDR_SDINTMASK_CIRIE 0x80
99 #define VIA_CRDR_SDINTMASK_CRDIE 0x200
100 #define VIA_CRDR_SDINTMASK_CRTOIE 0x400
101 #define VIA_CRDR_SDINTMASK_ASCRDIE 0x800
102 #define VIA_CRDR_SDINTMASK_DTIE 0x1000
103 #define VIA_CRDR_SDINTMASK_SCIE 0x2000
104 #define VIA_CRDR_SDINTMASK_RCIE 0x4000
105 #define VIA_CRDR_SDINTMASK_WCIE 0x8000
107 #define VIA_CRDR_SDACTIVE_INTMASK \
108 (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \
109 | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \
110 | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \
111 | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE)
113 #define VIA_CRDR_SDSTATUS 0x28
116 * WP : SD card Write Protect status
118 * SLOTG : SD SLOT status(Gpi pin status)
119 * MBD : Multiple Blocks transfer Done interrupt status
120 * BDD : Block Data transfer Done interrupt status
122 * CIR : Card Insertion or Removal interrupt detected on GPI pin
124 * CRD : Command-Response transfer Done interrupt status
125 * CRTO : Command-Response response TimeOut interrupt status
126 * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status
127 * DT : Data access Timeout interrupt status
128 * SC : reSponse CRC error interrupt status
129 * RC : Read data CRC error interrupt status
130 * WC : Write data CRC error interrupt status
132 #define VIA_CRDR_SDSTS_CECC 0x01
133 #define VIA_CRDR_SDSTS_WP 0x02
134 #define VIA_CRDR_SDSTS_SLOTD 0x04
135 #define VIA_CRDR_SDSTS_SLOTG 0x08
136 #define VIA_CRDR_SDSTS_MBD 0x10
137 #define VIA_CRDR_SDSTS_BDD 0x20
138 #define VIA_CRDR_SDSTS_CD 0x40
139 #define VIA_CRDR_SDSTS_CIR 0x80
140 #define VIA_CRDR_SDSTS_IO 0x100
141 #define VIA_CRDR_SDSTS_CRD 0x200
142 #define VIA_CRDR_SDSTS_CRTO 0x400
143 #define VIA_CRDR_SDSTS_ASCRDIE 0x800
144 #define VIA_CRDR_SDSTS_DT 0x1000
145 #define VIA_CRDR_SDSTS_SC 0x2000
146 #define VIA_CRDR_SDSTS_RC 0x4000
147 #define VIA_CRDR_SDSTS_WC 0x8000
149 #define VIA_CRDR_SDSTS_IGN_MASK\
150 (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO)
151 #define VIA_CRDR_SDSTS_INT_MASK \
152 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \
153 | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \
154 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
155 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
156 #define VIA_CRDR_SDSTS_W1C_MASK \
157 (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \
158 | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \
159 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
160 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
161 #define VIA_CRDR_SDSTS_CMD_MASK \
162 (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC)
163 #define VIA_CRDR_SDSTS_DATA_MASK\
164 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \
165 | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
167 #define VIA_CRDR_SDSTATUS2 0x2a
169 * CFE : Enable SD host automatic Clock FReezing
171 #define VIA_CRDR_SDSTS_CFE 0x80
173 #define VIA_CRDR_SDRSPTMO 0x2C
175 #define VIA_CRDR_SDCLKSEL 0x30
177 #define VIA_CRDR_SDEXTCTRL 0x34
178 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01
179 #define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02
180 #define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04
181 #define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08
182 #define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10
183 #define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20
184 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40
185 #define VIA_CRDR_SDEXTCTRL_HISPD 0x80
186 /* 0x38-0xFF reserved */
189 * Data DMA Control Registers
192 #define VIA_CRDR_DMABASEADD 0x0
193 #define VIA_CRDR_DMACOUNTER 0x4
195 #define VIA_CRDR_DMACTRL 0x8
197 * DIR :Transaction Direction
198 * 0 : From card to memory
199 * 1 : From memory to card
201 #define VIA_CRDR_DMACTRL_DIR 0x100
202 #define VIA_CRDR_DMACTRL_ENIRQ 0x10000
203 #define VIA_CRDR_DMACTRL_SFTRST 0x1000000
205 #define VIA_CRDR_DMASTS 0xc
207 #define VIA_CRDR_DMASTART 0x10
208 /*0x14-0xFF reserved*/
211 * PCI Control Registers
214 /*0x0 - 0x1 reserved*/
215 #define VIA_CRDR_PCICLKGATT 0x2
218 * 0 : Soft reset all the controller and it will be de-asserted automatically
219 * 1 : Soft reset is de-asserted
221 #define VIA_CRDR_PCICLKGATT_SFTRST 0x01
223 * 3V3 : Pad power select
226 * NOTE : No mater what the actual value should be, this bit always
227 * read as 0. This is a hardware bug.
229 #define VIA_CRDR_PCICLKGATT_3V3 0x10
231 * PAD_PWRON : Pad Power on/off select
234 * NOTE : No mater what the actual value should be, this bit always
235 * read as 0. This is a hardware bug.
237 #define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20
239 #define VIA_CRDR_PCISDCCLK 0x5
241 #define VIA_CRDR_PCIDMACLK 0x7
242 #define VIA_CRDR_PCIDMACLK_SDC 0x2
244 #define VIA_CRDR_PCIINTCTRL 0x8
245 #define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04
247 #define VIA_CRDR_PCIINTSTATUS 0x9
248 #define VIA_CRDR_PCIINTSTATUS_SDC 0x04
250 #define VIA_CRDR_PCITMOCTRL 0xa
251 #define VIA_CRDR_PCITMOCTRL_NO 0x0
252 #define VIA_CRDR_PCITMOCTRL_32US 0x1
253 #define VIA_CRDR_PCITMOCTRL_256US 0x2
254 #define VIA_CRDR_PCITMOCTRL_1024US 0x3
255 #define VIA_CRDR_PCITMOCTRL_256MS 0x4
256 #define VIA_CRDR_PCITMOCTRL_512MS 0x5
257 #define VIA_CRDR_PCITMOCTRL_1024MS 0x6
259 /*0xB-0xFF reserved*/
261 enum PCI_HOST_CLK_CONTROL {
299 struct via_crdr_mmc_host {
300 struct mmc_host *mmc;
301 struct mmc_request *mrq;
302 struct mmc_command *cmd;
303 struct mmc_data *data;
305 void __iomem *mmiobase;
306 void __iomem *sdhc_mmiobase;
307 void __iomem *ddma_mmiobase;
308 void __iomem *pcictrl_mmiobase;
310 struct pcictrlreg pm_pcictrl_reg;
311 struct sdhcreg pm_sdhc_reg;
313 struct work_struct carddet_work;
314 struct tasklet_struct finish_tasklet;
316 struct timer_list timer;
323 /* some devices need a very long delay for power to stabilize */
324 #define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001
326 #define VIA_CMD_TIMEOUT_MS 1000
328 static const struct pci_device_id via_ids[] = {
329 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530,
330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
334 MODULE_DEVICE_TABLE(pci, via_ids);
336 static void via_print_sdchc(struct via_crdr_mmc_host *host)
338 void __iomem *addrbase = host->sdhc_mmiobase;
340 pr_debug("SDC MMIO Registers:\n");
341 pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n",
342 readl(addrbase + VIA_CRDR_SDCTRL),
343 readl(addrbase + VIA_CRDR_SDCARG),
344 readl(addrbase + VIA_CRDR_SDBUSMODE));
345 pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n",
346 readl(addrbase + VIA_CRDR_SDBLKLEN),
347 readl(addrbase + VIA_CRDR_SDCURBLKCNT),
348 readl(addrbase + VIA_CRDR_SDINTMASK));
349 pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n",
350 readl(addrbase + VIA_CRDR_SDSTATUS),
351 readl(addrbase + VIA_CRDR_SDCLKSEL),
352 readl(addrbase + VIA_CRDR_SDEXTCTRL));
355 static void via_print_pcictrl(struct via_crdr_mmc_host *host)
357 void __iomem *addrbase = host->pcictrl_mmiobase;
359 pr_debug("PCI Control Registers:\n");
360 pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n",
361 readb(addrbase + VIA_CRDR_PCICLKGATT),
362 readb(addrbase + VIA_CRDR_PCISDCCLK),
363 readb(addrbase + VIA_CRDR_PCIDMACLK));
364 pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n",
365 readb(addrbase + VIA_CRDR_PCIINTCTRL),
366 readb(addrbase + VIA_CRDR_PCIINTSTATUS));
369 static void via_save_pcictrlreg(struct via_crdr_mmc_host *host)
371 struct pcictrlreg *pm_pcictrl_reg;
372 void __iomem *addrbase;
374 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
375 addrbase = host->pcictrl_mmiobase;
377 pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT);
378 pm_pcictrl_reg->pciclkgat_reg |=
379 VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
380 pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK);
381 pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK);
382 pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL);
383 pm_pcictrl_reg->pciintstatus_reg =
384 readb(addrbase + VIA_CRDR_PCIINTSTATUS);
385 pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL);
388 static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host)
390 struct pcictrlreg *pm_pcictrl_reg;
391 void __iomem *addrbase;
393 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
394 addrbase = host->pcictrl_mmiobase;
396 writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT);
397 writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK);
398 writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK);
399 writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL);
400 writeb(pm_pcictrl_reg->pciintstatus_reg,
401 addrbase + VIA_CRDR_PCIINTSTATUS);
402 writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL);
405 static void via_save_sdcreg(struct via_crdr_mmc_host *host)
407 struct sdhcreg *pm_sdhc_reg;
408 void __iomem *addrbase;
410 pm_sdhc_reg = &(host->pm_sdhc_reg);
411 addrbase = host->sdhc_mmiobase;
413 pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL);
414 pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG);
415 pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE);
416 pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN);
417 pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT);
418 pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK);
419 pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS);
420 pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO);
421 pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL);
422 pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL);
425 static void via_restore_sdcreg(struct via_crdr_mmc_host *host)
427 struct sdhcreg *pm_sdhc_reg;
428 void __iomem *addrbase;
430 pm_sdhc_reg = &(host->pm_sdhc_reg);
431 addrbase = host->sdhc_mmiobase;
433 writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
434 writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
435 writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE);
436 writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN);
437 writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT);
438 writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
439 writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS);
440 writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
441 writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
442 writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
445 static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost)
447 if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY)
453 static void via_set_ddma(struct via_crdr_mmc_host *host,
454 dma_addr_t dmaaddr, u32 count, int dir, int enirq)
456 void __iomem *addrbase;
460 ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ;
463 ctrl_data |= VIA_CRDR_DMACTRL_DIR;
465 addrbase = host->ddma_mmiobase;
467 writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD);
468 writel(count, addrbase + VIA_CRDR_DMACOUNTER);
469 writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL);
470 writel(0x01, addrbase + VIA_CRDR_DMASTART);
472 /* It seems that our DMA can not work normally with 375kHz clock */
473 /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */
474 addrbase = host->pcictrl_mmiobase;
475 if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) {
476 dev_info(host->mmc->parent, "forcing card speed to 8MHz\n");
477 writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK);
481 static void via_sdc_preparedata(struct via_crdr_mmc_host *host,
482 struct mmc_data *data)
484 void __iomem *addrbase;
491 BUG_ON(data->blksz > host->mmc->max_blk_size);
492 BUG_ON(data->blocks > host->mmc->max_blk_count);
496 count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
497 ((data->flags & MMC_DATA_READ) ?
498 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
501 via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg),
502 (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1);
504 addrbase = host->sdhc_mmiobase;
506 blk_reg = data->blksz - 1;
507 blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
508 blk_reg |= (data->blocks) << 16;
510 writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN);
513 static void via_sdc_get_response(struct via_crdr_mmc_host *host,
514 struct mmc_command *cmd)
516 void __iomem *addrbase = host->sdhc_mmiobase;
517 u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0);
518 u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1);
519 u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2);
520 u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3);
522 if (cmd->flags & MMC_RSP_136) {
523 cmd->resp[0] = ((u8) (dwdata1)) |
524 (((u8) (dwdata0 >> 24)) << 8) |
525 (((u8) (dwdata0 >> 16)) << 16) |
526 (((u8) (dwdata0 >> 8)) << 24);
528 cmd->resp[1] = ((u8) (dwdata2)) |
529 (((u8) (dwdata1 >> 24)) << 8) |
530 (((u8) (dwdata1 >> 16)) << 16) |
531 (((u8) (dwdata1 >> 8)) << 24);
533 cmd->resp[2] = ((u8) (dwdata3)) |
534 (((u8) (dwdata2 >> 24)) << 8) |
535 (((u8) (dwdata2 >> 16)) << 16) |
536 (((u8) (dwdata2 >> 8)) << 24);
538 cmd->resp[3] = 0xff |
539 ((((u8) (dwdata3 >> 24))) << 8) |
540 (((u8) (dwdata3 >> 16)) << 16) |
541 (((u8) (dwdata3 >> 8)) << 24);
544 cmd->resp[0] = ((dwdata0 & 0xff) << 24) |
545 (((dwdata0 >> 8) & 0xff) << 16) |
546 (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff);
549 cmd->resp[1] = ((dwdata1 & 0xff) << 24) |
550 (((dwdata1 >> 8) & 0xff) << 16) |
551 (((dwdata1 >> 16) & 0xff) << 8);
555 static void via_sdc_send_command(struct via_crdr_mmc_host *host,
556 struct mmc_command *cmd)
558 void __iomem *addrbase;
559 struct mmc_data *data;
560 unsigned int timeout_ms;
568 timeout_ms = cmd->busy_timeout ? cmd->busy_timeout : VIA_CMD_TIMEOUT_MS;
569 mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout_ms));
572 cmdctrl = cmd->opcode << 8;
575 switch (mmc_resp_type(cmd)) {
577 cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE;
580 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1;
583 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B;
586 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2;
589 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3;
592 pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc));
599 via_sdc_preparedata(host, data);
602 if (data->blocks > 1) {
603 if (data->flags & MMC_DATA_WRITE) {
604 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
605 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR;
607 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD;
610 if (data->flags & MMC_DATA_WRITE) {
611 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
612 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR;
614 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD;
619 if (cmd == host->mrq->stop)
620 cmdctrl |= VIA_CRDR_SDCTRL_STOP;
622 cmdctrl |= VIA_CRDR_SDCTRL_START;
624 addrbase = host->sdhc_mmiobase;
625 writel(cmd->arg, addrbase + VIA_CRDR_SDCARG);
626 writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL);
629 static void via_sdc_finish_data(struct via_crdr_mmc_host *host)
631 struct mmc_data *data;
639 data->bytes_xfered = 0;
641 data->bytes_xfered = data->blocks * data->blksz;
643 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
644 ((data->flags & MMC_DATA_READ) ?
645 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
648 via_sdc_send_command(host, data->stop);
650 tasklet_schedule(&host->finish_tasklet);
653 static void via_sdc_finish_command(struct via_crdr_mmc_host *host)
655 via_sdc_get_response(host, host->cmd);
657 host->cmd->error = 0;
659 if (!host->cmd->data)
660 tasklet_schedule(&host->finish_tasklet);
665 static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq)
667 void __iomem *addrbase;
668 struct via_crdr_mmc_host *host;
672 host = mmc_priv(mmc);
674 spin_lock_irqsave(&host->lock, flags);
676 addrbase = host->pcictrl_mmiobase;
677 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
679 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
680 status &= VIA_CRDR_SDSTS_W1C_MASK;
681 writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
683 WARN_ON(host->mrq != NULL);
686 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
687 if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) {
688 host->mrq->cmd->error = -ENOMEDIUM;
689 tasklet_schedule(&host->finish_tasklet);
691 via_sdc_send_command(host, mrq->cmd);
695 spin_unlock_irqrestore(&host->lock, flags);
698 static void via_sdc_set_power(struct via_crdr_mmc_host *host,
699 unsigned short power, unsigned int on)
704 spin_lock_irqsave(&host->lock, flags);
706 host->power = (1 << power);
708 gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
709 if (host->power == MMC_VDD_165_195)
710 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
712 gatt |= VIA_CRDR_PCICLKGATT_3V3;
714 gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON;
716 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
717 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
720 spin_unlock_irqrestore(&host->lock, flags);
722 via_pwron_sleep(host);
725 static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
727 struct via_crdr_mmc_host *host;
729 void __iomem *addrbase;
730 u32 org_data, sdextctrl;
733 host = mmc_priv(mmc);
735 spin_lock_irqsave(&host->lock, flags);
737 addrbase = host->sdhc_mmiobase;
738 org_data = readl(addrbase + VIA_CRDR_SDBUSMODE);
739 sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL);
741 if (ios->bus_width == MMC_BUS_WIDTH_1)
742 org_data &= ~VIA_CRDR_SDMODE_4BIT;
744 org_data |= VIA_CRDR_SDMODE_4BIT;
746 if (ios->power_mode == MMC_POWER_OFF)
747 org_data &= ~VIA_CRDR_SDMODE_CLK_ON;
749 org_data |= VIA_CRDR_SDMODE_CLK_ON;
751 if (ios->timing == MMC_TIMING_SD_HS)
752 sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD;
754 sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD;
756 writel(org_data, addrbase + VIA_CRDR_SDBUSMODE);
757 writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL);
759 if (ios->clock >= 48000000)
761 else if (ios->clock >= 33000000)
763 else if (ios->clock >= 24000000)
765 else if (ios->clock >= 16000000)
767 else if (ios->clock >= 12000000)
769 else if (ios->clock >= 8000000)
772 clock = PCI_CLK_375K;
774 addrbase = host->pcictrl_mmiobase;
775 if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock)
776 writeb(clock, addrbase + VIA_CRDR_PCISDCCLK);
779 spin_unlock_irqrestore(&host->lock, flags);
781 if (ios->power_mode != MMC_POWER_OFF)
782 via_sdc_set_power(host, ios->vdd, 1);
784 via_sdc_set_power(host, ios->vdd, 0);
787 static int via_sdc_get_ro(struct mmc_host *mmc)
789 struct via_crdr_mmc_host *host;
793 host = mmc_priv(mmc);
795 spin_lock_irqsave(&host->lock, flags);
797 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
799 spin_unlock_irqrestore(&host->lock, flags);
801 return !(status & VIA_CRDR_SDSTS_WP);
804 static const struct mmc_host_ops via_sdc_ops = {
805 .request = via_sdc_request,
806 .set_ios = via_sdc_set_ios,
807 .get_ro = via_sdc_get_ro,
810 static void via_reset_pcictrl(struct via_crdr_mmc_host *host)
815 spin_lock_irqsave(&host->lock, flags);
817 via_save_pcictrlreg(host);
818 via_save_sdcreg(host);
820 spin_unlock_irqrestore(&host->lock, flags);
822 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
823 if (host->power == MMC_VDD_165_195)
824 gatt &= VIA_CRDR_PCICLKGATT_3V3;
826 gatt |= VIA_CRDR_PCICLKGATT_3V3;
827 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
828 via_pwron_sleep(host);
829 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
830 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
833 spin_lock_irqsave(&host->lock, flags);
835 via_restore_pcictrlreg(host);
836 via_restore_sdcreg(host);
839 spin_unlock_irqrestore(&host->lock, flags);
842 static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask)
844 BUG_ON(intmask == 0);
847 pr_err("%s: Got command interrupt 0x%x even "
848 "though no command operation was in progress.\n",
849 mmc_hostname(host->mmc), intmask);
853 if (intmask & VIA_CRDR_SDSTS_CRTO)
854 host->cmd->error = -ETIMEDOUT;
855 else if (intmask & VIA_CRDR_SDSTS_SC)
856 host->cmd->error = -EILSEQ;
858 if (host->cmd->error)
859 tasklet_schedule(&host->finish_tasklet);
860 else if (intmask & VIA_CRDR_SDSTS_CRD)
861 via_sdc_finish_command(host);
864 static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask)
866 BUG_ON(intmask == 0);
871 if (intmask & VIA_CRDR_SDSTS_DT)
872 host->data->error = -ETIMEDOUT;
873 else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC))
874 host->data->error = -EILSEQ;
876 via_sdc_finish_data(host);
879 static irqreturn_t via_sdc_isr(int irq, void *dev_id)
881 struct via_crdr_mmc_host *sdhost = dev_id;
882 void __iomem *addrbase;
890 spin_lock(&sdhost->lock);
892 addrbase = sdhost->pcictrl_mmiobase;
893 pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS);
894 if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) {
899 addrbase = sdhost->sdhc_mmiobase;
900 sd_status = readw(addrbase + VIA_CRDR_SDSTATUS);
901 sd_status &= VIA_CRDR_SDSTS_INT_MASK;
902 sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK;
908 if (sd_status & VIA_CRDR_SDSTS_CIR) {
909 writew(sd_status & VIA_CRDR_SDSTS_CIR,
910 addrbase + VIA_CRDR_SDSTATUS);
912 schedule_work(&sdhost->carddet_work);
915 sd_status &= ~VIA_CRDR_SDSTS_CIR;
916 if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) {
917 writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK,
918 addrbase + VIA_CRDR_SDSTATUS);
919 via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK);
921 if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) {
922 writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK,
923 addrbase + VIA_CRDR_SDSTATUS);
924 via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK);
927 sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK);
929 pr_err("%s: Unexpected interrupt 0x%x\n",
930 mmc_hostname(sdhost->mmc), sd_status);
931 writew(sd_status, addrbase + VIA_CRDR_SDSTATUS);
934 result = IRQ_HANDLED;
938 spin_unlock(&sdhost->lock);
943 static void via_sdc_timeout(unsigned long ulongdata)
945 struct via_crdr_mmc_host *sdhost;
948 sdhost = (struct via_crdr_mmc_host *)ulongdata;
950 spin_lock_irqsave(&sdhost->lock, flags);
953 pr_err("%s: Timeout waiting for hardware interrupt."
954 "cmd:0x%x\n", mmc_hostname(sdhost->mmc),
955 sdhost->mrq->cmd->opcode);
958 writel(VIA_CRDR_DMACTRL_SFTRST,
959 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
960 sdhost->data->error = -ETIMEDOUT;
961 via_sdc_finish_data(sdhost);
964 sdhost->cmd->error = -ETIMEDOUT;
966 sdhost->mrq->cmd->error = -ETIMEDOUT;
967 tasklet_schedule(&sdhost->finish_tasklet);
972 spin_unlock_irqrestore(&sdhost->lock, flags);
975 static void via_sdc_tasklet_finish(unsigned long param)
977 struct via_crdr_mmc_host *host;
979 struct mmc_request *mrq;
981 host = (struct via_crdr_mmc_host *)param;
983 spin_lock_irqsave(&host->lock, flags);
985 del_timer(&host->timer);
991 spin_unlock_irqrestore(&host->lock, flags);
993 mmc_request_done(host->mmc, mrq);
996 static void via_sdc_card_detect(struct work_struct *work)
998 struct via_crdr_mmc_host *host;
999 void __iomem *addrbase;
1000 unsigned long flags;
1003 host = container_of(work, struct via_crdr_mmc_host, carddet_work);
1005 addrbase = host->ddma_mmiobase;
1006 writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL);
1008 spin_lock_irqsave(&host->lock, flags);
1010 addrbase = host->pcictrl_mmiobase;
1011 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
1013 addrbase = host->sdhc_mmiobase;
1014 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1015 if (!(status & VIA_CRDR_SDSTS_SLOTG)) {
1017 pr_err("%s: Card removed during transfer!\n",
1018 mmc_hostname(host->mmc));
1019 host->mrq->cmd->error = -ENOMEDIUM;
1020 tasklet_schedule(&host->finish_tasklet);
1024 spin_unlock_irqrestore(&host->lock, flags);
1026 via_reset_pcictrl(host);
1028 spin_lock_irqsave(&host->lock, flags);
1032 spin_unlock_irqrestore(&host->lock, flags);
1034 via_print_pcictrl(host);
1035 via_print_sdchc(host);
1037 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1040 static void via_init_mmc_host(struct via_crdr_mmc_host *host)
1042 struct mmc_host *mmc = host->mmc;
1043 void __iomem *addrbase;
1047 init_timer(&host->timer);
1048 host->timer.data = (unsigned long)host;
1049 host->timer.function = via_sdc_timeout;
1051 spin_lock_init(&host->lock);
1053 mmc->f_min = VIA_CRDR_MIN_CLOCK;
1054 mmc->f_max = VIA_CRDR_MAX_CLOCK;
1055 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1056 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED;
1057 mmc->ops = &via_sdc_ops;
1059 /*Hardware cannot do scatter lists*/
1062 mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH;
1063 mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT;
1065 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
1066 mmc->max_req_size = mmc->max_seg_size;
1068 INIT_WORK(&host->carddet_work, via_sdc_card_detect);
1070 tasklet_init(&host->finish_tasklet, via_sdc_tasklet_finish,
1071 (unsigned long)host);
1073 addrbase = host->sdhc_mmiobase;
1074 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1077 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1078 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1080 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1081 status &= VIA_CRDR_SDSTS_W1C_MASK;
1082 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1084 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1085 status |= VIA_CRDR_SDSTS_CFE;
1086 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1088 writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL);
1090 writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK);
1094 static int via_sd_probe(struct pci_dev *pcidev,
1095 const struct pci_device_id *id)
1097 struct mmc_host *mmc;
1098 struct via_crdr_mmc_host *sdhost;
1104 ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n",
1105 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1106 (int)pcidev->revision);
1108 ret = pci_enable_device(pcidev);
1112 ret = pci_request_regions(pcidev, DRV_NAME);
1116 pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0);
1117 pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0);
1119 mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev);
1125 sdhost = mmc_priv(mmc);
1127 dev_set_drvdata(&pcidev->dev, sdhost);
1129 len = pci_resource_len(pcidev, 0);
1130 base = pci_resource_start(pcidev, 0);
1131 sdhost->mmiobase = ioremap_nocache(base, len);
1132 if (!sdhost->mmiobase) {
1137 sdhost->sdhc_mmiobase =
1138 sdhost->mmiobase + VIA_CRDR_SDC_OFF;
1139 sdhost->ddma_mmiobase =
1140 sdhost->mmiobase + VIA_CRDR_DDMA_OFF;
1141 sdhost->pcictrl_mmiobase =
1142 sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF;
1144 sdhost->power = MMC_VDD_165_195;
1146 gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
1147 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1148 via_pwron_sleep(sdhost);
1149 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1150 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1153 via_init_mmc_host(sdhost);
1156 request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME,
1161 writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN,
1162 sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1163 writeb(VIA_CRDR_PCITMOCTRL_1024MS,
1164 sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL);
1166 /* device-specific quirks */
1167 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
1168 pcidev->subsystem_device == 0x3891)
1169 sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY;
1176 iounmap(sdhost->mmiobase);
1178 dev_set_drvdata(&pcidev->dev, NULL);
1181 pci_release_regions(pcidev);
1183 pci_disable_device(pcidev);
1188 static void via_sd_remove(struct pci_dev *pcidev)
1190 struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev);
1191 unsigned long flags;
1194 spin_lock_irqsave(&sdhost->lock, flags);
1196 /* Ensure we don't accept more commands from mmc layer */
1199 /* Disable generating further interrupts */
1200 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1204 pr_err("%s: Controller removed during "
1205 "transfer\n", mmc_hostname(sdhost->mmc));
1207 /* make sure all DMA is stopped */
1208 writel(VIA_CRDR_DMACTRL_SFTRST,
1209 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
1211 sdhost->mrq->cmd->error = -ENOMEDIUM;
1212 if (sdhost->mrq->stop)
1213 sdhost->mrq->stop->error = -ENOMEDIUM;
1214 tasklet_schedule(&sdhost->finish_tasklet);
1216 spin_unlock_irqrestore(&sdhost->lock, flags);
1218 mmc_remove_host(sdhost->mmc);
1220 free_irq(pcidev->irq, sdhost);
1222 del_timer_sync(&sdhost->timer);
1224 tasklet_kill(&sdhost->finish_tasklet);
1226 /* switch off power */
1227 gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1228 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
1229 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1231 iounmap(sdhost->mmiobase);
1232 dev_set_drvdata(&pcidev->dev, NULL);
1233 mmc_free_host(sdhost->mmc);
1234 pci_release_regions(pcidev);
1235 pci_disable_device(pcidev);
1238 ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n",
1239 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1244 static void via_init_sdc_pm(struct via_crdr_mmc_host *host)
1246 struct sdhcreg *pm_sdhcreg;
1247 void __iomem *addrbase;
1251 pm_sdhcreg = &(host->pm_sdhc_reg);
1252 addrbase = host->sdhc_mmiobase;
1254 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1256 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1257 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1259 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1260 status &= VIA_CRDR_SDSTS_W1C_MASK;
1261 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1263 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1264 status |= VIA_CRDR_SDSTS_CFE;
1265 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1267 writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
1268 writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
1269 writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
1270 writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
1271 writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
1272 writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
1274 via_print_pcictrl(host);
1275 via_print_sdchc(host);
1278 static int via_sd_suspend(struct pci_dev *pcidev, pm_message_t state)
1280 struct via_crdr_mmc_host *host;
1281 unsigned long flags;
1283 host = pci_get_drvdata(pcidev);
1285 spin_lock_irqsave(&host->lock, flags);
1286 via_save_pcictrlreg(host);
1287 via_save_sdcreg(host);
1288 spin_unlock_irqrestore(&host->lock, flags);
1290 pci_save_state(pcidev);
1291 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1292 pci_disable_device(pcidev);
1293 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1298 static int via_sd_resume(struct pci_dev *pcidev)
1300 struct via_crdr_mmc_host *sdhost;
1304 sdhost = pci_get_drvdata(pcidev);
1306 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
1307 if (sdhost->power == MMC_VDD_165_195)
1308 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
1310 gatt |= VIA_CRDR_PCICLKGATT_3V3;
1311 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1312 via_pwron_sleep(sdhost);
1313 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1314 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1319 pci_set_power_state(pcidev, PCI_D0);
1320 pci_restore_state(pcidev);
1321 ret = pci_enable_device(pcidev);
1325 via_restore_pcictrlreg(sdhost);
1326 via_init_sdc_pm(sdhost);
1331 #else /* CONFIG_PM */
1333 #define via_sd_suspend NULL
1334 #define via_sd_resume NULL
1336 #endif /* CONFIG_PM */
1338 static struct pci_driver via_sd_driver = {
1340 .id_table = via_ids,
1341 .probe = via_sd_probe,
1342 .remove = via_sd_remove,
1343 .suspend = via_sd_suspend,
1344 .resume = via_sd_resume,
1347 module_pci_driver(via_sd_driver);
1349 MODULE_LICENSE("GPL");
1350 MODULE_AUTHOR("VIA Technologies Inc.");
1351 MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver");