1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver
4 * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved.
8 #include <linux/module.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/highmem.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
14 #include <linux/mmc/host.h>
16 #define DRV_NAME "via_sdmmc"
18 #define PCI_DEVICE_ID_VIA_9530 0x9530
20 #define VIA_CRDR_SDC_OFF 0x200
21 #define VIA_CRDR_DDMA_OFF 0x400
22 #define VIA_CRDR_PCICTRL_OFF 0x600
24 #define VIA_CRDR_MIN_CLOCK 375000
25 #define VIA_CRDR_MAX_CLOCK 48000000
31 #define VIA_CRDR_PCI_WORK_MODE 0x40
32 #define VIA_CRDR_PCI_DBG_MODE 0x41
38 #define VIA_CRDR_SDCTRL 0x0
39 #define VIA_CRDR_SDCTRL_START 0x01
40 #define VIA_CRDR_SDCTRL_WRITE 0x04
41 #define VIA_CRDR_SDCTRL_SINGLE_WR 0x10
42 #define VIA_CRDR_SDCTRL_SINGLE_RD 0x20
43 #define VIA_CRDR_SDCTRL_MULTI_WR 0x30
44 #define VIA_CRDR_SDCTRL_MULTI_RD 0x40
45 #define VIA_CRDR_SDCTRL_STOP 0x70
47 #define VIA_CRDR_SDCTRL_RSP_NONE 0x0
48 #define VIA_CRDR_SDCTRL_RSP_R1 0x10000
49 #define VIA_CRDR_SDCTRL_RSP_R2 0x20000
50 #define VIA_CRDR_SDCTRL_RSP_R3 0x30000
51 #define VIA_CRDR_SDCTRL_RSP_R1B 0x90000
53 #define VIA_CRDR_SDCARG 0x4
55 #define VIA_CRDR_SDBUSMODE 0x8
56 #define VIA_CRDR_SDMODE_4BIT 0x02
57 #define VIA_CRDR_SDMODE_CLK_ON 0x40
59 #define VIA_CRDR_SDBLKLEN 0xc
61 * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048.
62 * Bit 11 - Bit 13 : Reserved.
63 * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design.
64 * INTEN : Enable SD host interrupt.
65 * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536.
67 #define VIA_CRDR_SDBLKLEN_GPIDET 0x2000
68 #define VIA_CRDR_SDBLKLEN_INTEN 0x8000
69 #define VIA_CRDR_MAX_BLOCK_COUNT 65536
70 #define VIA_CRDR_MAX_BLOCK_LENGTH 2048
72 #define VIA_CRDR_SDRESP0 0x10
73 #define VIA_CRDR_SDRESP1 0x14
74 #define VIA_CRDR_SDRESP2 0x18
75 #define VIA_CRDR_SDRESP3 0x1c
77 #define VIA_CRDR_SDCURBLKCNT 0x20
79 #define VIA_CRDR_SDINTMASK 0x24
81 * MBDIE : Multiple Blocks transfer Done Interrupt Enable
82 * BDDIE : Block Data transfer Done Interrupt Enable
83 * CIRIE : Card Insertion or Removal Interrupt Enable
84 * CRDIE : Command-Response transfer Done Interrupt Enable
85 * CRTOIE : Command-Response response TimeOut Interrupt Enable
86 * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable
87 * DTIE : Data access Timeout Interrupt Enable
88 * SCIE : reSponse CRC error Interrupt Enable
89 * RCIE : Read data CRC error Interrupt Enable
90 * WCIE : Write data CRC error Interrupt Enable
92 #define VIA_CRDR_SDINTMASK_MBDIE 0x10
93 #define VIA_CRDR_SDINTMASK_BDDIE 0x20
94 #define VIA_CRDR_SDINTMASK_CIRIE 0x80
95 #define VIA_CRDR_SDINTMASK_CRDIE 0x200
96 #define VIA_CRDR_SDINTMASK_CRTOIE 0x400
97 #define VIA_CRDR_SDINTMASK_ASCRDIE 0x800
98 #define VIA_CRDR_SDINTMASK_DTIE 0x1000
99 #define VIA_CRDR_SDINTMASK_SCIE 0x2000
100 #define VIA_CRDR_SDINTMASK_RCIE 0x4000
101 #define VIA_CRDR_SDINTMASK_WCIE 0x8000
103 #define VIA_CRDR_SDACTIVE_INTMASK \
104 (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \
105 | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \
106 | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \
107 | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE)
109 #define VIA_CRDR_SDSTATUS 0x28
112 * WP : SD card Write Protect status
114 * SLOTG : SD SLOT status(Gpi pin status)
115 * MBD : Multiple Blocks transfer Done interrupt status
116 * BDD : Block Data transfer Done interrupt status
118 * CIR : Card Insertion or Removal interrupt detected on GPI pin
120 * CRD : Command-Response transfer Done interrupt status
121 * CRTO : Command-Response response TimeOut interrupt status
122 * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status
123 * DT : Data access Timeout interrupt status
124 * SC : reSponse CRC error interrupt status
125 * RC : Read data CRC error interrupt status
126 * WC : Write data CRC error interrupt status
128 #define VIA_CRDR_SDSTS_CECC 0x01
129 #define VIA_CRDR_SDSTS_WP 0x02
130 #define VIA_CRDR_SDSTS_SLOTD 0x04
131 #define VIA_CRDR_SDSTS_SLOTG 0x08
132 #define VIA_CRDR_SDSTS_MBD 0x10
133 #define VIA_CRDR_SDSTS_BDD 0x20
134 #define VIA_CRDR_SDSTS_CD 0x40
135 #define VIA_CRDR_SDSTS_CIR 0x80
136 #define VIA_CRDR_SDSTS_IO 0x100
137 #define VIA_CRDR_SDSTS_CRD 0x200
138 #define VIA_CRDR_SDSTS_CRTO 0x400
139 #define VIA_CRDR_SDSTS_ASCRDIE 0x800
140 #define VIA_CRDR_SDSTS_DT 0x1000
141 #define VIA_CRDR_SDSTS_SC 0x2000
142 #define VIA_CRDR_SDSTS_RC 0x4000
143 #define VIA_CRDR_SDSTS_WC 0x8000
145 #define VIA_CRDR_SDSTS_IGN_MASK\
146 (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO)
147 #define VIA_CRDR_SDSTS_INT_MASK \
148 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \
149 | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \
150 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
151 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
152 #define VIA_CRDR_SDSTS_W1C_MASK \
153 (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \
154 | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \
155 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
156 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
157 #define VIA_CRDR_SDSTS_CMD_MASK \
158 (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC)
159 #define VIA_CRDR_SDSTS_DATA_MASK\
160 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \
161 | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
163 #define VIA_CRDR_SDSTATUS2 0x2a
165 * CFE : Enable SD host automatic Clock FReezing
167 #define VIA_CRDR_SDSTS_CFE 0x80
169 #define VIA_CRDR_SDRSPTMO 0x2C
171 #define VIA_CRDR_SDCLKSEL 0x30
173 #define VIA_CRDR_SDEXTCTRL 0x34
174 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01
175 #define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02
176 #define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04
177 #define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08
178 #define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10
179 #define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20
180 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40
181 #define VIA_CRDR_SDEXTCTRL_HISPD 0x80
182 /* 0x38-0xFF reserved */
185 * Data DMA Control Registers
188 #define VIA_CRDR_DMABASEADD 0x0
189 #define VIA_CRDR_DMACOUNTER 0x4
191 #define VIA_CRDR_DMACTRL 0x8
193 * DIR :Transaction Direction
194 * 0 : From card to memory
195 * 1 : From memory to card
197 #define VIA_CRDR_DMACTRL_DIR 0x100
198 #define VIA_CRDR_DMACTRL_ENIRQ 0x10000
199 #define VIA_CRDR_DMACTRL_SFTRST 0x1000000
201 #define VIA_CRDR_DMASTS 0xc
203 #define VIA_CRDR_DMASTART 0x10
204 /*0x14-0xFF reserved*/
207 * PCI Control Registers
210 /*0x0 - 0x1 reserved*/
211 #define VIA_CRDR_PCICLKGATT 0x2
214 * 0 : Soft reset all the controller and it will be de-asserted automatically
215 * 1 : Soft reset is de-asserted
217 #define VIA_CRDR_PCICLKGATT_SFTRST 0x01
219 * 3V3 : Pad power select
222 * NOTE : No mater what the actual value should be, this bit always
223 * read as 0. This is a hardware bug.
225 #define VIA_CRDR_PCICLKGATT_3V3 0x10
227 * PAD_PWRON : Pad Power on/off select
230 * NOTE : No mater what the actual value should be, this bit always
231 * read as 0. This is a hardware bug.
233 #define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20
235 #define VIA_CRDR_PCISDCCLK 0x5
237 #define VIA_CRDR_PCIDMACLK 0x7
238 #define VIA_CRDR_PCIDMACLK_SDC 0x2
240 #define VIA_CRDR_PCIINTCTRL 0x8
241 #define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04
243 #define VIA_CRDR_PCIINTSTATUS 0x9
244 #define VIA_CRDR_PCIINTSTATUS_SDC 0x04
246 #define VIA_CRDR_PCITMOCTRL 0xa
247 #define VIA_CRDR_PCITMOCTRL_NO 0x0
248 #define VIA_CRDR_PCITMOCTRL_32US 0x1
249 #define VIA_CRDR_PCITMOCTRL_256US 0x2
250 #define VIA_CRDR_PCITMOCTRL_1024US 0x3
251 #define VIA_CRDR_PCITMOCTRL_256MS 0x4
252 #define VIA_CRDR_PCITMOCTRL_512MS 0x5
253 #define VIA_CRDR_PCITMOCTRL_1024MS 0x6
255 /*0xB-0xFF reserved*/
257 enum PCI_HOST_CLK_CONTROL {
295 struct via_crdr_mmc_host {
296 struct mmc_host *mmc;
297 struct mmc_request *mrq;
298 struct mmc_command *cmd;
299 struct mmc_data *data;
301 void __iomem *mmiobase;
302 void __iomem *sdhc_mmiobase;
303 void __iomem *ddma_mmiobase;
304 void __iomem *pcictrl_mmiobase;
306 struct pcictrlreg pm_pcictrl_reg;
307 struct sdhcreg pm_sdhc_reg;
309 struct work_struct carddet_work;
310 struct tasklet_struct finish_tasklet;
312 struct timer_list timer;
319 /* some devices need a very long delay for power to stabilize */
320 #define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001
322 #define VIA_CMD_TIMEOUT_MS 1000
324 static const struct pci_device_id via_ids[] = {
325 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530,
326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
330 MODULE_DEVICE_TABLE(pci, via_ids);
332 static void via_print_sdchc(struct via_crdr_mmc_host *host)
334 void __iomem *addrbase = host->sdhc_mmiobase;
336 pr_debug("SDC MMIO Registers:\n");
337 pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n",
338 readl(addrbase + VIA_CRDR_SDCTRL),
339 readl(addrbase + VIA_CRDR_SDCARG),
340 readl(addrbase + VIA_CRDR_SDBUSMODE));
341 pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n",
342 readl(addrbase + VIA_CRDR_SDBLKLEN),
343 readl(addrbase + VIA_CRDR_SDCURBLKCNT),
344 readl(addrbase + VIA_CRDR_SDINTMASK));
345 pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n",
346 readl(addrbase + VIA_CRDR_SDSTATUS),
347 readl(addrbase + VIA_CRDR_SDCLKSEL),
348 readl(addrbase + VIA_CRDR_SDEXTCTRL));
351 static void via_print_pcictrl(struct via_crdr_mmc_host *host)
353 void __iomem *addrbase = host->pcictrl_mmiobase;
355 pr_debug("PCI Control Registers:\n");
356 pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n",
357 readb(addrbase + VIA_CRDR_PCICLKGATT),
358 readb(addrbase + VIA_CRDR_PCISDCCLK),
359 readb(addrbase + VIA_CRDR_PCIDMACLK));
360 pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n",
361 readb(addrbase + VIA_CRDR_PCIINTCTRL),
362 readb(addrbase + VIA_CRDR_PCIINTSTATUS));
365 static void via_save_pcictrlreg(struct via_crdr_mmc_host *host)
367 struct pcictrlreg *pm_pcictrl_reg;
368 void __iomem *addrbase;
370 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
371 addrbase = host->pcictrl_mmiobase;
373 pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT);
374 pm_pcictrl_reg->pciclkgat_reg |=
375 VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
376 pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK);
377 pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK);
378 pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL);
379 pm_pcictrl_reg->pciintstatus_reg =
380 readb(addrbase + VIA_CRDR_PCIINTSTATUS);
381 pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL);
384 static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host)
386 struct pcictrlreg *pm_pcictrl_reg;
387 void __iomem *addrbase;
389 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
390 addrbase = host->pcictrl_mmiobase;
392 writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT);
393 writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK);
394 writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK);
395 writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL);
396 writeb(pm_pcictrl_reg->pciintstatus_reg,
397 addrbase + VIA_CRDR_PCIINTSTATUS);
398 writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL);
401 static void via_save_sdcreg(struct via_crdr_mmc_host *host)
403 struct sdhcreg *pm_sdhc_reg;
404 void __iomem *addrbase;
406 pm_sdhc_reg = &(host->pm_sdhc_reg);
407 addrbase = host->sdhc_mmiobase;
409 pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL);
410 pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG);
411 pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE);
412 pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN);
413 pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT);
414 pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK);
415 pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS);
416 pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO);
417 pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL);
418 pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL);
421 static void via_restore_sdcreg(struct via_crdr_mmc_host *host)
423 struct sdhcreg *pm_sdhc_reg;
424 void __iomem *addrbase;
426 pm_sdhc_reg = &(host->pm_sdhc_reg);
427 addrbase = host->sdhc_mmiobase;
429 writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
430 writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
431 writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE);
432 writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN);
433 writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT);
434 writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
435 writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS);
436 writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
437 writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
438 writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
441 static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost)
443 if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY)
449 static void via_set_ddma(struct via_crdr_mmc_host *host,
450 dma_addr_t dmaaddr, u32 count, int dir, int enirq)
452 void __iomem *addrbase;
456 ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ;
459 ctrl_data |= VIA_CRDR_DMACTRL_DIR;
461 addrbase = host->ddma_mmiobase;
463 writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD);
464 writel(count, addrbase + VIA_CRDR_DMACOUNTER);
465 writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL);
466 writel(0x01, addrbase + VIA_CRDR_DMASTART);
468 /* It seems that our DMA can not work normally with 375kHz clock */
469 /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */
470 addrbase = host->pcictrl_mmiobase;
471 if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) {
472 dev_info(host->mmc->parent, "forcing card speed to 8MHz\n");
473 writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK);
477 static void via_sdc_preparedata(struct via_crdr_mmc_host *host,
478 struct mmc_data *data)
480 void __iomem *addrbase;
487 BUG_ON(data->blksz > host->mmc->max_blk_size);
488 BUG_ON(data->blocks > host->mmc->max_blk_count);
492 count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
493 ((data->flags & MMC_DATA_READ) ?
494 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
497 via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg),
498 (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1);
500 addrbase = host->sdhc_mmiobase;
502 blk_reg = data->blksz - 1;
503 blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
504 blk_reg |= (data->blocks) << 16;
506 writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN);
509 static void via_sdc_get_response(struct via_crdr_mmc_host *host,
510 struct mmc_command *cmd)
512 void __iomem *addrbase = host->sdhc_mmiobase;
513 u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0);
514 u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1);
515 u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2);
516 u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3);
518 if (cmd->flags & MMC_RSP_136) {
519 cmd->resp[0] = ((u8) (dwdata1)) |
520 (((u8) (dwdata0 >> 24)) << 8) |
521 (((u8) (dwdata0 >> 16)) << 16) |
522 (((u8) (dwdata0 >> 8)) << 24);
524 cmd->resp[1] = ((u8) (dwdata2)) |
525 (((u8) (dwdata1 >> 24)) << 8) |
526 (((u8) (dwdata1 >> 16)) << 16) |
527 (((u8) (dwdata1 >> 8)) << 24);
529 cmd->resp[2] = ((u8) (dwdata3)) |
530 (((u8) (dwdata2 >> 24)) << 8) |
531 (((u8) (dwdata2 >> 16)) << 16) |
532 (((u8) (dwdata2 >> 8)) << 24);
534 cmd->resp[3] = 0xff |
535 ((((u8) (dwdata3 >> 24))) << 8) |
536 (((u8) (dwdata3 >> 16)) << 16) |
537 (((u8) (dwdata3 >> 8)) << 24);
540 cmd->resp[0] = ((dwdata0 & 0xff) << 24) |
541 (((dwdata0 >> 8) & 0xff) << 16) |
542 (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff);
545 cmd->resp[1] = ((dwdata1 & 0xff) << 24) |
546 (((dwdata1 >> 8) & 0xff) << 16) |
547 (((dwdata1 >> 16) & 0xff) << 8);
551 static void via_sdc_send_command(struct via_crdr_mmc_host *host,
552 struct mmc_command *cmd)
554 void __iomem *addrbase;
555 struct mmc_data *data;
556 unsigned int timeout_ms;
564 timeout_ms = cmd->busy_timeout ? cmd->busy_timeout : VIA_CMD_TIMEOUT_MS;
565 mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout_ms));
568 cmdctrl = cmd->opcode << 8;
571 switch (mmc_resp_type(cmd)) {
573 cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE;
576 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1;
579 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B;
582 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2;
585 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3;
588 pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc));
595 via_sdc_preparedata(host, data);
598 if (data->blocks > 1) {
599 if (data->flags & MMC_DATA_WRITE) {
600 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
601 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR;
603 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD;
606 if (data->flags & MMC_DATA_WRITE) {
607 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
608 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR;
610 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD;
615 if (cmd == host->mrq->stop)
616 cmdctrl |= VIA_CRDR_SDCTRL_STOP;
618 cmdctrl |= VIA_CRDR_SDCTRL_START;
620 addrbase = host->sdhc_mmiobase;
621 writel(cmd->arg, addrbase + VIA_CRDR_SDCARG);
622 writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL);
625 static void via_sdc_finish_data(struct via_crdr_mmc_host *host)
627 struct mmc_data *data;
635 data->bytes_xfered = 0;
637 data->bytes_xfered = data->blocks * data->blksz;
639 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
640 ((data->flags & MMC_DATA_READ) ?
641 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
644 via_sdc_send_command(host, data->stop);
646 tasklet_schedule(&host->finish_tasklet);
649 static void via_sdc_finish_command(struct via_crdr_mmc_host *host)
651 via_sdc_get_response(host, host->cmd);
653 host->cmd->error = 0;
655 if (!host->cmd->data)
656 tasklet_schedule(&host->finish_tasklet);
661 static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq)
663 void __iomem *addrbase;
664 struct via_crdr_mmc_host *host;
668 host = mmc_priv(mmc);
670 spin_lock_irqsave(&host->lock, flags);
672 addrbase = host->pcictrl_mmiobase;
673 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
675 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
676 status &= VIA_CRDR_SDSTS_W1C_MASK;
677 writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
679 WARN_ON(host->mrq != NULL);
682 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
683 if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) {
684 host->mrq->cmd->error = -ENOMEDIUM;
685 tasklet_schedule(&host->finish_tasklet);
687 via_sdc_send_command(host, mrq->cmd);
690 spin_unlock_irqrestore(&host->lock, flags);
693 static void via_sdc_set_power(struct via_crdr_mmc_host *host,
694 unsigned short power, unsigned int on)
699 spin_lock_irqsave(&host->lock, flags);
701 host->power = (1 << power);
703 gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
704 if (host->power == MMC_VDD_165_195)
705 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
707 gatt |= VIA_CRDR_PCICLKGATT_3V3;
709 gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON;
711 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
712 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
714 spin_unlock_irqrestore(&host->lock, flags);
716 via_pwron_sleep(host);
719 static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
721 struct via_crdr_mmc_host *host;
723 void __iomem *addrbase;
724 u32 org_data, sdextctrl;
727 host = mmc_priv(mmc);
729 spin_lock_irqsave(&host->lock, flags);
731 addrbase = host->sdhc_mmiobase;
732 org_data = readl(addrbase + VIA_CRDR_SDBUSMODE);
733 sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL);
735 if (ios->bus_width == MMC_BUS_WIDTH_1)
736 org_data &= ~VIA_CRDR_SDMODE_4BIT;
738 org_data |= VIA_CRDR_SDMODE_4BIT;
740 if (ios->power_mode == MMC_POWER_OFF)
741 org_data &= ~VIA_CRDR_SDMODE_CLK_ON;
743 org_data |= VIA_CRDR_SDMODE_CLK_ON;
745 if (ios->timing == MMC_TIMING_SD_HS)
746 sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD;
748 sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD;
750 writel(org_data, addrbase + VIA_CRDR_SDBUSMODE);
751 writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL);
753 if (ios->clock >= 48000000)
755 else if (ios->clock >= 33000000)
757 else if (ios->clock >= 24000000)
759 else if (ios->clock >= 16000000)
761 else if (ios->clock >= 12000000)
763 else if (ios->clock >= 8000000)
766 clock = PCI_CLK_375K;
768 addrbase = host->pcictrl_mmiobase;
769 if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock)
770 writeb(clock, addrbase + VIA_CRDR_PCISDCCLK);
772 spin_unlock_irqrestore(&host->lock, flags);
774 if (ios->power_mode != MMC_POWER_OFF)
775 via_sdc_set_power(host, ios->vdd, 1);
777 via_sdc_set_power(host, ios->vdd, 0);
780 static int via_sdc_get_ro(struct mmc_host *mmc)
782 struct via_crdr_mmc_host *host;
786 host = mmc_priv(mmc);
788 spin_lock_irqsave(&host->lock, flags);
790 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
792 spin_unlock_irqrestore(&host->lock, flags);
794 return !(status & VIA_CRDR_SDSTS_WP);
797 static const struct mmc_host_ops via_sdc_ops = {
798 .request = via_sdc_request,
799 .set_ios = via_sdc_set_ios,
800 .get_ro = via_sdc_get_ro,
803 static void via_reset_pcictrl(struct via_crdr_mmc_host *host)
808 spin_lock_irqsave(&host->lock, flags);
810 via_save_pcictrlreg(host);
811 via_save_sdcreg(host);
813 spin_unlock_irqrestore(&host->lock, flags);
815 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
816 if (host->power == MMC_VDD_165_195)
817 gatt &= VIA_CRDR_PCICLKGATT_3V3;
819 gatt |= VIA_CRDR_PCICLKGATT_3V3;
820 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
821 via_pwron_sleep(host);
822 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
823 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
826 spin_lock_irqsave(&host->lock, flags);
828 via_restore_pcictrlreg(host);
829 via_restore_sdcreg(host);
831 spin_unlock_irqrestore(&host->lock, flags);
834 static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask)
836 BUG_ON(intmask == 0);
839 pr_err("%s: Got command interrupt 0x%x even "
840 "though no command operation was in progress.\n",
841 mmc_hostname(host->mmc), intmask);
845 if (intmask & VIA_CRDR_SDSTS_CRTO)
846 host->cmd->error = -ETIMEDOUT;
847 else if (intmask & VIA_CRDR_SDSTS_SC)
848 host->cmd->error = -EILSEQ;
850 if (host->cmd->error)
851 tasklet_schedule(&host->finish_tasklet);
852 else if (intmask & VIA_CRDR_SDSTS_CRD)
853 via_sdc_finish_command(host);
856 static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask)
858 BUG_ON(intmask == 0);
863 if (intmask & VIA_CRDR_SDSTS_DT)
864 host->data->error = -ETIMEDOUT;
865 else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC))
866 host->data->error = -EILSEQ;
868 via_sdc_finish_data(host);
871 static irqreturn_t via_sdc_isr(int irq, void *dev_id)
873 struct via_crdr_mmc_host *sdhost = dev_id;
874 void __iomem *addrbase;
882 spin_lock(&sdhost->lock);
884 addrbase = sdhost->pcictrl_mmiobase;
885 pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS);
886 if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) {
891 addrbase = sdhost->sdhc_mmiobase;
892 sd_status = readw(addrbase + VIA_CRDR_SDSTATUS);
893 sd_status &= VIA_CRDR_SDSTS_INT_MASK;
894 sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK;
900 if (sd_status & VIA_CRDR_SDSTS_CIR) {
901 writew(sd_status & VIA_CRDR_SDSTS_CIR,
902 addrbase + VIA_CRDR_SDSTATUS);
904 schedule_work(&sdhost->carddet_work);
907 sd_status &= ~VIA_CRDR_SDSTS_CIR;
908 if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) {
909 writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK,
910 addrbase + VIA_CRDR_SDSTATUS);
911 via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK);
913 if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) {
914 writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK,
915 addrbase + VIA_CRDR_SDSTATUS);
916 via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK);
919 sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK);
921 pr_err("%s: Unexpected interrupt 0x%x\n",
922 mmc_hostname(sdhost->mmc), sd_status);
923 writew(sd_status, addrbase + VIA_CRDR_SDSTATUS);
926 result = IRQ_HANDLED;
929 spin_unlock(&sdhost->lock);
934 static void via_sdc_timeout(struct timer_list *t)
936 struct via_crdr_mmc_host *sdhost;
939 sdhost = from_timer(sdhost, t, timer);
941 spin_lock_irqsave(&sdhost->lock, flags);
944 pr_err("%s: Timeout waiting for hardware interrupt."
945 "cmd:0x%x\n", mmc_hostname(sdhost->mmc),
946 sdhost->mrq->cmd->opcode);
949 writel(VIA_CRDR_DMACTRL_SFTRST,
950 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
951 sdhost->data->error = -ETIMEDOUT;
952 via_sdc_finish_data(sdhost);
955 sdhost->cmd->error = -ETIMEDOUT;
957 sdhost->mrq->cmd->error = -ETIMEDOUT;
958 tasklet_schedule(&sdhost->finish_tasklet);
962 spin_unlock_irqrestore(&sdhost->lock, flags);
965 static void via_sdc_tasklet_finish(unsigned long param)
967 struct via_crdr_mmc_host *host;
969 struct mmc_request *mrq;
971 host = (struct via_crdr_mmc_host *)param;
973 spin_lock_irqsave(&host->lock, flags);
975 del_timer(&host->timer);
981 spin_unlock_irqrestore(&host->lock, flags);
983 mmc_request_done(host->mmc, mrq);
986 static void via_sdc_card_detect(struct work_struct *work)
988 struct via_crdr_mmc_host *host;
989 void __iomem *addrbase;
993 host = container_of(work, struct via_crdr_mmc_host, carddet_work);
995 addrbase = host->ddma_mmiobase;
996 writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL);
998 spin_lock_irqsave(&host->lock, flags);
1000 addrbase = host->pcictrl_mmiobase;
1001 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
1003 addrbase = host->sdhc_mmiobase;
1004 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1005 if (!(status & VIA_CRDR_SDSTS_SLOTG)) {
1007 pr_err("%s: Card removed during transfer!\n",
1008 mmc_hostname(host->mmc));
1009 host->mrq->cmd->error = -ENOMEDIUM;
1010 tasklet_schedule(&host->finish_tasklet);
1013 spin_unlock_irqrestore(&host->lock, flags);
1015 via_reset_pcictrl(host);
1017 spin_lock_irqsave(&host->lock, flags);
1020 spin_unlock_irqrestore(&host->lock, flags);
1022 via_print_pcictrl(host);
1023 via_print_sdchc(host);
1025 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1028 static void via_init_mmc_host(struct via_crdr_mmc_host *host)
1030 struct mmc_host *mmc = host->mmc;
1031 void __iomem *addrbase;
1035 timer_setup(&host->timer, via_sdc_timeout, 0);
1037 spin_lock_init(&host->lock);
1039 mmc->f_min = VIA_CRDR_MIN_CLOCK;
1040 mmc->f_max = VIA_CRDR_MAX_CLOCK;
1041 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1042 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED;
1043 mmc->ops = &via_sdc_ops;
1045 /*Hardware cannot do scatter lists*/
1048 mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH;
1049 mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT;
1051 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
1052 mmc->max_req_size = mmc->max_seg_size;
1054 INIT_WORK(&host->carddet_work, via_sdc_card_detect);
1056 tasklet_init(&host->finish_tasklet, via_sdc_tasklet_finish,
1057 (unsigned long)host);
1059 addrbase = host->sdhc_mmiobase;
1060 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1063 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1064 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1066 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1067 status &= VIA_CRDR_SDSTS_W1C_MASK;
1068 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1070 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1071 status |= VIA_CRDR_SDSTS_CFE;
1072 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1074 writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL);
1076 writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK);
1080 static int via_sd_probe(struct pci_dev *pcidev,
1081 const struct pci_device_id *id)
1083 struct mmc_host *mmc;
1084 struct via_crdr_mmc_host *sdhost;
1090 ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n",
1091 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1092 (int)pcidev->revision);
1094 ret = pci_enable_device(pcidev);
1098 ret = pci_request_regions(pcidev, DRV_NAME);
1102 pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0);
1103 pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0);
1105 mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev);
1111 sdhost = mmc_priv(mmc);
1113 dev_set_drvdata(&pcidev->dev, sdhost);
1115 len = pci_resource_len(pcidev, 0);
1116 base = pci_resource_start(pcidev, 0);
1117 sdhost->mmiobase = ioremap(base, len);
1118 if (!sdhost->mmiobase) {
1123 sdhost->sdhc_mmiobase =
1124 sdhost->mmiobase + VIA_CRDR_SDC_OFF;
1125 sdhost->ddma_mmiobase =
1126 sdhost->mmiobase + VIA_CRDR_DDMA_OFF;
1127 sdhost->pcictrl_mmiobase =
1128 sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF;
1130 sdhost->power = MMC_VDD_165_195;
1132 gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
1133 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1134 via_pwron_sleep(sdhost);
1135 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1136 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1139 via_init_mmc_host(sdhost);
1142 request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME,
1147 writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN,
1148 sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1149 writeb(VIA_CRDR_PCITMOCTRL_1024MS,
1150 sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL);
1152 /* device-specific quirks */
1153 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
1154 pcidev->subsystem_device == 0x3891)
1155 sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY;
1157 ret = mmc_add_host(mmc);
1164 iounmap(sdhost->mmiobase);
1166 dev_set_drvdata(&pcidev->dev, NULL);
1169 pci_release_regions(pcidev);
1171 pci_disable_device(pcidev);
1176 static void via_sd_remove(struct pci_dev *pcidev)
1178 struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev);
1179 unsigned long flags;
1182 spin_lock_irqsave(&sdhost->lock, flags);
1184 /* Ensure we don't accept more commands from mmc layer */
1187 /* Disable generating further interrupts */
1188 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1191 pr_err("%s: Controller removed during "
1192 "transfer\n", mmc_hostname(sdhost->mmc));
1194 /* make sure all DMA is stopped */
1195 writel(VIA_CRDR_DMACTRL_SFTRST,
1196 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
1197 sdhost->mrq->cmd->error = -ENOMEDIUM;
1198 if (sdhost->mrq->stop)
1199 sdhost->mrq->stop->error = -ENOMEDIUM;
1200 tasklet_schedule(&sdhost->finish_tasklet);
1202 spin_unlock_irqrestore(&sdhost->lock, flags);
1204 mmc_remove_host(sdhost->mmc);
1206 free_irq(pcidev->irq, sdhost);
1208 del_timer_sync(&sdhost->timer);
1210 tasklet_kill(&sdhost->finish_tasklet);
1212 /* switch off power */
1213 gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1214 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
1215 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1217 iounmap(sdhost->mmiobase);
1218 dev_set_drvdata(&pcidev->dev, NULL);
1219 mmc_free_host(sdhost->mmc);
1220 pci_release_regions(pcidev);
1221 pci_disable_device(pcidev);
1224 ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n",
1225 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1228 static void __maybe_unused via_init_sdc_pm(struct via_crdr_mmc_host *host)
1230 struct sdhcreg *pm_sdhcreg;
1231 void __iomem *addrbase;
1235 pm_sdhcreg = &(host->pm_sdhc_reg);
1236 addrbase = host->sdhc_mmiobase;
1238 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1240 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1241 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1243 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1244 status &= VIA_CRDR_SDSTS_W1C_MASK;
1245 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1247 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1248 status |= VIA_CRDR_SDSTS_CFE;
1249 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1251 writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
1252 writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
1253 writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
1254 writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
1255 writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
1256 writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
1258 via_print_pcictrl(host);
1259 via_print_sdchc(host);
1262 static int __maybe_unused via_sd_suspend(struct device *dev)
1264 struct via_crdr_mmc_host *host;
1265 unsigned long flags;
1267 host = dev_get_drvdata(dev);
1269 spin_lock_irqsave(&host->lock, flags);
1270 via_save_pcictrlreg(host);
1271 via_save_sdcreg(host);
1272 spin_unlock_irqrestore(&host->lock, flags);
1274 device_wakeup_enable(dev);
1279 static int __maybe_unused via_sd_resume(struct device *dev)
1281 struct via_crdr_mmc_host *sdhost;
1285 sdhost = dev_get_drvdata(dev);
1287 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
1288 if (sdhost->power == MMC_VDD_165_195)
1289 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
1291 gatt |= VIA_CRDR_PCICLKGATT_3V3;
1292 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1293 via_pwron_sleep(sdhost);
1294 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1295 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1300 via_restore_pcictrlreg(sdhost);
1301 via_init_sdc_pm(sdhost);
1306 static SIMPLE_DEV_PM_OPS(via_sd_pm_ops, via_sd_suspend, via_sd_resume);
1308 static struct pci_driver via_sd_driver = {
1310 .id_table = via_ids,
1311 .probe = via_sd_probe,
1312 .remove = via_sd_remove,
1313 .driver.pm = &via_sd_pm_ops,
1316 module_pci_driver(via_sd_driver);
1318 MODULE_LICENSE("GPL");
1319 MODULE_AUTHOR("VIA Technologies Inc.");
1320 MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver");