drivers/mmc/host/uniphier-sd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (C) 2017-2018 Socionext Inc.
   4 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/bitops.h>
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/mfd/tmio.h>
  12 #include <linux/mmc/host.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/reset.h>
  19
  20 #include "tmio_mmc.h"
  21
  22 #define   UNIPHIER_SD_CLK_CTL_DIV1024           BIT(16)
  23 #define   UNIPHIER_SD_CLK_CTL_DIV1              BIT(10)
  24 #define   UNIPHIER_SD_CLKCTL_OFFEN              BIT(9)  // auto SDCLK stop
  25 #define UNIPHIER_SD_CC_EXT_MODE         0x1b0
  26 #define   UNIPHIER_SD_CC_EXT_MODE_DMA           BIT(1)
  27 #define UNIPHIER_SD_HOST_MODE           0x1c8
  28 #define UNIPHIER_SD_VOLT                0x1e4
  29 #define   UNIPHIER_SD_VOLT_MASK                 GENMASK(1, 0)
  30 #define   UNIPHIER_SD_VOLT_OFF                  0
  31 #define   UNIPHIER_SD_VOLT_330                  1       // 3.3V signal
  32 #define   UNIPHIER_SD_VOLT_180                  2       // 1.8V signal
  33 #define UNIPHIER_SD_DMA_MODE            0x410
  34 #define   UNIPHIER_SD_DMA_MODE_DIR_MASK         GENMASK(17, 16)
  35 #define   UNIPHIER_SD_DMA_MODE_DIR_TO_DEV       0
  36 #define   UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV     1
  37 #define   UNIPHIER_SD_DMA_MODE_WIDTH_MASK       GENMASK(5, 4)
  38 #define   UNIPHIER_SD_DMA_MODE_WIDTH_8          0
  39 #define   UNIPHIER_SD_DMA_MODE_WIDTH_16         1
  40 #define   UNIPHIER_SD_DMA_MODE_WIDTH_32         2
  41 #define   UNIPHIER_SD_DMA_MODE_WIDTH_64         3
  42 #define   UNIPHIER_SD_DMA_MODE_ADDR_INC         BIT(0)  // 1: inc, 0: fixed
  43 #define UNIPHIER_SD_DMA_CTL             0x414
  44 #define   UNIPHIER_SD_DMA_CTL_START     BIT(0)  // start DMA (auto cleared)
  45 #define UNIPHIER_SD_DMA_RST             0x418
  46 #define   UNIPHIER_SD_DMA_RST_CH1       BIT(9)
  47 #define   UNIPHIER_SD_DMA_RST_CH0       BIT(8)
  48 #define UNIPHIER_SD_DMA_ADDR_L          0x440
  49 #define UNIPHIER_SD_DMA_ADDR_H          0x444
  50
  51 /*
  52  * IP is extended to support various features: built-in DMA engine,
  53  * 1/1024 divisor, etc.
  54  */
  55 #define UNIPHIER_SD_CAP_EXTENDED_IP             BIT(0)
  56 /* RX channel of the built-in DMA controller is broken (Pro5) */
  57 #define UNIPHIER_SD_CAP_BROKEN_DMA_RX           BIT(1)
  58
  59 struct uniphier_sd_priv {
  60         struct tmio_mmc_data tmio_data;
  61         struct pinctrl *pinctrl;
  62         struct pinctrl_state *pinstate_uhs;
  63         struct clk *clk;
  64         struct reset_control *rst;
  65         struct reset_control *rst_br;
  66         struct reset_control *rst_hw;
  67         struct dma_chan *chan;
  68         enum dma_data_direction dma_dir;
  69         unsigned long clk_rate;
  70         unsigned long caps;
  71 };
  72
  73 static void *uniphier_sd_priv(struct tmio_mmc_host *host)
  74 {
  75         return container_of(host->pdata, struct uniphier_sd_priv, tmio_data);
  76 }
  77
  78 static void uniphier_sd_dma_endisable(struct tmio_mmc_host *host, int enable)
  79 {
  80         sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
  81 }
  82
  83 /* external DMA engine */
  84 static void uniphier_sd_external_dma_issue(unsigned long arg)
  85 {
  86         struct tmio_mmc_host *host = (void *)arg;
  87         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  88
  89         uniphier_sd_dma_endisable(host, 1);
  90         dma_async_issue_pending(priv->chan);
  91 }
  92
  93 static void uniphier_sd_external_dma_callback(void *param,
  94                                         const struct dmaengine_result *result)
  95 {
  96         struct tmio_mmc_host *host = param;
  97         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  98         unsigned long flags;
  99
 100         dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
 101                      priv->dma_dir);
 102
 103         spin_lock_irqsave(&host->lock, flags);
 104
 105         if (result->result == DMA_TRANS_NOERROR) {
 106                 /*
 107                  * When the external DMA engine is enabled, strangely enough,
 108                  * the DATAEND flag can be asserted even if the DMA engine has
 109                  * not been kicked yet.  Enable the TMIO_STAT_DATAEND irq only
 110                  * after we make sure the DMA engine finishes the transfer,
 111                  * hence, in this callback.
 112                  */
 113                 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
 114         } else {
 115                 host->data->error = -ETIMEDOUT;
 116                 tmio_mmc_do_data_irq(host);
 117         }
 118
 119         spin_unlock_irqrestore(&host->lock, flags);
 120 }
 121
 122 static void uniphier_sd_external_dma_start(struct tmio_mmc_host *host,
 123                                            struct mmc_data *data)
 124 {
 125         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
 126         enum dma_transfer_direction dma_tx_dir;
 127         struct dma_async_tx_descriptor *desc;
 128         dma_cookie_t cookie;
 129         int sg_len;
 130
 131         if (!priv->chan)
 132                 goto force_pio;
 133
 134         if (data->flags & MMC_DATA_READ) {
 135                 priv->dma_dir = DMA_FROM_DEVICE;
 136                 dma_tx_dir = DMA_DEV_TO_MEM;
 137         } else {
 138                 priv->dma_dir = DMA_TO_DEVICE;
 139                 dma_tx_dir = DMA_MEM_TO_DEV;
 140         }
 141
 142         sg_len = dma_map_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
 143                             priv->dma_dir);
 144         if (sg_len == 0)
 145                 goto force_pio;
 146
 147         desc = dmaengine_prep_slave_sg(priv->chan, host->sg_ptr, sg_len,
 148                                        dma_tx_dir, DMA_CTRL_ACK);
 149         if (!desc)
 150                 goto unmap_sg;
 151
 152         desc->callback_result = uniphier_sd_external_dma_callback;
 153         desc->callback_param = host;
 154
 155         cookie = dmaengine_submit(desc);
 156         if (cookie < 0)
 157                 goto unmap_sg;
 158
 159         host->dma_on = true;
 160
 161         return;
 162
 163 unmap_sg:
 164         dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
 165                      priv->dma_dir);
 166 force_pio:
 167         uniphier_sd_dma_endisable(host, 0);
 168 }
 169
 170 static void uniphier_sd_external_dma_enable(struct tmio_mmc_host *host,
 171                                             bool enable)
 172 {
 173 }
 174
 175 static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host,
 176                                              struct tmio_mmc_data *pdata)
 177 {
 178         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
 179         struct dma_chan *chan;
 180
 181         chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx");
 182         if (IS_ERR(chan)) {
 183                 dev_warn(mmc_dev(host->mmc),
 184                          "failed to request DMA channel. falling back to PIO\n");
 185                 return; /* just use PIO even for -EPROBE_DEFER */
 186         }
 187
 188         /* this driver uses a single channel for both RX an TX */
 189         priv->chan = chan;
 190         host->chan_rx = chan;
 191         host->chan_tx = chan;
 192
 193         tasklet_init(&host->dma_issue, uniphier_sd_external_dma_issue,
 194                      (unsigned long)host);
 195 }
 196
 197 static void uniphier_sd_external_dma_release(struct tmio_mmc_host *host)
 198 {
 199         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
 200
 201         if (priv->chan)
 202                 dma_release_channel(priv->chan);
 203 }
 204
 205 static void uniphier_sd_external_dma_abort(struct tmio_mmc_host *host)
 206 {
 207         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
 208
 209         uniphier_sd_dma_endisable(host, 0);
 210
 211         if (priv->chan)
 212                 dmaengine_terminate_sync(priv->chan);
 213 }
 214
 215 static void uniphier_sd_external_dma_dataend(struct tmio_mmc_host *host)
 216 {
 217         uniphier_sd_dma_endisable(host, 0);
 218
 219         tmio_mmc_do_data_irq(host);
 220 }
 221
 222 static const struct tmio_mmc_dma_ops uniphier_sd_external_dma_ops = {
 223         .start = uniphier_sd_external_dma_start,
 224         .enable = uniphier_sd_external_dma_enable,
 225         .request = uniphier_sd_external_dma_request,
 226         .release = uniphier_sd_external_dma_release,
 227         .abort = uniphier_sd_external_dma_abort,
 228         .dataend = uniphier_sd_external_dma_dataend,
 229 };
 230
 231 static void uniphier_sd_internal_dma_issue(unsigned long arg)
 232 {
 233         struct tmio_mmc_host *host = (void *)arg;
 234         unsigned long flags;
 235
 236         spin_lock_irqsave(&host->lock, flags);
 237         tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
 238         spin_unlock_irqrestore(&host->lock, flags);
 239
 240         uniphier_sd_dma_endisable(host, 1);
 241         writel(UNIPHIER_SD_DMA_CTL_START, host->ctl + UNIPHIER_SD_DMA_CTL);
 242 }
 243
 244 static void uniphier_sd_internal_dma_start(struct tmio_mmc_host *host,
 245                                            struct mmc_data *data)
 246 {
 247         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
 248         struct scatterlist *sg = host->sg_ptr;
 249         dma_addr_t dma_addr;
 250         unsigned int dma_mode_dir;
 251         u32 dma_mode;
 252         int sg_len;
 253
 254         if ((data->flags & MMC_DATA_READ) && !host->chan_rx)
 255                 goto force_pio;
 256
 257         if (WARN_ON(host->sg_len != 1))
 258                 goto force_pio;
 259
 260         if (!IS_ALIGNED(sg->offset, 8))
 261                 goto force_pio;
 262
 263         if (data->flags & MMC_DATA_READ) {
 264                 priv->dma_dir = DMA_FROM_DEVICE;
 265                 dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV;
 266         } else {
 267                 priv->dma_dir = DMA_TO_DEVICE;
 268                 dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_TO_DEV;
 269         }
 270
 271         sg_len = dma_map_sg(mmc_dev(host->mmc), sg, 1, priv->dma_dir);
 272         if (sg_len == 0)
 273                 goto force_pio;
 274
 275         dma_mode = FIELD_PREP(UNIPHIER_SD_DMA_MODE_DIR_MASK, dma_mode_dir);
 276         dma_mode |= FIELD_PREP(UNIPHIER_SD_DMA_MODE_WIDTH_MASK,
 277                                UNIPHIER_SD_DMA_MODE_WIDTH_64);
 278         dma_mode |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
 279
 280         writel(dma_mode, host->ctl + UNIPHIER_SD_DMA_MODE);
 281
 282         dma_addr = sg_dma_address(data->sg);
 283         writel(lower_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_L);
 284         writel(upper_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_H);
 285
 286         host->dma_on = true;
 287
 288         return;
 289 force_pio:
 290         uniphier_sd_dma_endisable(host, 0);
 291 }
 292
 293 static void uniphier_sd_internal_dma_enable(struct tmio_mmc_host *host,
 294                                             bool enable)
 295 {
 296 }
 297
 298 static void uniphier_sd_internal_dma_request(struct tmio_mmc_host *host,
 299                                              struct tmio_mmc_data *pdata)
 300 {
 301         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
 302
 303         /*
 304          * Due to a hardware bug, Pro5 cannot use DMA for RX.
 305          * We can still use DMA for TX, but PIO for RX.
 306          */
 307         if (!(priv->caps & UNIPHIER_SD_CAP_BROKEN_DMA_RX))
 308                 host->chan_rx = (void *)0xdeadbeaf;
 309
 310         host->chan_tx = (void *)0xdeadbeaf;
 311
 312         tasklet_init(&host->dma_issue, uniphier_sd_internal_dma_issue,
 313                      (unsigned long)host);
 314 }
 315
 316 static void uniphier_sd_internal_dma_release(struct tmio_mmc_host *host)
 317 {
 318         /* Each value is set to zero to assume "disabling" each DMA */
 319         host->chan_rx = NULL;
 320         host->chan_tx = NULL;
 321 }
 322
 323 static void uniphier_sd_internal_dma_abort(struct tmio_mmc_host *host)
 324 {
 325         u32 tmp;
 326
 327         uniphier_sd_dma_endisable(host, 0);
 328
 329         tmp = readl(host->ctl + UNIPHIER_SD_DMA_RST);
 330         tmp &= ~(UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0);
 331         writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
 332
 333         tmp |= UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0;
 334         writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
 335 }
 336
 337 static void uniphier_sd_internal_dma_dataend(struct tmio_mmc_host *host)
 338 {
 339         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
 340
 341         uniphier_sd_dma_endisable(host, 0);
 342         dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, 1, priv->dma_dir);
 343
 344         tmio_mmc_do_data_irq(host);
 345 }
 346
 347 static const struct tmio_mmc_dma_ops uniphier_sd_internal_dma_ops = {
 348         .start = uniphier_sd_internal_dma_start,
 349         .enable = uniphier_sd_internal_dma_enable,
 350         .request = uniphier_sd_internal_dma_request,
 351         .release = uniphier_sd_internal_dma_release,
 352         .abort = uniphier_sd_internal_dma_abort,
 353         .dataend = uniphier_sd_internal_dma_dataend,
 354 };
 355
 356 static int uniphier_sd_clk_enable(struct tmio_mmc_host *host)
 357 {
 358         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
 359         struct mmc_host *mmc = host->mmc;
 360         int ret;
 361
 362         ret = clk_prepare_enable(priv->clk);
 363         if (ret)
 364                 return ret;
 365
 366         ret = clk_set_rate(priv->clk, ULONG_MAX);
 367         if (ret)
 368                 goto disable_clk;
 369
 370         priv->clk_rate = clk_get_rate(priv->clk);
 371
 372         /* If max-frequency property is set, use it. */
 373         if (!mmc->f_max)
 374                 mmc->f_max = priv->clk_rate;
 375
 376         /*
 377          * 1/512 is the finest divisor in the original IP.  Newer versions
 378          * also supports 1/1024 divisor. (UniPhier-specific extension)
 379          */
 380         if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
 381                 mmc->f_min = priv->clk_rate / 1024;
 382         else
 383                 mmc->f_min = priv->clk_rate / 512;
 384
 385         ret = reset_control_deassert(priv->rst);
 386         if (ret)
 387                 goto disable_clk;
 388
 389         ret = reset_control_deassert(priv->rst_br);
 390         if (ret)
 391                 goto assert_rst;
 392
 393         return 0;
 394
 395 assert_rst:
 396         reset_control_assert(priv->rst);
 397 disable_clk:
 398         clk_disable_unprepare(priv->clk);
 399
 400         return ret;
 401 }
 402
 403 static void uniphier_sd_clk_disable(struct tmio_mmc_host *host)
 404 {
 405         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
 406
 407         reset_control_assert(priv->rst_br);
 408         reset_control_assert(priv->rst);
 409         clk_disable_unprepare(priv->clk);
 410 }
 411
 412 static void uniphier_sd_hw_reset(struct mmc_host *mmc)
 413 {
 414         struct tmio_mmc_host *host = mmc_priv(mmc);
 415         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
 416
 417         reset_control_assert(priv->rst_hw);
 418         /* For eMMC, minimum is 1us but give it 9us for good measure */
 419         udelay(9);
 420         reset_control_deassert(priv->rst_hw);
 421         /* For eMMC, minimum is 200us but give it 300us for good measure */
 422         usleep_range(300, 1000);
 423 }
 424
 425 static void uniphier_sd_set_clock(struct tmio_mmc_host *host,
 426                                   unsigned int clock)
 427 {
 428         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
 429         unsigned long divisor;
 430         u32 tmp;
 431
 432         tmp = readl(host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
 433
 434         /* stop the clock before changing its rate to avoid a glitch signal */
 435         tmp &= ~CLK_CTL_SCLKEN;
 436         writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
 437
 438         if (clock == 0)
 439                 return;
 440
 441         tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1024;
 442         tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1;
 443         tmp &= ~CLK_CTL_DIV_MASK;
 444
 445         divisor = priv->clk_rate / clock;
 446
 447         /*
 448          * In the original IP, bit[7:0] represents the divisor.
 449          * bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2
 450          *
 451          * The IP does not define a way to achieve 1/1.  For UniPhier variants,
 452          * bit10 is used for 1/1.  Newer versions of UniPhier variants use
 453          * bit16 for 1/1024.
 454          */
 455         if (divisor <= 1)
 456                 tmp |= UNIPHIER_SD_CLK_CTL_DIV1;
 457         else if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP && divisor > 512)
 458                 tmp |= UNIPHIER_SD_CLK_CTL_DIV1024;
 459         else
 460                 tmp |= roundup_pow_of_two(divisor) >> 2;
 461
 462         writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
 463
 464         tmp |= CLK_CTL_SCLKEN;
 465         writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
 466 }
 467
 468 static void uniphier_sd_host_init(struct tmio_mmc_host *host)
 469 {
 470         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
 471         u32 val;
 472
 473         /*
 474          * Connected to 32bit AXI.
 475          * This register holds settings for SoC-specific internal bus
 476          * connection.  What is worse, the register spec was changed,
 477          * breaking the backward compatibility.  Write an appropriate
 478          * value depending on a flag associated with a compatible string.
 479          */
 480         if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
 481                 val = 0x00000101;
 482         else
 483                 val = 0x00000000;
 484
 485         writel(val, host->ctl + UNIPHIER_SD_HOST_MODE);
 486
 487         val = 0;
 488         /*
 489          * If supported, the controller can automatically
 490          * enable/disable the clock line to the card.
 491          */
 492         if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
 493                 val |= UNIPHIER_SD_CLKCTL_OFFEN;
 494
 495         writel(val, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
 496 }
 497
 498 static int uniphier_sd_start_signal_voltage_switch(struct mmc_host *mmc,
 499                                                    struct mmc_ios *ios)
 500 {
 501         struct tmio_mmc_host *host = mmc_priv(mmc);
 502         struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
 503         struct pinctrl_state *pinstate = NULL;
 504         u32 val, tmp;
 505
 506         switch (ios->signal_voltage) {
 507         case MMC_SIGNAL_VOLTAGE_330:
 508                 val = UNIPHIER_SD_VOLT_330;
 509                 break;
 510         case MMC_SIGNAL_VOLTAGE_180:
 511                 val = UNIPHIER_SD_VOLT_180;
 512                 pinstate = priv->pinstate_uhs;
 513                 break;
 514         default:
 515                 return -ENOTSUPP;
 516         }
 517
 518         tmp = readl(host->ctl + UNIPHIER_SD_VOLT);
 519         tmp &= ~UNIPHIER_SD_VOLT_MASK;
 520         tmp |= FIELD_PREP(UNIPHIER_SD_VOLT_MASK, val);
 521         writel(tmp, host->ctl + UNIPHIER_SD_VOLT);
 522
 523         if (pinstate)
 524                 pinctrl_select_state(priv->pinctrl, pinstate);
 525         else
 526                 pinctrl_select_default_state(mmc_dev(mmc));
 527
 528         return 0;
 529 }
 530
 531 static int uniphier_sd_uhs_init(struct tmio_mmc_host *host,
 532                                 struct uniphier_sd_priv *priv)
 533 {
 534         priv->pinctrl = devm_pinctrl_get(mmc_dev(host->mmc));
 535         if (IS_ERR(priv->pinctrl))
 536                 return PTR_ERR(priv->pinctrl);
 537
 538         priv->pinstate_uhs = pinctrl_lookup_state(priv->pinctrl, "uhs");
 539         if (IS_ERR(priv->pinstate_uhs))
 540                 return PTR_ERR(priv->pinstate_uhs);
 541
 542         host->ops.start_signal_voltage_switch =
 543                                         uniphier_sd_start_signal_voltage_switch;
 544
 545         return 0;
 546 }
 547
 548 static int uniphier_sd_probe(struct platform_device *pdev)
 549 {
 550         struct device *dev = &pdev->dev;
 551         struct uniphier_sd_priv *priv;
 552         struct tmio_mmc_data *tmio_data;
 553         struct tmio_mmc_host *host;
 554         int irq, ret;
 555
 556         irq = platform_get_irq(pdev, 0);
 557         if (irq < 0)
 558                 return irq;
 559
 560         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 561         if (!priv)
 562                 return -ENOMEM;
 563
 564         priv->caps = (unsigned long)of_device_get_match_data(dev);
 565
 566         priv->clk = devm_clk_get(dev, NULL);
 567         if (IS_ERR(priv->clk)) {
 568                 dev_err(dev, "failed to get clock\n");
 569                 return PTR_ERR(priv->clk);
 570         }
 571
 572         priv->rst = devm_reset_control_get_shared(dev, "host");
 573         if (IS_ERR(priv->rst)) {
 574                 dev_err(dev, "failed to get host reset\n");
 575                 return PTR_ERR(priv->rst);
 576         }
 577
 578         /* old version has one more reset */
 579         if (!(priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)) {
 580                 priv->rst_br = devm_reset_control_get_shared(dev, "bridge");
 581                 if (IS_ERR(priv->rst_br)) {
 582                         dev_err(dev, "failed to get bridge reset\n");
 583                         return PTR_ERR(priv->rst_br);
 584                 }
 585         }
 586
 587         tmio_data = &priv->tmio_data;
 588         tmio_data->flags |= TMIO_MMC_32BIT_DATA_PORT;
 589
 590         host = tmio_mmc_host_alloc(pdev, tmio_data);
 591         if (IS_ERR(host))
 592                 return PTR_ERR(host);
 593
 594         if (host->mmc->caps & MMC_CAP_HW_RESET) {
 595                 priv->rst_hw = devm_reset_control_get_exclusive(dev, "hw");
 596                 if (IS_ERR(priv->rst_hw)) {
 597                         dev_err(dev, "failed to get hw reset\n");
 598                         ret = PTR_ERR(priv->rst_hw);
 599                         goto free_host;
 600                 }
 601                 host->ops.hw_reset = uniphier_sd_hw_reset;
 602         }
 603
 604         if (host->mmc->caps & MMC_CAP_UHS) {
 605                 ret = uniphier_sd_uhs_init(host, priv);
 606                 if (ret) {
 607                         dev_warn(dev,
 608                                  "failed to setup UHS (error %d).  Disabling UHS.",
 609                                  ret);
 610                         host->mmc->caps &= ~MMC_CAP_UHS;
 611                 }
 612         }
 613
 614         if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
 615                 host->dma_ops = &uniphier_sd_internal_dma_ops;
 616         else
 617                 host->dma_ops = &uniphier_sd_external_dma_ops;
 618
 619         host->bus_shift = 1;
 620         host->clk_enable = uniphier_sd_clk_enable;
 621         host->clk_disable = uniphier_sd_clk_disable;
 622         host->set_clock = uniphier_sd_set_clock;
 623
 624         ret = uniphier_sd_clk_enable(host);
 625         if (ret)
 626                 goto free_host;
 627
 628         uniphier_sd_host_init(host);
 629
 630         tmio_data->ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34;
 631         if (host->mmc->caps & MMC_CAP_UHS)
 632                 tmio_data->ocr_mask |= MMC_VDD_165_195;
 633
 634         tmio_data->max_segs = 1;
 635         tmio_data->max_blk_count = U16_MAX;
 636
 637         ret = tmio_mmc_host_probe(host);
 638         if (ret)
 639                 goto disable_clk;
 640
 641         ret = devm_request_irq(dev, irq, tmio_mmc_irq, IRQF_SHARED,
 642                                dev_name(dev), host);
 643         if (ret)
 644                 goto remove_host;
 645
 646         return 0;
 647
 648 remove_host:
 649         tmio_mmc_host_remove(host);
 650 disable_clk:
 651         uniphier_sd_clk_disable(host);
 652 free_host:
 653         tmio_mmc_host_free(host);
 654
 655         return ret;
 656 }
 657
 658 static int uniphier_sd_remove(struct platform_device *pdev)
 659 {
 660         struct tmio_mmc_host *host = platform_get_drvdata(pdev);
 661
 662         tmio_mmc_host_remove(host);
 663         uniphier_sd_clk_disable(host);
 664         tmio_mmc_host_free(host);
 665
 666         return 0;
 667 }
 668
 669 static const struct of_device_id uniphier_sd_match[] = {
 670         {
 671                 .compatible = "socionext,uniphier-sd-v2.91",
 672         },
 673         {
 674                 .compatible = "socionext,uniphier-sd-v3.1",
 675                 .data = (void *)(UNIPHIER_SD_CAP_EXTENDED_IP |
 676                                  UNIPHIER_SD_CAP_BROKEN_DMA_RX),
 677         },
 678         {
 679                 .compatible = "socionext,uniphier-sd-v3.1.1",
 680                 .data = (void *)UNIPHIER_SD_CAP_EXTENDED_IP,
 681         },
 682         { /* sentinel */ }
 683 };
 684 MODULE_DEVICE_TABLE(of, uniphier_sd_match);
 685
 686 static struct platform_driver uniphier_sd_driver = {
 687         .probe = uniphier_sd_probe,
 688         .remove = uniphier_sd_remove,
 689         .driver = {
 690                 .name = "uniphier-sd",
 691                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
 692                 .of_match_table = uniphier_sd_match,
 693         },
 694 };
 695 module_platform_driver(uniphier_sd_driver);
 696
 697 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
 698 MODULE_DESCRIPTION("UniPhier SD/eMMC host controller driver");
 699 MODULE_LICENSE("GPL v2");