drivers/mmc/host/sunplus-mmc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) Sunplus Inc.
   4  * Author: Tony Huang <tonyhuang.sunplus@gmail.com>
   5  * Author: Li-hao Kuo <lhjeff911@gmail.com>
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/mmc/core.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/mmc/mmc.h>
  17 #include <linux/mmc/sdio.h>
  18 #include <linux/mmc/slot-gpio.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/reset.h>
  25
  26 #define SPMMC_MIN_CLK                   400000
  27 #define SPMMC_MAX_CLK                   52000000
  28 #define SPMMC_MAX_BLK_COUNT             65536
  29 #define SPMMC_MAX_TUNABLE_DLY   7
  30 #define SPMMC_TIMEOUT_US                500000
  31 #define SPMMC_POLL_DELAY_US             10
  32
  33 #define SPMMC_CARD_MEDIATYPE_SRCDST_REG 0x0000
  34 #define SPMMC_MEDIA_TYPE                GENMASK(2, 0)
  35 #define SPMMC_DMA_SOURCE                GENMASK(6, 4)
  36 #define SPMMC_DMA_DESTINATION           GENMASK(10, 8)
  37 #define SPMMC_MEDIA_NONE        0
  38 #define SPMMC_MEDIA_SD          6
  39 #define SPMMC_MEDIA_MS          7
  40
  41 #define SPMMC_SDRAM_SECTOR_0_SIZE_REG   0x0008
  42 #define SPMMC_DMA_BASE_ADDR_REG         0x000C
  43 #define SPMMC_HW_DMA_CTRL_REG           0x0010
  44 #define SPMMC_HW_DMA_RST        BIT(9)
  45 #define SPMMC_DMAIDLE           BIT(10)
  46
  47 #define SPMMC_MAX_DMA_MEMORY_SECTORS    8
  48
  49 #define SPMMC_SDRAM_SECTOR_1_ADDR_REG 0x0018
  50 #define SPMMC_SDRAM_SECTOR_1_LENG_REG 0x001C
  51 #define SPMMC_SDRAM_SECTOR_2_ADDR_REG 0x0020
  52 #define SPMMC_SDRAM_SECTOR_2_LENG_REG 0x0024
  53 #define SPMMC_SDRAM_SECTOR_3_ADDR_REG 0x0028
  54 #define SPMMC_SDRAM_SECTOR_3_LENG_REG 0x002C
  55 #define SPMMC_SDRAM_SECTOR_4_ADDR_REG 0x0030
  56 #define SPMMC_SDRAM_SECTOR_4_LENG_REG 0x0034
  57 #define SPMMC_SDRAM_SECTOR_5_ADDR_REG 0x0038
  58 #define SPMMC_SDRAM_SECTOR_5_LENG_REG 0x003C
  59 #define SPMMC_SDRAM_SECTOR_6_ADDR_REG 0x0040
  60 #define SPMMC_SDRAM_SECTOR_6_LENG_REG 0x0044
  61 #define SPMMC_SDRAM_SECTOR_7_ADDR_REG 0x0048
  62 #define SPMMC_SDRAM_SECTOR_7_LENG_REG 0x004C
  63
  64 #define SPMMC_SD_INT_REG        0x0088
  65 #define SPMMC_SDINT_SDCMPEN     BIT(0)
  66 #define SPMMC_SDINT_SDCMP       BIT(1)
  67 #define SPMMC_SDINT_SDCMPCLR    BIT(2)
  68 #define SPMMC_SDINT_SDIOEN      BIT(3)
  69 #define SPMMC_SDINT_SDIO        BIT(4)
  70 #define SPMMC_SDINT_SDIOCLR     BIT(5)
  71
  72 #define SPMMC_SD_PAGE_NUM_REG   0x008C
  73
  74 #define SPMMC_SD_CONFIG0_REG    0x0090
  75 #define SPMMC_SD_PIO_MODE       BIT(0)
  76 #define SPMMC_SD_DDR_MODE       BIT(1)
  77 #define SPMMC_SD_LEN_MODE       BIT(2)
  78 #define SPMMC_SD_TRANS_MODE     GENMASK(5, 4)
  79 #define SPMMC_SD_AUTO_RESPONSE  BIT(6)
  80 #define SPMMC_SD_CMD_DUMMY      BIT(7)
  81 #define SPMMC_SD_RSP_CHK_EN     BIT(8)
  82 #define SPMMC_SDIO_MODE         BIT(9)
  83 #define SPMMC_SD_MMC_MODE       BIT(10)
  84 #define SPMMC_SD_DATA_WD        BIT(11)
  85 #define SPMMC_RX4_EN            BIT(14)
  86 #define SPMMC_SD_RSP_TYPE       BIT(15)
  87 #define SPMMC_MMC8_EN           BIT(18)
  88 #define SPMMC_CLOCK_DIVISION    GENMASK(31, 20)
  89
  90 #define SPMMC_SDIO_CTRL_REG             0x0094
  91 #define SPMMC_INT_MULTI_TRIG            BIT(6)
  92
  93 #define SPMMC_SD_RST_REG                0x0098
  94 #define SPMMC_SD_CTRL_REG               0x009C
  95 #define SPMMC_NEW_COMMAND_TRIGGER       BIT(0)
  96 #define SPMMC_DUMMY_CLOCK_TRIGGER       BIT(1)
  97
  98 #define SPMMC_SD_STATUS_REG                                             0x00A0
  99 #define SPMMC_SDSTATUS_DUMMY_READY                              BIT(0)
 100 #define SPMMC_SDSTATUS_RSP_BUF_FULL                             BIT(1)
 101 #define SPMMC_SDSTATUS_TX_DATA_BUF_EMPTY                BIT(2)
 102 #define SPMMC_SDSTATUS_RX_DATA_BUF_FULL                 BIT(3)
 103 #define SPMMC_SDSTATUS_CMD_PIN_STATUS                   BIT(4)
 104 #define SPMMC_SDSTATUS_DAT0_PIN_STATUS                  BIT(5)
 105 #define SPMMC_SDSTATUS_RSP_TIMEOUT                              BIT(6)
 106 #define SPMMC_SDSTATUS_CARD_CRC_CHECK_TIMEOUT   BIT(7)
 107 #define SPMMC_SDSTATUS_STB_TIMEOUT                              BIT(8)
 108 #define SPMMC_SDSTATUS_RSP_CRC7_ERROR                   BIT(9)
 109 #define SPMMC_SDSTATUS_CRC_TOKEN_CHECK_ERROR    BIT(10)
 110 #define SPMMC_SDSTATUS_RDATA_CRC16_ERROR                BIT(11)
 111 #define SPMMC_SDSTATUS_SUSPEND_STATE_READY              BIT(12)
 112 #define SPMMC_SDSTATUS_BUSY_CYCLE                               BIT(13)
 113 #define SPMMC_SDSTATUS_DAT1_PIN_STATUS                  BIT(14)
 114 #define SPMMC_SDSTATUS_SD_SENSE_STATUS                  BIT(15)
 115 #define SPMMC_SDSTATUS_BOOT_ACK_TIMEOUT                 BIT(16)
 116 #define SPMMC_SDSTATUS_BOOT_DATA_TIMEOUT                BIT(17)
 117 #define SPMMC_SDSTATUS_BOOT_ACK_ERROR                   BIT(18)
 118
 119 #define SPMMC_SD_STATE_REG              0x00A4
 120 #define SPMMC_CRCTOKEN_CHECK_RESULT     GENMASK(6, 4)
 121 #define SPMMC_SDSTATE_ERROR             BIT(13)
 122 #define SPMMC_SDSTATE_FINISH    BIT(14)
 123
 124 #define SPMMC_SD_HW_STATE_REG           0x00A8
 125 #define SPMMC_SD_BLOCKSIZE_REG          0x00AC
 126
 127 #define SPMMC_SD_CONFIG1_REG            0x00B0
 128 #define SPMMC_TX_DUMMY_NUM              GENMASK(8, 0)
 129 #define SPMMC_SD_HIGH_SPEED_EN          BIT(31)
 130
 131 #define SPMMC_SD_TIMING_CONFIG0_REG 0x00B4
 132 #define SPMMC_SD_CLOCK_DELAY    GENMASK(2, 0)
 133 #define SPMMC_SD_WRITE_DATA_DELAY       GENMASK(6, 4)
 134 #define SPMMC_SD_WRITE_COMMAND_DELAY    GENMASK(10, 8)
 135 #define SPMMC_SD_READ_RESPONSE_DELAY    GENMASK(14, 12)
 136 #define SPMMC_SD_READ_DATA_DELAY        GENMASK(18, 16)
 137 #define SPMMC_SD_READ_CRC_DELAY GENMASK(22, 20)
 138
 139 #define SPMMC_SD_PIODATATX_REG          0x00BC
 140 #define SPMMC_SD_PIODATARX_REG          0x00C0
 141 #define SPMMC_SD_CMDBUF0_3_REG          0x00C4
 142 #define SPMMC_SD_CMDBUF4_REG            0x00C8
 143 #define SPMMC_SD_RSPBUF0_3_REG          0x00CC
 144 #define SPMMC_SD_RSPBUF4_5_REG          0x00D0
 145
 146 #define SPMMC_MAX_RETRIES (8 * 8)
 147
 148 struct spmmc_tuning_info {
 149         int enable_tuning;
 150         int need_tuning;
 151         int retried; /* how many times has been retried */
 152         u32 rd_crc_dly:3;
 153         u32 rd_dat_dly:3;
 154         u32 rd_rsp_dly:3;
 155         u32 wr_cmd_dly:3;
 156         u32 wr_dat_dly:3;
 157         u32 clk_dly:3;
 158 };
 159
 160 #define SPMMC_DMA_MODE 0
 161 #define SPMMC_PIO_MODE 1
 162
 163 struct spmmc_host {
 164         void __iomem *base;
 165         struct clk *clk;
 166         struct reset_control *rstc;
 167         struct mmc_host *mmc;
 168         struct mmc_request *mrq; /* current mrq */
 169         int irq;
 170         int dmapio_mode;
 171         struct spmmc_tuning_info tuning_info;
 172         int dma_int_threshold;
 173         int dma_use_int;
 174 };
 175
 176 static inline int spmmc_wait_finish(struct spmmc_host *host)
 177 {
 178         u32 state;
 179
 180         return readl_poll_timeout(host->base + SPMMC_SD_STATE_REG, state,
 181                                         (state & SPMMC_SDSTATE_FINISH),
 182                                         SPMMC_POLL_DELAY_US, SPMMC_TIMEOUT_US);
 183 }
 184
 185 static inline int spmmc_wait_sdstatus(struct spmmc_host *host, unsigned int status_bit)
 186 {
 187         u32 status;
 188
 189         return readl_poll_timeout(host->base + SPMMC_SD_STATUS_REG, status,
 190                                         (status & status_bit),
 191                                         SPMMC_POLL_DELAY_US, SPMMC_TIMEOUT_US);
 192 }
 193
 194 #define spmmc_wait_rspbuf_full(host) spmmc_wait_sdstatus(host, SPMMC_SDSTATUS_RSP_BUF_FULL)
 195 #define spmmc_wait_rxbuf_full(host) spmmc_wait_sdstatus(host, SPMMC_SDSTATUS_RX_DATA_BUF_FULL)
 196 #define spmmc_wait_txbuf_empty(host) spmmc_wait_sdstatus(host, SPMMC_SDSTATUS_TX_DATA_BUF_EMPTY)
 197
 198 static void spmmc_get_rsp(struct spmmc_host *host, struct mmc_command *cmd)
 199 {
 200         u32 value0_3, value4_5;
 201
 202         if (!(cmd->flags & MMC_RSP_PRESENT))
 203                 return;
 204         if (cmd->flags & MMC_RSP_136) {
 205                 if (spmmc_wait_rspbuf_full(host))
 206                         return;
 207                 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG);
 208                 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff;
 209                 cmd->resp[0] = (value0_3 << 8) | (value4_5 >> 8);
 210                 cmd->resp[1] = value4_5 << 24;
 211                 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG);
 212                 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff;
 213                 cmd->resp[1] |= value0_3 >> 8;
 214                 cmd->resp[2] = value0_3 << 24;
 215                 cmd->resp[2] |= value4_5 << 8;
 216                 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG);
 217                 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff;
 218                 cmd->resp[2] |= value0_3 >> 24;
 219                 cmd->resp[3] = value0_3 << 8;
 220                 cmd->resp[3] |= value4_5 >> 8;
 221         } else {
 222                 if (spmmc_wait_rspbuf_full(host))
 223                         return;
 224                 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG);
 225                 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff;
 226                 cmd->resp[0] = (value0_3 << 8) | (value4_5 >> 8);
 227                 cmd->resp[1] = value4_5 << 24;
 228         }
 229 }
 230
 231 static void spmmc_set_bus_clk(struct spmmc_host *host, int clk)
 232 {
 233         unsigned int clkdiv;
 234         int f_min = host->mmc->f_min;
 235         int f_max = host->mmc->f_max;
 236         u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
 237
 238         if (clk < f_min)
 239                 clk = f_min;
 240         if (clk > f_max)
 241                 clk = f_max;
 242
 243         clkdiv = (clk_get_rate(host->clk) + clk) / clk - 1;
 244         if (clkdiv > 0xfff)
 245                 clkdiv = 0xfff;
 246         value &= ~SPMMC_CLOCK_DIVISION;
 247         value |= FIELD_PREP(SPMMC_CLOCK_DIVISION, clkdiv);
 248         writel(value, host->base + SPMMC_SD_CONFIG0_REG);
 249 }
 250
 251 static void spmmc_set_bus_timing(struct spmmc_host *host, unsigned int timing)
 252 {
 253         u32 value = readl(host->base + SPMMC_SD_CONFIG1_REG);
 254         int clkdiv = FIELD_GET(SPMMC_CLOCK_DIVISION, readl(host->base + SPMMC_SD_CONFIG0_REG));
 255         int delay = clkdiv / 2 < 7 ? clkdiv / 2 : 7;
 256         int hs_en = 1, ddr_enabled = 0;
 257
 258         switch (timing) {
 259         case MMC_TIMING_LEGACY:
 260                 hs_en = 0;
 261                 break;
 262         case MMC_TIMING_MMC_HS:
 263         case MMC_TIMING_SD_HS:
 264         case MMC_TIMING_UHS_SDR50:
 265         case MMC_TIMING_UHS_SDR104:
 266         case MMC_TIMING_MMC_HS200:
 267                 hs_en = 1;
 268                 break;
 269         case MMC_TIMING_UHS_DDR50:
 270                 ddr_enabled = 1;
 271                 break;
 272         case MMC_TIMING_MMC_DDR52:
 273                 ddr_enabled = 1;
 274                 break;
 275         default:
 276                 hs_en = 0;
 277                 break;
 278         }
 279
 280         if (hs_en) {
 281                 value |= SPMMC_SD_HIGH_SPEED_EN;
 282                 writel(value, host->base + SPMMC_SD_CONFIG1_REG);
 283                 value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG);
 284                 value &= ~SPMMC_SD_WRITE_DATA_DELAY;
 285                 value |= FIELD_PREP(SPMMC_SD_WRITE_DATA_DELAY, delay);
 286                 value &= ~SPMMC_SD_WRITE_COMMAND_DELAY;
 287                 value |= FIELD_PREP(SPMMC_SD_WRITE_COMMAND_DELAY, delay);
 288                 writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
 289         } else {
 290                 value &= ~SPMMC_SD_HIGH_SPEED_EN;
 291                 writel(value, host->base + SPMMC_SD_CONFIG1_REG);
 292         }
 293         if (ddr_enabled) {
 294                 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
 295                 value |= SPMMC_SD_DDR_MODE;
 296                 writel(value, host->base + SPMMC_SD_CONFIG0_REG);
 297         } else {
 298                 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
 299                 value &= ~SPMMC_SD_DDR_MODE;
 300                 writel(value, host->base + SPMMC_SD_CONFIG0_REG);
 301         }
 302 }
 303
 304 static void spmmc_set_bus_width(struct spmmc_host *host, int width)
 305 {
 306         u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
 307
 308         switch (width) {
 309         case MMC_BUS_WIDTH_8:
 310                 value &= ~SPMMC_SD_DATA_WD;
 311                 value |= SPMMC_MMC8_EN;
 312                 break;
 313         case MMC_BUS_WIDTH_4:
 314                 value |= SPMMC_SD_DATA_WD;
 315                 value &= ~SPMMC_MMC8_EN;
 316                 break;
 317         default:
 318                 value &= ~SPMMC_SD_DATA_WD;
 319                 value &= ~SPMMC_MMC8_EN;
 320                 break;
 321         }
 322         writel(value, host->base + SPMMC_SD_CONFIG0_REG);
 323 }
 324
 325 /*
 326  * select the working mode of controller: sd/sdio/emmc
 327  */
 328 static void spmmc_set_sdmmc_mode(struct spmmc_host *host)
 329 {
 330         u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
 331
 332         value |= SPMMC_SD_MMC_MODE;
 333         value &= ~SPMMC_SDIO_MODE;
 334         writel(value, host->base + SPMMC_SD_CONFIG0_REG);
 335 }
 336
 337 static void spmmc_sw_reset(struct spmmc_host *host)
 338 {
 339         u32 value;
 340
 341         /*
 342          * Must reset dma operation first, or it will
 343          * be stuck on sd_state == 0x1c00 because of
 344          * a controller software reset bug
 345          */
 346         value = readl(host->base + SPMMC_HW_DMA_CTRL_REG);
 347         value |= SPMMC_DMAIDLE;
 348         writel(value, host->base + SPMMC_HW_DMA_CTRL_REG);
 349         value &= ~SPMMC_DMAIDLE;
 350         writel(value, host->base + SPMMC_HW_DMA_CTRL_REG);
 351         value = readl(host->base + SPMMC_HW_DMA_CTRL_REG);
 352         value |= SPMMC_HW_DMA_RST;
 353         writel(value, host->base + SPMMC_HW_DMA_CTRL_REG);
 354         writel(0x7, host->base + SPMMC_SD_RST_REG);
 355         readl_poll_timeout_atomic(host->base + SPMMC_SD_HW_STATE_REG, value,
 356                                   !(value & BIT(6)), 1, SPMMC_TIMEOUT_US);
 357 }
 358
 359 static void spmmc_prepare_cmd(struct spmmc_host *host, struct mmc_command *cmd)
 360 {
 361         u32 value;
 362
 363         /* add start bit, according to spec, command format */
 364         value = ((cmd->opcode | 0x40) << 24) | (cmd->arg >> 8);
 365         writel(value, host->base + SPMMC_SD_CMDBUF0_3_REG);
 366         writeb(cmd->arg & 0xff, host->base + SPMMC_SD_CMDBUF4_REG);
 367
 368         /* disable interrupt if needed */
 369         value = readl(host->base + SPMMC_SD_INT_REG);
 370         value |= SPMMC_SDINT_SDCMPCLR;
 371         value &= ~SPMMC_SDINT_SDCMPEN;
 372         writel(value, host->base + SPMMC_SD_INT_REG);
 373
 374         value = readl(host->base + SPMMC_SD_CONFIG0_REG);
 375         value &= ~SPMMC_SD_TRANS_MODE;
 376         value |= SPMMC_SD_CMD_DUMMY;
 377         if (cmd->flags & MMC_RSP_PRESENT) {
 378                 value |= SPMMC_SD_AUTO_RESPONSE;
 379         } else {
 380                 value &= ~SPMMC_SD_AUTO_RESPONSE;
 381                 writel(value, host->base + SPMMC_SD_CONFIG0_REG);
 382
 383                 return;
 384         }
 385         /*
 386          * Currently, host is not capable of checking R2's CRC7,
 387          * thus, enable crc7 check only for 48 bit response commands
 388          */
 389         if (cmd->flags & MMC_RSP_CRC && !(cmd->flags & MMC_RSP_136))
 390                 value |= SPMMC_SD_RSP_CHK_EN;
 391         else
 392                 value &= ~SPMMC_SD_RSP_CHK_EN;
 393
 394         if (cmd->flags & MMC_RSP_136)
 395                 value |= SPMMC_SD_RSP_TYPE;
 396         else
 397                 value &= ~SPMMC_SD_RSP_TYPE;
 398         writel(value, host->base + SPMMC_SD_CONFIG0_REG);
 399 }
 400
 401 static void spmmc_prepare_data(struct spmmc_host *host, struct mmc_data *data)
 402 {
 403         u32 value, srcdst;
 404
 405         writel(data->blocks - 1, host->base + SPMMC_SD_PAGE_NUM_REG);
 406         writel(data->blksz - 1, host->base + SPMMC_SD_BLOCKSIZE_REG);
 407         value = readl(host->base + SPMMC_SD_CONFIG0_REG);
 408         if (data->flags & MMC_DATA_READ) {
 409                 value &= ~SPMMC_SD_TRANS_MODE;
 410                 value |= FIELD_PREP(SPMMC_SD_TRANS_MODE, 2);
 411                 value &= ~SPMMC_SD_AUTO_RESPONSE;
 412                 value &= ~SPMMC_SD_CMD_DUMMY;
 413                 srcdst = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
 414                 srcdst &= ~SPMMC_DMA_SOURCE;
 415                 srcdst |= FIELD_PREP(SPMMC_DMA_SOURCE, 0x2);
 416                 srcdst &= ~SPMMC_DMA_DESTINATION;
 417                 srcdst |= FIELD_PREP(SPMMC_DMA_DESTINATION, 0x1);
 418                 writel(srcdst, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
 419         } else {
 420                 value &= ~SPMMC_SD_TRANS_MODE;
 421                 value |= FIELD_PREP(SPMMC_SD_TRANS_MODE, 1);
 422                 srcdst = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
 423                 srcdst &= ~SPMMC_DMA_SOURCE;
 424                 srcdst |= FIELD_PREP(SPMMC_DMA_SOURCE, 0x1);
 425                 srcdst &= ~SPMMC_DMA_DESTINATION;
 426                 srcdst |= FIELD_PREP(SPMMC_DMA_DESTINATION, 0x2);
 427                 writel(srcdst, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
 428         }
 429
 430         value |= SPMMC_SD_LEN_MODE;
 431         if (host->dmapio_mode == SPMMC_DMA_MODE) {
 432                 struct scatterlist *sg;
 433                 dma_addr_t dma_addr;
 434                 unsigned int dma_size;
 435                 int i, count = 1;
 436
 437                 count = dma_map_sg(host->mmc->parent, data->sg, data->sg_len,
 438                                    mmc_get_dma_dir(data));
 439                 if (!count || count > SPMMC_MAX_DMA_MEMORY_SECTORS) {
 440                         data->error = -EINVAL;
 441
 442                         return;
 443                 }
 444                 for_each_sg(data->sg, sg, count, i) {
 445                         dma_addr = sg_dma_address(sg);
 446                         dma_size = sg_dma_len(sg) / data->blksz - 1;
 447                         if (i == 0) {
 448                                 writel(dma_addr, host->base + SPMMC_DMA_BASE_ADDR_REG);
 449                                 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_0_SIZE_REG);
 450                         } else if (i == 1) {
 451                                 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_1_ADDR_REG);
 452                                 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_1_LENG_REG);
 453                         } else if (i == 2) {
 454                                 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_2_ADDR_REG);
 455                                 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_2_LENG_REG);
 456                         } else if (i == 3) {
 457                                 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_3_ADDR_REG);
 458                                 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_3_LENG_REG);
 459                         } else if (i == 4) {
 460                                 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_4_ADDR_REG);
 461                                 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_4_LENG_REG);
 462                         } else if (i == 5) {
 463                                 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_5_ADDR_REG);
 464                                 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_5_LENG_REG);
 465                         } else if (i == 6) {
 466                                 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_6_ADDR_REG);
 467                                 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_6_LENG_REG);
 468                         } else if (i == 7) {
 469                                 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_7_ADDR_REG);
 470                                 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_7_LENG_REG);
 471                         }
 472                 }
 473                 value &= ~SPMMC_SD_PIO_MODE;
 474                 writel(value, host->base + SPMMC_SD_CONFIG0_REG);
 475                 /* enable interrupt if needed */
 476                 if (data->blksz * data->blocks > host->dma_int_threshold) {
 477                         host->dma_use_int = 1;
 478                         value = readl(host->base + SPMMC_SD_INT_REG);
 479                         value &= ~SPMMC_SDINT_SDCMPEN;
 480                         value |= FIELD_PREP(SPMMC_SDINT_SDCMPEN, 1); /* sdcmpen */
 481                         writel(value, host->base + SPMMC_SD_INT_REG);
 482                 }
 483         } else {
 484                 value |= SPMMC_SD_PIO_MODE;
 485                 value |= SPMMC_RX4_EN;
 486                 writel(value, host->base + SPMMC_SD_CONFIG0_REG);
 487         }
 488 }
 489
 490 static inline void spmmc_trigger_transaction(struct spmmc_host *host)
 491 {
 492         u32 value = readl(host->base + SPMMC_SD_CTRL_REG);
 493
 494         value |= SPMMC_NEW_COMMAND_TRIGGER;
 495         writel(value, host->base + SPMMC_SD_CTRL_REG);
 496 }
 497
 498 static void spmmc_send_stop_cmd(struct spmmc_host *host)
 499 {
 500         struct mmc_command stop = {};
 501         u32 value;
 502
 503         stop.opcode = MMC_STOP_TRANSMISSION;
 504         stop.arg = 0;
 505         stop.flags = MMC_RSP_R1B;
 506         spmmc_prepare_cmd(host, &stop);
 507         value = readl(host->base + SPMMC_SD_INT_REG);
 508         value &= ~SPMMC_SDINT_SDCMPEN;
 509         value |= FIELD_PREP(SPMMC_SDINT_SDCMPEN, 0);
 510         writel(value, host->base + SPMMC_SD_INT_REG);
 511         spmmc_trigger_transaction(host);
 512         readl_poll_timeout(host->base + SPMMC_SD_STATE_REG, value,
 513                            (value & SPMMC_SDSTATE_FINISH), 1, SPMMC_TIMEOUT_US);
 514 }
 515
 516 static int spmmc_check_error(struct spmmc_host *host, struct mmc_request *mrq)
 517 {
 518         int ret = 0;
 519         struct mmc_command *cmd = mrq->cmd;
 520         struct mmc_data *data = mrq->data;
 521
 522         u32 value = readl(host->base + SPMMC_SD_STATE_REG);
 523         u32 crc_token = FIELD_GET(SPMMC_CRCTOKEN_CHECK_RESULT, value);
 524
 525         if (value & SPMMC_SDSTATE_ERROR) {
 526                 u32 timing_cfg0 = 0;
 527
 528                 value = readl(host->base + SPMMC_SD_STATUS_REG);
 529
 530                 if (host->tuning_info.enable_tuning) {
 531                         timing_cfg0 = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG);
 532                         host->tuning_info.rd_crc_dly = FIELD_GET(SPMMC_SD_READ_CRC_DELAY,
 533                                                                  timing_cfg0);
 534                         host->tuning_info.rd_dat_dly = FIELD_GET(SPMMC_SD_READ_DATA_DELAY,
 535                                                                  timing_cfg0);
 536                         host->tuning_info.rd_rsp_dly = FIELD_GET(SPMMC_SD_READ_RESPONSE_DELAY,
 537                                                                  timing_cfg0);
 538                         host->tuning_info.wr_cmd_dly = FIELD_GET(SPMMC_SD_WRITE_COMMAND_DELAY,
 539                                                                  timing_cfg0);
 540                         host->tuning_info.wr_dat_dly = FIELD_GET(SPMMC_SD_WRITE_DATA_DELAY,
 541                                                                  timing_cfg0);
 542                 }
 543
 544                 if (value & SPMMC_SDSTATUS_RSP_TIMEOUT) {
 545                         ret = -ETIMEDOUT;
 546                         host->tuning_info.wr_cmd_dly++;
 547                 } else if (value & SPMMC_SDSTATUS_RSP_CRC7_ERROR) {
 548                         ret = -EILSEQ;
 549                         host->tuning_info.rd_rsp_dly++;
 550                 } else if (data) {
 551                         if ((value & SPMMC_SDSTATUS_STB_TIMEOUT)) {
 552                                 ret = -ETIMEDOUT;
 553                                 host->tuning_info.rd_dat_dly++;
 554                         } else if (value & SPMMC_SDSTATUS_RDATA_CRC16_ERROR) {
 555                                 ret = -EILSEQ;
 556                                 host->tuning_info.rd_dat_dly++;
 557                         } else if (value & SPMMC_SDSTATUS_CARD_CRC_CHECK_TIMEOUT) {
 558                                 ret = -ETIMEDOUT;
 559                                 host->tuning_info.rd_crc_dly++;
 560                         } else if (value & SPMMC_SDSTATUS_CRC_TOKEN_CHECK_ERROR) {
 561                                 ret = -EILSEQ;
 562                                 if (crc_token == 0x5)
 563                                         host->tuning_info.wr_dat_dly++;
 564                                 else
 565                                         host->tuning_info.rd_crc_dly++;
 566                         }
 567                 }
 568                 cmd->error = ret;
 569                 if (data) {
 570                         data->error = ret;
 571                         data->bytes_xfered = 0;
 572                 }
 573                 if (!host->tuning_info.need_tuning && host->tuning_info.enable_tuning)
 574                         cmd->retries = SPMMC_MAX_RETRIES;
 575                 spmmc_sw_reset(host);
 576
 577                 if (host->tuning_info.enable_tuning) {
 578                         timing_cfg0 &= ~SPMMC_SD_READ_CRC_DELAY;
 579                         timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY,
 580                                                        host->tuning_info.rd_crc_dly);
 581                         timing_cfg0 &= ~SPMMC_SD_READ_DATA_DELAY;
 582                         timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_DATA_DELAY,
 583                                                        host->tuning_info.rd_dat_dly);
 584                         timing_cfg0 &= ~SPMMC_SD_READ_RESPONSE_DELAY;
 585                         timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY,
 586                                                        host->tuning_info.rd_rsp_dly);
 587                         timing_cfg0 &= ~SPMMC_SD_WRITE_COMMAND_DELAY;
 588                         timing_cfg0 |= FIELD_PREP(SPMMC_SD_WRITE_COMMAND_DELAY,
 589                                                        host->tuning_info.wr_cmd_dly);
 590                         timing_cfg0 &= ~SPMMC_SD_WRITE_DATA_DELAY;
 591                         timing_cfg0 |= FIELD_PREP(SPMMC_SD_WRITE_DATA_DELAY,
 592                                                        host->tuning_info.wr_dat_dly);
 593                         writel(timing_cfg0, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
 594                 }
 595         } else if (data) {
 596                 data->error = 0;
 597                 data->bytes_xfered = data->blocks * data->blksz;
 598         }
 599         host->tuning_info.need_tuning = ret;
 600
 601         return ret;
 602 }
 603
 604 /*
 605  * the strategy is:
 606  * 1. if several continuous delays are acceptable, we choose a middle one;
 607  * 2. otherwise, we choose the first one.
 608  */
 609 static inline int spmmc_find_best_delay(u8 candidate_dly)
 610 {
 611         int f, w, value;
 612
 613         if (!candidate_dly)
 614                 return 0;
 615         f = ffs(candidate_dly) - 1;
 616         w = hweight8(candidate_dly);
 617         value = ((1 << w) - 1) << f;
 618         if (0xff == (value & ~candidate_dly))
 619                 return (f + w / 2);
 620         else
 621                 return (f);
 622 }
 623
 624 static void spmmc_xfer_data_pio(struct spmmc_host *host, struct mmc_data *data)
 625 {
 626         u32 *buf;
 627         int data_left = data->blocks * data->blksz;
 628         int consumed, remain;
 629
 630         struct sg_mapping_iter sg_miter;
 631         unsigned int flags = 0;
 632
 633         if (data->flags & MMC_DATA_WRITE)
 634                 flags |= SG_MITER_FROM_SG;
 635         else
 636                 flags |= SG_MITER_TO_SG;
 637         sg_miter_start(&sg_miter, data->sg, data->sg_len, flags);
 638         while (data_left > 0) {
 639                 consumed = 0;
 640                 if (!sg_miter_next(&sg_miter))
 641                         break;
 642                 buf = sg_miter.addr;
 643                 remain = sg_miter.length;
 644                 do {
 645                         if (data->flags & MMC_DATA_WRITE) {
 646                                 if (spmmc_wait_txbuf_empty(host))
 647                                         goto done;
 648                                 writel(*buf, host->base + SPMMC_SD_PIODATATX_REG);
 649                         } else {
 650                                 if (spmmc_wait_rxbuf_full(host))
 651                                         goto done;
 652                                 *buf = readl(host->base + SPMMC_SD_PIODATARX_REG);
 653                         }
 654                         buf++;
 655                         /* tx/rx 4 bytes one time in pio mode */
 656                         consumed += 4;
 657                         remain -= 4;
 658                 } while (remain);
 659                 sg_miter.consumed = consumed;
 660                 data_left -= consumed;
 661         }
 662 done:
 663         sg_miter_stop(&sg_miter);
 664 }
 665
 666 static void spmmc_controller_init(struct spmmc_host *host)
 667 {
 668         u32 value;
 669         int ret = reset_control_assert(host->rstc);
 670
 671         if (!ret) {
 672                 usleep_range(1000, 1250);
 673                 ret = reset_control_deassert(host->rstc);
 674         }
 675
 676         value = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
 677         value &= ~SPMMC_MEDIA_TYPE;
 678         value |= FIELD_PREP(SPMMC_MEDIA_TYPE, SPMMC_MEDIA_SD);
 679         writel(value, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
 680 }
 681
 682 /*
 683  * 1. unmap scatterlist if needed;
 684  * 2. get response & check error conditions;
 685  * 3. notify mmc layer the request is done
 686  */
 687 static void spmmc_finish_request(struct spmmc_host *host, struct mmc_request *mrq)
 688 {
 689         struct mmc_command *cmd;
 690         struct mmc_data *data;
 691
 692         if (!mrq)
 693                 return;
 694
 695         cmd = mrq->cmd;
 696         data = mrq->data;
 697
 698         if (data && SPMMC_DMA_MODE == host->dmapio_mode) {
 699                 dma_unmap_sg(host->mmc->parent, data->sg, data->sg_len, mmc_get_dma_dir(data));
 700                 host->dma_use_int = 0;
 701         }
 702
 703         spmmc_get_rsp(host, cmd);
 704         spmmc_check_error(host, mrq);
 705         if (mrq->stop)
 706                 spmmc_send_stop_cmd(host);
 707
 708         host->mrq = NULL;
 709         mmc_request_done(host->mmc, mrq);
 710 }
 711
 712 /* Interrupt Service Routine */
 713 static irqreturn_t spmmc_irq(int irq, void *dev_id)
 714 {
 715         struct spmmc_host *host = dev_id;
 716         u32 value = readl(host->base + SPMMC_SD_INT_REG);
 717
 718         if ((value & SPMMC_SDINT_SDCMP) && (value & SPMMC_SDINT_SDCMPEN)) {
 719                 value &= ~SPMMC_SDINT_SDCMPEN;
 720                 value |= SPMMC_SDINT_SDCMPCLR;
 721                 writel(value, host->base + SPMMC_SD_INT_REG);
 722                 return IRQ_WAKE_THREAD;
 723         }
 724         return IRQ_HANDLED;
 725 }
 726
 727 static void spmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 728 {
 729         struct spmmc_host *host = mmc_priv(mmc);
 730         struct mmc_data *data;
 731         struct mmc_command *cmd;
 732
 733         host->mrq = mrq;
 734         data = mrq->data;
 735         cmd = mrq->cmd;
 736
 737         spmmc_prepare_cmd(host, cmd);
 738         /* we need manually read response R2. */
 739         if (cmd->flags & MMC_RSP_136) {
 740                 spmmc_trigger_transaction(host);
 741                 spmmc_get_rsp(host, cmd);
 742                 spmmc_wait_finish(host);
 743                 spmmc_check_error(host, mrq);
 744                 host->mrq = NULL;
 745                 mmc_request_done(host->mmc, mrq);
 746         } else {
 747                 if (data)
 748                         spmmc_prepare_data(host, data);
 749
 750                 if (host->dmapio_mode == SPMMC_PIO_MODE && data) {
 751                         u32 value;
 752                         /* pio data transfer do not use interrupt */
 753                         value = readl(host->base + SPMMC_SD_INT_REG);
 754                         value &= ~SPMMC_SDINT_SDCMPEN;
 755                         writel(value, host->base + SPMMC_SD_INT_REG);
 756                         spmmc_trigger_transaction(host);
 757                         spmmc_xfer_data_pio(host, data);
 758                         spmmc_wait_finish(host);
 759                         spmmc_finish_request(host, mrq);
 760                 } else {
 761                         if (host->dma_use_int) {
 762                                 spmmc_trigger_transaction(host);
 763                         } else {
 764                                 spmmc_trigger_transaction(host);
 765                                 spmmc_wait_finish(host);
 766                                 spmmc_finish_request(host, mrq);
 767                         }
 768                 }
 769         }
 770 }
 771
 772 static void spmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 773 {
 774         struct spmmc_host *host = (struct spmmc_host *)mmc_priv(mmc);
 775
 776         spmmc_set_bus_clk(host, ios->clock);
 777         spmmc_set_bus_timing(host, ios->timing);
 778         spmmc_set_bus_width(host, ios->bus_width);
 779         /* ensure mode is correct, because we might have hw reset the controller */
 780         spmmc_set_sdmmc_mode(host);
 781 }
 782
 783 /*
 784  * Return values for the get_cd callback should be:
 785  *   0 for a absent card
 786  *   1 for a present card
 787  *   -ENOSYS when not supported (equal to NULL callback)
 788  *   or a negative errno value when something bad happened
 789  */
 790 static int spmmc_get_cd(struct mmc_host *mmc)
 791 {
 792         int ret = 0;
 793
 794         if (mmc_can_gpio_cd(mmc))
 795                 ret = mmc_gpio_get_cd(mmc);
 796
 797         if (ret < 0)
 798                 ret = 0;
 799
 800         return ret;
 801 }
 802
 803 static int spmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
 804 {
 805         struct spmmc_host *host = mmc_priv(mmc);
 806         u8 smpl_dly = 0, candidate_dly = 0;
 807         u32 value;
 808
 809         host->tuning_info.enable_tuning = 0;
 810         do {
 811                 value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG);
 812                 value &= ~SPMMC_SD_READ_RESPONSE_DELAY;
 813                 value |= FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY, smpl_dly);
 814                 value &= ~SPMMC_SD_READ_DATA_DELAY;
 815                 value |= FIELD_PREP(SPMMC_SD_READ_DATA_DELAY, smpl_dly);
 816                 value &= ~SPMMC_SD_READ_CRC_DELAY;
 817                 value |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, smpl_dly);
 818                 writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
 819
 820                 if (!mmc_send_tuning(mmc, opcode, NULL)) {
 821                         candidate_dly |= (1 << smpl_dly);
 822                         break;
 823                 }
 824         } while (smpl_dly++ <= SPMMC_MAX_TUNABLE_DLY);
 825         host->tuning_info.enable_tuning = 1;
 826
 827         if (candidate_dly) {
 828                 smpl_dly = spmmc_find_best_delay(candidate_dly);
 829                 value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG);
 830                 value &= ~SPMMC_SD_READ_RESPONSE_DELAY;
 831                 value |= FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY, smpl_dly);
 832                 value &= ~SPMMC_SD_READ_DATA_DELAY;
 833                 value |= FIELD_PREP(SPMMC_SD_READ_DATA_DELAY, smpl_dly);
 834                 value &= ~SPMMC_SD_READ_CRC_DELAY;
 835                 value |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, smpl_dly);
 836                 writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
 837                 return 0;
 838         }
 839
 840         return -EIO;
 841 }
 842
 843 static const struct mmc_host_ops spmmc_ops = {
 844         .request = spmmc_request,
 845         .set_ios = spmmc_set_ios,
 846         .get_cd = spmmc_get_cd,
 847         .execute_tuning = spmmc_execute_tuning,
 848 };
 849
 850 static irqreturn_t spmmc_func_finish_req(int irq, void *dev_id)
 851 {
 852         struct spmmc_host *host = dev_id;
 853
 854         spmmc_finish_request(host, host->mrq);
 855
 856         return IRQ_HANDLED;
 857 }
 858
 859 static int spmmc_drv_probe(struct platform_device *pdev)
 860 {
 861         struct mmc_host *mmc;
 862         struct resource *res;
 863         struct spmmc_host *host;
 864         int ret = 0;
 865
 866         mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct spmmc_host));
 867         if (!mmc)
 868                 return -ENOMEM;
 869
 870         host = mmc_priv(mmc);
 871         host->mmc = mmc;
 872         host->dmapio_mode = SPMMC_DMA_MODE;
 873         host->dma_int_threshold = 1024;
 874
 875         host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 876         if (IS_ERR(host->base))
 877                 return PTR_ERR(host->base);
 878
 879         host->clk = devm_clk_get(&pdev->dev, NULL);
 880         if (IS_ERR(host->clk))
 881                 return dev_err_probe(&pdev->dev, PTR_ERR(host->clk), "clk get fail\n");
 882
 883         host->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 884         if (IS_ERR(host->rstc))
 885                 return dev_err_probe(&pdev->dev, PTR_ERR(host->rstc), "rst get fail\n");
 886
 887         host->irq = platform_get_irq(pdev, 0);
 888         if (host->irq < 0)
 889                 return host->irq;
 890
 891         ret = devm_request_threaded_irq(&pdev->dev, host->irq,
 892                                         spmmc_irq, spmmc_func_finish_req, IRQF_SHARED,
 893                         NULL, host);
 894         if (ret)
 895                 return ret;
 896
 897         ret = clk_prepare_enable(host->clk);
 898         if (ret)
 899                 return dev_err_probe(&pdev->dev, ret, "failed to enable clk\n");
 900
 901         ret = mmc_of_parse(mmc);
 902         if (ret)
 903                 goto clk_disable;
 904
 905         mmc->ops = &spmmc_ops;
 906         mmc->f_min = SPMMC_MIN_CLK;
 907         if (mmc->f_max > SPMMC_MAX_CLK)
 908                 mmc->f_max = SPMMC_MAX_CLK;
 909
 910         ret = mmc_regulator_get_supply(mmc);
 911         if (ret)
 912                 goto clk_disable;
 913
 914         if (!mmc->ocr_avail)
 915                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 916         mmc->max_seg_size = SPMMC_MAX_BLK_COUNT * 512;
 917         mmc->max_segs = SPMMC_MAX_DMA_MEMORY_SECTORS;
 918         mmc->max_req_size = SPMMC_MAX_BLK_COUNT * 512;
 919         mmc->max_blk_size = 512;
 920         mmc->max_blk_count = SPMMC_MAX_BLK_COUNT;
 921
 922         dev_set_drvdata(&pdev->dev, host);
 923         spmmc_controller_init(host);
 924         spmmc_set_sdmmc_mode(host);
 925         host->tuning_info.enable_tuning = 1;
 926         pm_runtime_set_active(&pdev->dev);
 927         pm_runtime_enable(&pdev->dev);
 928         ret = mmc_add_host(mmc);
 929         if (ret)
 930                 goto pm_disable;
 931
 932         return 0;
 933
 934 pm_disable:
 935         pm_runtime_disable(&pdev->dev);
 936
 937 clk_disable:
 938         clk_disable_unprepare(host->clk);
 939         return ret;
 940 }
 941
 942 static void spmmc_drv_remove(struct platform_device *dev)
 943 {
 944         struct spmmc_host *host = platform_get_drvdata(dev);
 945
 946         mmc_remove_host(host->mmc);
 947         pm_runtime_get_sync(&dev->dev);
 948         clk_disable_unprepare(host->clk);
 949         pm_runtime_put_noidle(&dev->dev);
 950         pm_runtime_disable(&dev->dev);
 951 }
 952
 953 static int spmmc_pm_runtime_suspend(struct device *dev)
 954 {
 955         struct spmmc_host *host;
 956
 957         host = dev_get_drvdata(dev);
 958         clk_disable_unprepare(host->clk);
 959
 960         return 0;
 961 }
 962
 963 static int spmmc_pm_runtime_resume(struct device *dev)
 964 {
 965         struct spmmc_host *host;
 966
 967         host = dev_get_drvdata(dev);
 968
 969         return clk_prepare_enable(host->clk);
 970 }
 971
 972 static DEFINE_RUNTIME_DEV_PM_OPS(spmmc_pm_ops, spmmc_pm_runtime_suspend,
 973                                                         spmmc_pm_runtime_resume, NULL);
 974
 975 static const struct of_device_id spmmc_of_table[] = {
 976         {
 977                 .compatible = "sunplus,sp7021-mmc",
 978         },
 979         {/* sentinel */}
 980 };
 981 MODULE_DEVICE_TABLE(of, spmmc_of_table);
 982
 983 static struct platform_driver spmmc_driver = {
 984         .probe = spmmc_drv_probe,
 985         .remove_new = spmmc_drv_remove,
 986         .driver = {
 987                 .name = "spmmc",
 988                 .pm = pm_ptr(&spmmc_pm_ops),
 989                 .of_match_table = spmmc_of_table,
 990         },
 991 };
 992 module_platform_driver(spmmc_driver);
 993
 994 MODULE_AUTHOR("Tony Huang <tonyhuang.sunplus@gmail.com>");
 995 MODULE_AUTHOR("Li-hao Kuo <lhjeff911@gmail.com>");
 996 MODULE_DESCRIPTION("Sunplus MMC controller driver");
 997 MODULE_LICENSE("GPL");