drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/bitfield.h>
  17 #include <linux/delay.h>
  18 #include <linux/ktime.h>
  19 #include <linux/highmem.h>
  20 #include <linux/io.h>
  21 #include <linux/module.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/slab.h>
  24 #include <linux/scatterlist.h>
  25 #include <linux/sizes.h>
  26 #include <linux/swiotlb.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/of.h>
  30
  31 #include <linux/leds.h>
  32
  33 #include <linux/mmc/mmc.h>
  34 #include <linux/mmc/host.h>
  35 #include <linux/mmc/card.h>
  36 #include <linux/mmc/sdio.h>
  37 #include <linux/mmc/slot-gpio.h>
  38
  39 #include "sdhci.h"
  40
  41 #define DRIVER_NAME "sdhci"
  42
  43 #define DBG(f, x...) \
  44         pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
  45
  46 #define SDHCI_DUMP(f, x...) \
  47         pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
  48
  49 #define MAX_TUNING_LOOP 40
  50
  51 static unsigned int debug_quirks = 0;
  52 static unsigned int debug_quirks2;
  53
  54 static void sdhci_finish_data(struct sdhci_host *);
  55
  56 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  57
  58 void sdhci_dumpregs(struct sdhci_host *host)
  59 {
  60         SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
  61
  62         SDHCI_DUMP("Sys addr:  0x%08x | Version:  0x%08x\n",
  63                    sdhci_readl(host, SDHCI_DMA_ADDRESS),
  64                    sdhci_readw(host, SDHCI_HOST_VERSION));
  65         SDHCI_DUMP("Blk size:  0x%08x | Blk cnt:  0x%08x\n",
  66                    sdhci_readw(host, SDHCI_BLOCK_SIZE),
  67                    sdhci_readw(host, SDHCI_BLOCK_COUNT));
  68         SDHCI_DUMP("Argument:  0x%08x | Trn mode: 0x%08x\n",
  69                    sdhci_readl(host, SDHCI_ARGUMENT),
  70                    sdhci_readw(host, SDHCI_TRANSFER_MODE));
  71         SDHCI_DUMP("Present:   0x%08x | Host ctl: 0x%08x\n",
  72                    sdhci_readl(host, SDHCI_PRESENT_STATE),
  73                    sdhci_readb(host, SDHCI_HOST_CONTROL));
  74         SDHCI_DUMP("Power:     0x%08x | Blk gap:  0x%08x\n",
  75                    sdhci_readb(host, SDHCI_POWER_CONTROL),
  76                    sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  77         SDHCI_DUMP("Wake-up:   0x%08x | Clock:    0x%08x\n",
  78                    sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  79                    sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  80         SDHCI_DUMP("Timeout:   0x%08x | Int stat: 0x%08x\n",
  81                    sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  82                    sdhci_readl(host, SDHCI_INT_STATUS));
  83         SDHCI_DUMP("Int enab:  0x%08x | Sig enab: 0x%08x\n",
  84                    sdhci_readl(host, SDHCI_INT_ENABLE),
  85                    sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  86         SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
  87                    sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
  88                    sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  89         SDHCI_DUMP("Caps:      0x%08x | Caps_1:   0x%08x\n",
  90                    sdhci_readl(host, SDHCI_CAPABILITIES),
  91                    sdhci_readl(host, SDHCI_CAPABILITIES_1));
  92         SDHCI_DUMP("Cmd:       0x%08x | Max curr: 0x%08x\n",
  93                    sdhci_readw(host, SDHCI_COMMAND),
  94                    sdhci_readl(host, SDHCI_MAX_CURRENT));
  95         SDHCI_DUMP("Resp[0]:   0x%08x | Resp[1]:  0x%08x\n",
  96                    sdhci_readl(host, SDHCI_RESPONSE),
  97                    sdhci_readl(host, SDHCI_RESPONSE + 4));
  98         SDHCI_DUMP("Resp[2]:   0x%08x | Resp[3]:  0x%08x\n",
  99                    sdhci_readl(host, SDHCI_RESPONSE + 8),
 100                    sdhci_readl(host, SDHCI_RESPONSE + 12));
 101         SDHCI_DUMP("Host ctl2: 0x%08x\n",
 102                    sdhci_readw(host, SDHCI_HOST_CONTROL2));
 103
 104         if (host->flags & SDHCI_USE_ADMA) {
 105                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
 106                         SDHCI_DUMP("ADMA Err:  0x%08x | ADMA Ptr: 0x%08x%08x\n",
 107                                    sdhci_readl(host, SDHCI_ADMA_ERROR),
 108                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
 109                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS));
 110                 } else {
 111                         SDHCI_DUMP("ADMA Err:  0x%08x | ADMA Ptr: 0x%08x\n",
 112                                    sdhci_readl(host, SDHCI_ADMA_ERROR),
 113                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS));
 114                 }
 115         }
 116
 117         SDHCI_DUMP("============================================\n");
 118 }
 119 EXPORT_SYMBOL_GPL(sdhci_dumpregs);
 120
 121 /*****************************************************************************\
 122  *                                                                           *
 123  * Low level functions                                                       *
 124  *                                                                           *
 125 \*****************************************************************************/
 126
 127 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
 128 {
 129         return cmd->data || cmd->flags & MMC_RSP_BUSY;
 130 }
 131
 132 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 133 {
 134         u32 present;
 135
 136         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 137             !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
 138                 return;
 139
 140         if (enable) {
 141                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 142                                       SDHCI_CARD_PRESENT;
 143
 144                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 145                                        SDHCI_INT_CARD_INSERT;
 146         } else {
 147                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 148         }
 149
 150         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 151         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 152 }
 153
 154 static void sdhci_enable_card_detection(struct sdhci_host *host)
 155 {
 156         sdhci_set_card_detection(host, true);
 157 }
 158
 159 static void sdhci_disable_card_detection(struct sdhci_host *host)
 160 {
 161         sdhci_set_card_detection(host, false);
 162 }
 163
 164 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
 165 {
 166         if (host->bus_on)
 167                 return;
 168         host->bus_on = true;
 169         pm_runtime_get_noresume(host->mmc->parent);
 170 }
 171
 172 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
 173 {
 174         if (!host->bus_on)
 175                 return;
 176         host->bus_on = false;
 177         pm_runtime_put_noidle(host->mmc->parent);
 178 }
 179
 180 void sdhci_reset(struct sdhci_host *host, u8 mask)
 181 {
 182         ktime_t timeout;
 183
 184         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 185
 186         if (mask & SDHCI_RESET_ALL) {
 187                 host->clock = 0;
 188                 /* Reset-all turns off SD Bus Power */
 189                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 190                         sdhci_runtime_pm_bus_off(host);
 191         }
 192
 193         /* Wait max 100 ms */
 194         timeout = ktime_add_ms(ktime_get(), 100);
 195
 196         /* hw clears the bit when it's done */
 197         while (1) {
 198                 bool timedout = ktime_after(ktime_get(), timeout);
 199
 200                 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
 201                         break;
 202                 if (timedout) {
 203                         pr_err("%s: Reset 0x%x never completed.\n",
 204                                 mmc_hostname(host->mmc), (int)mask);
 205                         sdhci_dumpregs(host);
 206                         return;
 207                 }
 208                 udelay(10);
 209         }
 210 }
 211 EXPORT_SYMBOL_GPL(sdhci_reset);
 212
 213 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 214 {
 215         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 216                 struct mmc_host *mmc = host->mmc;
 217
 218                 if (!mmc->ops->get_cd(mmc))
 219                         return;
 220         }
 221
 222         host->ops->reset(host, mask);
 223
 224         if (mask & SDHCI_RESET_ALL) {
 225                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 226                         if (host->ops->enable_dma)
 227                                 host->ops->enable_dma(host);
 228                 }
 229
 230                 /* Resetting the controller clears many */
 231                 host->preset_enabled = false;
 232         }
 233 }
 234
 235 static void sdhci_set_default_irqs(struct sdhci_host *host)
 236 {
 237         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 238                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 239                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 240                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 241                     SDHCI_INT_RESPONSE;
 242
 243         if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
 244             host->tuning_mode == SDHCI_TUNING_MODE_3)
 245                 host->ier |= SDHCI_INT_RETUNE;
 246
 247         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 248         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 249 }
 250
 251 static void sdhci_init(struct sdhci_host *host, int soft)
 252 {
 253         struct mmc_host *mmc = host->mmc;
 254
 255         if (soft)
 256                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 257         else
 258                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 259
 260         sdhci_set_default_irqs(host);
 261
 262         host->cqe_on = false;
 263
 264         if (soft) {
 265                 /* force clock reconfiguration */
 266                 host->clock = 0;
 267                 host->reinit_uhs = true;
 268                 mmc->ops->set_ios(mmc, &mmc->ios);
 269         }
 270 }
 271
 272 static void sdhci_reinit(struct sdhci_host *host)
 273 {
 274         sdhci_init(host, 0);
 275         sdhci_enable_card_detection(host);
 276 }
 277
 278 static void __sdhci_led_activate(struct sdhci_host *host)
 279 {
 280         u8 ctrl;
 281
 282         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 283         ctrl |= SDHCI_CTRL_LED;
 284         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 285 }
 286
 287 static void __sdhci_led_deactivate(struct sdhci_host *host)
 288 {
 289         u8 ctrl;
 290
 291         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 292         ctrl &= ~SDHCI_CTRL_LED;
 293         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 294 }
 295
 296 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
 297 static void sdhci_led_control(struct led_classdev *led,
 298                               enum led_brightness brightness)
 299 {
 300         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 301         unsigned long flags;
 302
 303         spin_lock_irqsave(&host->lock, flags);
 304
 305         if (host->runtime_suspended)
 306                 goto out;
 307
 308         if (brightness == LED_OFF)
 309                 __sdhci_led_deactivate(host);
 310         else
 311                 __sdhci_led_activate(host);
 312 out:
 313         spin_unlock_irqrestore(&host->lock, flags);
 314 }
 315
 316 static int sdhci_led_register(struct sdhci_host *host)
 317 {
 318         struct mmc_host *mmc = host->mmc;
 319
 320         snprintf(host->led_name, sizeof(host->led_name),
 321                  "%s::", mmc_hostname(mmc));
 322
 323         host->led.name = host->led_name;
 324         host->led.brightness = LED_OFF;
 325         host->led.default_trigger = mmc_hostname(mmc);
 326         host->led.brightness_set = sdhci_led_control;
 327
 328         return led_classdev_register(mmc_dev(mmc), &host->led);
 329 }
 330
 331 static void sdhci_led_unregister(struct sdhci_host *host)
 332 {
 333         led_classdev_unregister(&host->led);
 334 }
 335
 336 static inline void sdhci_led_activate(struct sdhci_host *host)
 337 {
 338 }
 339
 340 static inline void sdhci_led_deactivate(struct sdhci_host *host)
 341 {
 342 }
 343
 344 #else
 345
 346 static inline int sdhci_led_register(struct sdhci_host *host)
 347 {
 348         return 0;
 349 }
 350
 351 static inline void sdhci_led_unregister(struct sdhci_host *host)
 352 {
 353 }
 354
 355 static inline void sdhci_led_activate(struct sdhci_host *host)
 356 {
 357         __sdhci_led_activate(host);
 358 }
 359
 360 static inline void sdhci_led_deactivate(struct sdhci_host *host)
 361 {
 362         __sdhci_led_deactivate(host);
 363 }
 364
 365 #endif
 366
 367 /*****************************************************************************\
 368  *                                                                           *
 369  * Core functions                                                            *
 370  *                                                                           *
 371 \*****************************************************************************/
 372
 373 static void sdhci_read_block_pio(struct sdhci_host *host)
 374 {
 375         unsigned long flags;
 376         size_t blksize, len, chunk;
 377         u32 scratch;
 378         u8 *buf;
 379
 380         DBG("PIO reading\n");
 381
 382         blksize = host->data->blksz;
 383         chunk = 0;
 384
 385         local_irq_save(flags);
 386
 387         while (blksize) {
 388                 BUG_ON(!sg_miter_next(&host->sg_miter));
 389
 390                 len = min(host->sg_miter.length, blksize);
 391
 392                 blksize -= len;
 393                 host->sg_miter.consumed = len;
 394
 395                 buf = host->sg_miter.addr;
 396
 397                 while (len) {
 398                         if (chunk == 0) {
 399                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 400                                 chunk = 4;
 401                         }
 402
 403                         *buf = scratch & 0xFF;
 404
 405                         buf++;
 406                         scratch >>= 8;
 407                         chunk--;
 408                         len--;
 409                 }
 410         }
 411
 412         sg_miter_stop(&host->sg_miter);
 413
 414         local_irq_restore(flags);
 415 }
 416
 417 static void sdhci_write_block_pio(struct sdhci_host *host)
 418 {
 419         unsigned long flags;
 420         size_t blksize, len, chunk;
 421         u32 scratch;
 422         u8 *buf;
 423
 424         DBG("PIO writing\n");
 425
 426         blksize = host->data->blksz;
 427         chunk = 0;
 428         scratch = 0;
 429
 430         local_irq_save(flags);
 431
 432         while (blksize) {
 433                 BUG_ON(!sg_miter_next(&host->sg_miter));
 434
 435                 len = min(host->sg_miter.length, blksize);
 436
 437                 blksize -= len;
 438                 host->sg_miter.consumed = len;
 439
 440                 buf = host->sg_miter.addr;
 441
 442                 while (len) {
 443                         scratch |= (u32)*buf << (chunk * 8);
 444
 445                         buf++;
 446                         chunk++;
 447                         len--;
 448
 449                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 450                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 451                                 chunk = 0;
 452                                 scratch = 0;
 453                         }
 454                 }
 455         }
 456
 457         sg_miter_stop(&host->sg_miter);
 458
 459         local_irq_restore(flags);
 460 }
 461
 462 static void sdhci_transfer_pio(struct sdhci_host *host)
 463 {
 464         u32 mask;
 465
 466         if (host->blocks == 0)
 467                 return;
 468
 469         if (host->data->flags & MMC_DATA_READ)
 470                 mask = SDHCI_DATA_AVAILABLE;
 471         else
 472                 mask = SDHCI_SPACE_AVAILABLE;
 473
 474         /*
 475          * Some controllers (JMicron JMB38x) mess up the buffer bits
 476          * for transfers < 4 bytes. As long as it is just one block,
 477          * we can ignore the bits.
 478          */
 479         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 480                 (host->data->blocks == 1))
 481                 mask = ~0;
 482
 483         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 484                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 485                         udelay(100);
 486
 487                 if (host->data->flags & MMC_DATA_READ)
 488                         sdhci_read_block_pio(host);
 489                 else
 490                         sdhci_write_block_pio(host);
 491
 492                 host->blocks--;
 493                 if (host->blocks == 0)
 494                         break;
 495         }
 496
 497         DBG("PIO transfer complete.\n");
 498 }
 499
 500 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
 501                                   struct mmc_data *data, int cookie)
 502 {
 503         int sg_count;
 504
 505         /*
 506          * If the data buffers are already mapped, return the previous
 507          * dma_map_sg() result.
 508          */
 509         if (data->host_cookie == COOKIE_PRE_MAPPED)
 510                 return data->sg_count;
 511
 512         /* Bounce write requests to the bounce buffer */
 513         if (host->bounce_buffer) {
 514                 unsigned int length = data->blksz * data->blocks;
 515
 516                 if (length > host->bounce_buffer_size) {
 517                         pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
 518                                mmc_hostname(host->mmc), length,
 519                                host->bounce_buffer_size);
 520                         return -EIO;
 521                 }
 522                 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
 523                         /* Copy the data to the bounce buffer */
 524                         sg_copy_to_buffer(data->sg, data->sg_len,
 525                                           host->bounce_buffer,
 526                                           length);
 527                 }
 528                 /* Switch ownership to the DMA */
 529                 dma_sync_single_for_device(host->mmc->parent,
 530                                            host->bounce_addr,
 531                                            host->bounce_buffer_size,
 532                                            mmc_get_dma_dir(data));
 533                 /* Just a dummy value */
 534                 sg_count = 1;
 535         } else {
 536                 /* Just access the data directly from memory */
 537                 sg_count = dma_map_sg(mmc_dev(host->mmc),
 538                                       data->sg, data->sg_len,
 539                                       mmc_get_dma_dir(data));
 540         }
 541
 542         if (sg_count == 0)
 543                 return -ENOSPC;
 544
 545         data->sg_count = sg_count;
 546         data->host_cookie = cookie;
 547
 548         return sg_count;
 549 }
 550
 551 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 552 {
 553         local_irq_save(*flags);
 554         return kmap_atomic(sg_page(sg)) + sg->offset;
 555 }
 556
 557 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 558 {
 559         kunmap_atomic(buffer);
 560         local_irq_restore(*flags);
 561 }
 562
 563 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
 564                                   dma_addr_t addr, int len, unsigned cmd)
 565 {
 566         struct sdhci_adma2_64_desc *dma_desc = desc;
 567
 568         /* 32-bit and 64-bit descriptors have these members in same position */
 569         dma_desc->cmd = cpu_to_le16(cmd);
 570         dma_desc->len = cpu_to_le16(len);
 571         dma_desc->addr_lo = cpu_to_le32((u32)addr);
 572
 573         if (host->flags & SDHCI_USE_64_BIT_DMA)
 574                 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
 575 }
 576
 577 static void sdhci_adma_mark_end(void *desc)
 578 {
 579         struct sdhci_adma2_64_desc *dma_desc = desc;
 580
 581         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 582         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 583 }
 584
 585 static void sdhci_adma_table_pre(struct sdhci_host *host,
 586         struct mmc_data *data, int sg_count)
 587 {
 588         struct scatterlist *sg;
 589         unsigned long flags;
 590         dma_addr_t addr, align_addr;
 591         void *desc, *align;
 592         char *buffer;
 593         int len, offset, i;
 594
 595         /*
 596          * The spec does not specify endianness of descriptor table.
 597          * We currently guess that it is LE.
 598          */
 599
 600         host->sg_count = sg_count;
 601
 602         desc = host->adma_table;
 603         align = host->align_buffer;
 604
 605         align_addr = host->align_addr;
 606
 607         for_each_sg(data->sg, sg, host->sg_count, i) {
 608                 addr = sg_dma_address(sg);
 609                 len = sg_dma_len(sg);
 610
 611                 /*
 612                  * The SDHCI specification states that ADMA addresses must
 613                  * be 32-bit aligned. If they aren't, then we use a bounce
 614                  * buffer for the (up to three) bytes that screw up the
 615                  * alignment.
 616                  */
 617                 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
 618                          SDHCI_ADMA2_MASK;
 619                 if (offset) {
 620                         if (data->flags & MMC_DATA_WRITE) {
 621                                 buffer = sdhci_kmap_atomic(sg, &flags);
 622                                 memcpy(align, buffer, offset);
 623                                 sdhci_kunmap_atomic(buffer, &flags);
 624                         }
 625
 626                         /* tran, valid */
 627                         sdhci_adma_write_desc(host, desc, align_addr, offset,
 628                                               ADMA2_TRAN_VALID);
 629
 630                         BUG_ON(offset > 65536);
 631
 632                         align += SDHCI_ADMA2_ALIGN;
 633                         align_addr += SDHCI_ADMA2_ALIGN;
 634
 635                         desc += host->desc_sz;
 636
 637                         addr += offset;
 638                         len -= offset;
 639                 }
 640
 641                 BUG_ON(len > 65536);
 642
 643                 if (len) {
 644                         /* tran, valid */
 645                         sdhci_adma_write_desc(host, desc, addr, len,
 646                                               ADMA2_TRAN_VALID);
 647                         desc += host->desc_sz;
 648                 }
 649
 650                 /*
 651                  * If this triggers then we have a calculation bug
 652                  * somewhere. :/
 653                  */
 654                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 655         }
 656
 657         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 658                 /* Mark the last descriptor as the terminating descriptor */
 659                 if (desc != host->adma_table) {
 660                         desc -= host->desc_sz;
 661                         sdhci_adma_mark_end(desc);
 662                 }
 663         } else {
 664                 /* Add a terminating entry - nop, end, valid */
 665                 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
 666         }
 667 }
 668
 669 static void sdhci_adma_table_post(struct sdhci_host *host,
 670         struct mmc_data *data)
 671 {
 672         struct scatterlist *sg;
 673         int i, size;
 674         void *align;
 675         char *buffer;
 676         unsigned long flags;
 677
 678         if (data->flags & MMC_DATA_READ) {
 679                 bool has_unaligned = false;
 680
 681                 /* Do a quick scan of the SG list for any unaligned mappings */
 682                 for_each_sg(data->sg, sg, host->sg_count, i)
 683                         if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 684                                 has_unaligned = true;
 685                                 break;
 686                         }
 687
 688                 if (has_unaligned) {
 689                         dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 690                                             data->sg_len, DMA_FROM_DEVICE);
 691
 692                         align = host->align_buffer;
 693
 694                         for_each_sg(data->sg, sg, host->sg_count, i) {
 695                                 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 696                                         size = SDHCI_ADMA2_ALIGN -
 697                                                (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
 698
 699                                         buffer = sdhci_kmap_atomic(sg, &flags);
 700                                         memcpy(buffer, align, size);
 701                                         sdhci_kunmap_atomic(buffer, &flags);
 702
 703                                         align += SDHCI_ADMA2_ALIGN;
 704                                 }
 705                         }
 706                 }
 707         }
 708 }
 709
 710 static u32 sdhci_sdma_address(struct sdhci_host *host)
 711 {
 712         if (host->bounce_buffer)
 713                 return host->bounce_addr;
 714         else
 715                 return sg_dma_address(host->data->sg);
 716 }
 717
 718 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 719 {
 720         u8 count;
 721         struct mmc_data *data = cmd->data;
 722         unsigned target_timeout, current_timeout;
 723
 724         /*
 725          * If the host controller provides us with an incorrect timeout
 726          * value, just skip the check and use 0xE.  The hardware may take
 727          * longer to time out, but that's much better than having a too-short
 728          * timeout value.
 729          */
 730         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 731                 return 0xE;
 732
 733         /* Unspecified timeout, assume max */
 734         if (!data && !cmd->busy_timeout)
 735                 return 0xE;
 736
 737         /* timeout in us */
 738         if (!data)
 739                 target_timeout = cmd->busy_timeout * 1000;
 740         else {
 741                 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
 742                 if (host->clock && data->timeout_clks) {
 743                         unsigned long long val;
 744
 745                         /*
 746                          * data->timeout_clks is in units of clock cycles.
 747                          * host->clock is in Hz.  target_timeout is in us.
 748                          * Hence, us = 1000000 * cycles / Hz.  Round up.
 749                          */
 750                         val = 1000000ULL * data->timeout_clks;
 751                         if (do_div(val, host->clock))
 752                                 target_timeout++;
 753                         target_timeout += val;
 754                 }
 755         }
 756
 757         /*
 758          * Figure out needed cycles.
 759          * We do this in steps in order to fit inside a 32 bit int.
 760          * The first step is the minimum timeout, which will have a
 761          * minimum resolution of 6 bits:
 762          * (1) 2^13*1000 > 2^22,
 763          * (2) host->timeout_clk < 2^16
 764          *     =>
 765          *     (1) / (2) > 2^6
 766          */
 767         count = 0;
 768         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 769         while (current_timeout < target_timeout) {
 770                 count++;
 771                 current_timeout <<= 1;
 772                 if (count >= 0xF)
 773                         break;
 774         }
 775
 776         if (count >= 0xF) {
 777                 DBG("Too large timeout 0x%x requested for CMD%d!\n",
 778                     count, cmd->opcode);
 779                 count = 0xE;
 780         }
 781
 782         return count;
 783 }
 784
 785 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 786 {
 787         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 788         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 789
 790         if (host->flags & SDHCI_REQ_USE_DMA)
 791                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 792         else
 793                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 794
 795         if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
 796                 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
 797         else
 798                 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
 799
 800         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 801         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 802 }
 803
 804 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 805 {
 806         u8 count;
 807
 808         if (host->ops->set_timeout) {
 809                 host->ops->set_timeout(host, cmd);
 810         } else {
 811                 count = sdhci_calc_timeout(host, cmd);
 812                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 813         }
 814 }
 815
 816 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 817 {
 818         u8 ctrl;
 819         struct mmc_data *data = cmd->data;
 820
 821         if (sdhci_data_line_cmd(cmd))
 822                 sdhci_set_timeout(host, cmd);
 823
 824         if (!data)
 825                 return;
 826
 827         WARN_ON(host->data);
 828
 829         /* Sanity checks */
 830         BUG_ON(data->blksz * data->blocks > 524288);
 831         BUG_ON(data->blksz > host->mmc->max_blk_size);
 832         BUG_ON(data->blocks > 65535);
 833
 834         host->data = data;
 835         host->data_early = 0;
 836         host->data->bytes_xfered = 0;
 837
 838         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 839                 struct scatterlist *sg;
 840                 unsigned int length_mask, offset_mask;
 841                 int i;
 842
 843                 host->flags |= SDHCI_REQ_USE_DMA;
 844
 845                 /*
 846                  * FIXME: This doesn't account for merging when mapping the
 847                  * scatterlist.
 848                  *
 849                  * The assumption here being that alignment and lengths are
 850                  * the same after DMA mapping to device address space.
 851                  */
 852                 length_mask = 0;
 853                 offset_mask = 0;
 854                 if (host->flags & SDHCI_USE_ADMA) {
 855                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
 856                                 length_mask = 3;
 857                                 /*
 858                                  * As we use up to 3 byte chunks to work
 859                                  * around alignment problems, we need to
 860                                  * check the offset as well.
 861                                  */
 862                                 offset_mask = 3;
 863                         }
 864                 } else {
 865                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 866                                 length_mask = 3;
 867                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 868                                 offset_mask = 3;
 869                 }
 870
 871                 if (unlikely(length_mask | offset_mask)) {
 872                         for_each_sg(data->sg, sg, data->sg_len, i) {
 873                                 if (sg->length & length_mask) {
 874                                         DBG("Reverting to PIO because of transfer size (%d)\n",
 875                                             sg->length);
 876                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 877                                         break;
 878                                 }
 879                                 if (sg->offset & offset_mask) {
 880                                         DBG("Reverting to PIO because of bad alignment\n");
 881                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 882                                         break;
 883                                 }
 884                         }
 885                 }
 886         }
 887
 888         if (host->flags & SDHCI_REQ_USE_DMA) {
 889                 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
 890
 891                 if (sg_cnt <= 0) {
 892                         /*
 893                          * This only happens when someone fed
 894                          * us an invalid request.
 895                          */
 896                         WARN_ON(1);
 897                         host->flags &= ~SDHCI_REQ_USE_DMA;
 898                 } else if (host->flags & SDHCI_USE_ADMA) {
 899                         sdhci_adma_table_pre(host, data, sg_cnt);
 900
 901                         sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
 902                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 903                                 sdhci_writel(host,
 904                                              (u64)host->adma_addr >> 32,
 905                                              SDHCI_ADMA_ADDRESS_HI);
 906                 } else {
 907                         WARN_ON(sg_cnt != 1);
 908                         sdhci_writel(host, sdhci_sdma_address(host),
 909                                      SDHCI_DMA_ADDRESS);
 910                 }
 911         }
 912
 913         /*
 914          * Always adjust the DMA selection as some controllers
 915          * (e.g. JMicron) can't do PIO properly when the selection
 916          * is ADMA.
 917          */
 918         if (host->version >= SDHCI_SPEC_200) {
 919                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 920                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 921                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 922                         (host->flags & SDHCI_USE_ADMA)) {
 923                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 924                                 ctrl |= SDHCI_CTRL_ADMA64;
 925                         else
 926                                 ctrl |= SDHCI_CTRL_ADMA32;
 927                 } else {
 928                         ctrl |= SDHCI_CTRL_SDMA;
 929                 }
 930                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 931         }
 932
 933         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 934                 int flags;
 935
 936                 flags = SG_MITER_ATOMIC;
 937                 if (host->data->flags & MMC_DATA_READ)
 938                         flags |= SG_MITER_TO_SG;
 939                 else
 940                         flags |= SG_MITER_FROM_SG;
 941                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 942                 host->blocks = data->blocks;
 943         }
 944
 945         sdhci_set_transfer_irqs(host);
 946
 947         /* Set the DMA boundary value and block size */
 948         sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
 949                      SDHCI_BLOCK_SIZE);
 950         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 951 }
 952
 953 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
 954                                     struct mmc_request *mrq)
 955 {
 956         return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
 957                !mrq->cap_cmd_during_tfr;
 958 }
 959
 960 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 961         struct mmc_command *cmd)
 962 {
 963         u16 mode = 0;
 964         struct mmc_data *data = cmd->data;
 965
 966         if (data == NULL) {
 967                 if (host->quirks2 &
 968                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
 969                         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
 970                 } else {
 971                 /* clear Auto CMD settings for no data CMDs */
 972                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 973                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 974                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 975                 }
 976                 return;
 977         }
 978
 979         WARN_ON(!host->data);
 980
 981         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
 982                 mode = SDHCI_TRNS_BLK_CNT_EN;
 983
 984         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 985                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
 986                 /*
 987                  * If we are sending CMD23, CMD12 never gets sent
 988                  * on successful completion (so no Auto-CMD12).
 989                  */
 990                 if (sdhci_auto_cmd12(host, cmd->mrq) &&
 991                     (cmd->opcode != SD_IO_RW_EXTENDED))
 992                         mode |= SDHCI_TRNS_AUTO_CMD12;
 993                 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 994                         mode |= SDHCI_TRNS_AUTO_CMD23;
 995                         sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
 996                 }
 997         }
 998
 999         if (data->flags & MMC_DATA_READ)
1000                 mode |= SDHCI_TRNS_READ;
1001         if (host->flags & SDHCI_REQ_USE_DMA)
1002                 mode |= SDHCI_TRNS_DMA;
1003
1004         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1005 }
1006
1007 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1008 {
1009         return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1010                 ((mrq->cmd && mrq->cmd->error) ||
1011                  (mrq->sbc && mrq->sbc->error) ||
1012                  (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1013                  (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1014 }
1015
1016 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1017 {
1018         int i;
1019
1020         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1021                 if (host->mrqs_done[i] == mrq) {
1022                         WARN_ON(1);
1023                         return;
1024                 }
1025         }
1026
1027         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1028                 if (!host->mrqs_done[i]) {
1029                         host->mrqs_done[i] = mrq;
1030                         break;
1031                 }
1032         }
1033
1034         WARN_ON(i >= SDHCI_MAX_MRQS);
1035
1036         tasklet_schedule(&host->finish_tasklet);
1037 }
1038
1039 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1040 {
1041         if (host->cmd && host->cmd->mrq == mrq)
1042                 host->cmd = NULL;
1043
1044         if (host->data_cmd && host->data_cmd->mrq == mrq)
1045                 host->data_cmd = NULL;
1046
1047         if (host->data && host->data->mrq == mrq)
1048                 host->data = NULL;
1049
1050         if (sdhci_needs_reset(host, mrq))
1051                 host->pending_reset = true;
1052
1053         __sdhci_finish_mrq(host, mrq);
1054 }
1055
1056 static void sdhci_finish_data(struct sdhci_host *host)
1057 {
1058         struct mmc_command *data_cmd = host->data_cmd;
1059         struct mmc_data *data = host->data;
1060
1061         host->data = NULL;
1062         host->data_cmd = NULL;
1063
1064         /*
1065          * The controller needs a reset of internal state machines upon error
1066          * conditions.
1067          */
1068         if (data->error) {
1069                 if (!host->cmd || host->cmd == data_cmd)
1070                         sdhci_do_reset(host, SDHCI_RESET_CMD);
1071                 sdhci_do_reset(host, SDHCI_RESET_DATA);
1072         }
1073
1074         if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1075             (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1076                 sdhci_adma_table_post(host, data);
1077
1078         /*
1079          * The specification states that the block count register must
1080          * be updated, but it does not specify at what point in the
1081          * data flow. That makes the register entirely useless to read
1082          * back so we have to assume that nothing made it to the card
1083          * in the event of an error.
1084          */
1085         if (data->error)
1086                 data->bytes_xfered = 0;
1087         else
1088                 data->bytes_xfered = data->blksz * data->blocks;
1089
1090         /*
1091          * Need to send CMD12 if -
1092          * a) open-ended multiblock transfer (no CMD23)
1093          * b) error in multiblock transfer
1094          */
1095         if (data->stop &&
1096             (data->error ||
1097              !data->mrq->sbc)) {
1098                 /*
1099                  * 'cap_cmd_during_tfr' request must not use the command line
1100                  * after mmc_command_done() has been called. It is upper layer's
1101                  * responsibility to send the stop command if required.
1102                  */
1103                 if (data->mrq->cap_cmd_during_tfr) {
1104                         sdhci_finish_mrq(host, data->mrq);
1105                 } else {
1106                         /* Avoid triggering warning in sdhci_send_command() */
1107                         host->cmd = NULL;
1108                         sdhci_send_command(host, data->stop);
1109                 }
1110         } else {
1111                 sdhci_finish_mrq(host, data->mrq);
1112         }
1113 }
1114
1115 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1116                             unsigned long timeout)
1117 {
1118         if (sdhci_data_line_cmd(mrq->cmd))
1119                 mod_timer(&host->data_timer, timeout);
1120         else
1121                 mod_timer(&host->timer, timeout);
1122 }
1123
1124 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1125 {
1126         if (sdhci_data_line_cmd(mrq->cmd))
1127                 del_timer(&host->data_timer);
1128         else
1129                 del_timer(&host->timer);
1130 }
1131
1132 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1133 {
1134         int flags;
1135         u32 mask;
1136         unsigned long timeout;
1137
1138         WARN_ON(host->cmd);
1139
1140         /* Initially, a command has no error */
1141         cmd->error = 0;
1142
1143         if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1144             cmd->opcode == MMC_STOP_TRANSMISSION)
1145                 cmd->flags |= MMC_RSP_BUSY;
1146
1147         /* Wait max 10 ms */
1148         timeout = 10;
1149
1150         mask = SDHCI_CMD_INHIBIT;
1151         if (sdhci_data_line_cmd(cmd))
1152                 mask |= SDHCI_DATA_INHIBIT;
1153
1154         /* We shouldn't wait for data inihibit for stop commands, even
1155            though they might use busy signaling */
1156         if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1157                 mask &= ~SDHCI_DATA_INHIBIT;
1158
1159         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1160                 if (timeout == 0) {
1161                         pr_err("%s: Controller never released inhibit bit(s).\n",
1162                                mmc_hostname(host->mmc));
1163                         sdhci_dumpregs(host);
1164                         cmd->error = -EIO;
1165                         sdhci_finish_mrq(host, cmd->mrq);
1166                         return;
1167                 }
1168                 timeout--;
1169                 mdelay(1);
1170         }
1171
1172         timeout = jiffies;
1173         if (!cmd->data && cmd->busy_timeout > 9000)
1174                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1175         else
1176                 timeout += 10 * HZ;
1177         sdhci_mod_timer(host, cmd->mrq, timeout);
1178
1179         host->cmd = cmd;
1180         if (sdhci_data_line_cmd(cmd)) {
1181                 WARN_ON(host->data_cmd);
1182                 host->data_cmd = cmd;
1183         }
1184
1185         sdhci_prepare_data(host, cmd);
1186
1187         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1188
1189         sdhci_set_transfer_mode(host, cmd);
1190
1191         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1192                 pr_err("%s: Unsupported response type!\n",
1193                         mmc_hostname(host->mmc));
1194                 cmd->error = -EINVAL;
1195                 sdhci_finish_mrq(host, cmd->mrq);
1196                 return;
1197         }
1198
1199         if (!(cmd->flags & MMC_RSP_PRESENT))
1200                 flags = SDHCI_CMD_RESP_NONE;
1201         else if (cmd->flags & MMC_RSP_136)
1202                 flags = SDHCI_CMD_RESP_LONG;
1203         else if (cmd->flags & MMC_RSP_BUSY)
1204                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1205         else
1206                 flags = SDHCI_CMD_RESP_SHORT;
1207
1208         if (cmd->flags & MMC_RSP_CRC)
1209                 flags |= SDHCI_CMD_CRC;
1210         if (cmd->flags & MMC_RSP_OPCODE)
1211                 flags |= SDHCI_CMD_INDEX;
1212
1213         /* CMD19 is special in that the Data Present Select should be set */
1214         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1215             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1216                 flags |= SDHCI_CMD_DATA;
1217
1218         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1219 }
1220 EXPORT_SYMBOL_GPL(sdhci_send_command);
1221
1222 static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1223 {
1224         int i, reg;
1225
1226         for (i = 0; i < 4; i++) {
1227                 reg = SDHCI_RESPONSE + (3 - i) * 4;
1228                 cmd->resp[i] = sdhci_readl(host, reg);
1229         }
1230
1231         if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1232                 return;
1233
1234         /* CRC is stripped so we need to do some shifting */
1235         for (i = 0; i < 4; i++) {
1236                 cmd->resp[i] <<= 8;
1237                 if (i != 3)
1238                         cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1239         }
1240 }
1241
1242 static void sdhci_finish_command(struct sdhci_host *host)
1243 {
1244         struct mmc_command *cmd = host->cmd;
1245
1246         host->cmd = NULL;
1247
1248         if (cmd->flags & MMC_RSP_PRESENT) {
1249                 if (cmd->flags & MMC_RSP_136) {
1250                         sdhci_read_rsp_136(host, cmd);
1251                 } else {
1252                         cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1253                 }
1254         }
1255
1256         if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1257                 mmc_command_done(host->mmc, cmd->mrq);
1258
1259         /*
1260          * The host can send and interrupt when the busy state has
1261          * ended, allowing us to wait without wasting CPU cycles.
1262          * The busy signal uses DAT0 so this is similar to waiting
1263          * for data to complete.
1264          *
1265          * Note: The 1.0 specification is a bit ambiguous about this
1266          *       feature so there might be some problems with older
1267          *       controllers.
1268          */
1269         if (cmd->flags & MMC_RSP_BUSY) {
1270                 if (cmd->data) {
1271                         DBG("Cannot wait for busy signal when also doing a data transfer");
1272                 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1273                            cmd == host->data_cmd) {
1274                         /* Command complete before busy is ended */
1275                         return;
1276                 }
1277         }
1278
1279         /* Finished CMD23, now send actual command. */
1280         if (cmd == cmd->mrq->sbc) {
1281                 sdhci_send_command(host, cmd->mrq->cmd);
1282         } else {
1283
1284                 /* Processed actual command. */
1285                 if (host->data && host->data_early)
1286                         sdhci_finish_data(host);
1287
1288                 if (!cmd->data)
1289                         sdhci_finish_mrq(host, cmd->mrq);
1290         }
1291 }
1292
1293 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1294 {
1295         u16 preset = 0;
1296
1297         switch (host->timing) {
1298         case MMC_TIMING_MMC_HS:
1299         case MMC_TIMING_SD_HS:
1300                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1301                 break;
1302         case MMC_TIMING_UHS_SDR12:
1303                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1304                 break;
1305         case MMC_TIMING_UHS_SDR25:
1306                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1307                 break;
1308         case MMC_TIMING_UHS_SDR50:
1309                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1310                 break;
1311         case MMC_TIMING_UHS_SDR104:
1312         case MMC_TIMING_MMC_HS200:
1313                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1314                 break;
1315         case MMC_TIMING_UHS_DDR50:
1316         case MMC_TIMING_MMC_DDR52:
1317                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1318                 break;
1319         case MMC_TIMING_MMC_HS400:
1320                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1321                 break;
1322         default:
1323                 pr_warn("%s: Invalid UHS-I mode selected\n",
1324                         mmc_hostname(host->mmc));
1325                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1326                 break;
1327         }
1328         return preset;
1329 }
1330
1331 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1332                    unsigned int *actual_clock)
1333 {
1334         int div = 0; /* Initialized for compiler warning */
1335         int real_div = div, clk_mul = 1;
1336         u16 clk = 0;
1337         bool switch_base_clk = false;
1338
1339         if (host->version >= SDHCI_SPEC_300) {
1340                 if (host->preset_enabled) {
1341                         u16 pre_val;
1342
1343                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1344                         pre_val = sdhci_get_preset_value(host);
1345                         div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
1346                         if (host->clk_mul &&
1347                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
1348                                 clk = SDHCI_PROG_CLOCK_MODE;
1349                                 real_div = div + 1;
1350                                 clk_mul = host->clk_mul;
1351                         } else {
1352                                 real_div = max_t(int, 1, div << 1);
1353                         }
1354                         goto clock_set;
1355                 }
1356
1357                 /*
1358                  * Check if the Host Controller supports Programmable Clock
1359                  * Mode.
1360                  */
1361                 if (host->clk_mul) {
1362                         for (div = 1; div <= 1024; div++) {
1363                                 if ((host->max_clk * host->clk_mul / div)
1364                                         <= clock)
1365                                         break;
1366                         }
1367                         if ((host->max_clk * host->clk_mul / div) <= clock) {
1368                                 /*
1369                                  * Set Programmable Clock Mode in the Clock
1370                                  * Control register.
1371                                  */
1372                                 clk = SDHCI_PROG_CLOCK_MODE;
1373                                 real_div = div;
1374                                 clk_mul = host->clk_mul;
1375                                 div--;
1376                         } else {
1377                                 /*
1378                                  * Divisor can be too small to reach clock
1379                                  * speed requirement. Then use the base clock.
1380                                  */
1381                                 switch_base_clk = true;
1382                         }
1383                 }
1384
1385                 if (!host->clk_mul || switch_base_clk) {
1386                         /* Version 3.00 divisors must be a multiple of 2. */
1387                         if (host->max_clk <= clock)
1388                                 div = 1;
1389                         else {
1390                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1391                                      div += 2) {
1392                                         if ((host->max_clk / div) <= clock)
1393                                                 break;
1394                                 }
1395                         }
1396                         real_div = div;
1397                         div >>= 1;
1398                         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1399                                 && !div && host->max_clk <= 25000000)
1400                                 div = 1;
1401                 }
1402         } else {
1403                 /* Version 2.00 divisors must be a power of 2. */
1404                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1405                         if ((host->max_clk / div) <= clock)
1406                                 break;
1407                 }
1408                 real_div = div;
1409                 div >>= 1;
1410         }
1411
1412 clock_set:
1413         if (real_div)
1414                 *actual_clock = (host->max_clk * clk_mul) / real_div;
1415         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1416         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1417                 << SDHCI_DIVIDER_HI_SHIFT;
1418
1419         return clk;
1420 }
1421 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1422
1423 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1424 {
1425         ktime_t timeout;
1426
1427         clk |= SDHCI_CLOCK_INT_EN;
1428         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1429
1430         /* Wait max 20 ms */
1431         timeout = ktime_add_ms(ktime_get(), 20);
1432         while (1) {
1433                 bool timedout = ktime_after(ktime_get(), timeout);
1434
1435                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1436                 if (clk & SDHCI_CLOCK_INT_STABLE)
1437                         break;
1438                 if (timedout) {
1439                         pr_err("%s: Internal clock never stabilised.\n",
1440                                mmc_hostname(host->mmc));
1441                         sdhci_dumpregs(host);
1442                         return;
1443                 }
1444                 udelay(10);
1445         }
1446
1447         clk |= SDHCI_CLOCK_CARD_EN;
1448         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1449 }
1450 EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1451
1452 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1453 {
1454         u16 clk;
1455
1456         host->mmc->actual_clock = 0;
1457
1458         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1459
1460         if (clock == 0)
1461                 return;
1462
1463         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1464         sdhci_enable_clk(host, clk);
1465 }
1466 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1467
1468 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1469                                 unsigned short vdd)
1470 {
1471         struct mmc_host *mmc = host->mmc;
1472
1473         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1474
1475         if (mode != MMC_POWER_OFF)
1476                 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1477         else
1478                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1479 }
1480
1481 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1482                            unsigned short vdd)
1483 {
1484         u8 pwr = 0;
1485
1486         if (mode != MMC_POWER_OFF) {
1487                 switch (1 << vdd) {
1488                 case MMC_VDD_165_195:
1489                 /*
1490                  * Without a regulator, SDHCI does not support 2.0v
1491                  * so we only get here if the driver deliberately
1492                  * added the 2.0v range to ocr_avail. Map it to 1.8v
1493                  * for the purpose of turning on the power.
1494                  */
1495                 case MMC_VDD_20_21:
1496                         pwr = SDHCI_POWER_180;
1497                         break;
1498                 case MMC_VDD_29_30:
1499                 case MMC_VDD_30_31:
1500                         pwr = SDHCI_POWER_300;
1501                         break;
1502                 case MMC_VDD_32_33:
1503                 case MMC_VDD_33_34:
1504                 /*
1505                  * 3.4 ~ 3.6V are valid only for those platforms where it's
1506                  * known that the voltage range is supported by hardware.
1507                  */
1508                 case MMC_VDD_34_35:
1509                 case MMC_VDD_35_36:
1510                         pwr = SDHCI_POWER_330;
1511                         break;
1512                 default:
1513                         WARN(1, "%s: Invalid vdd %#x\n",
1514                              mmc_hostname(host->mmc), vdd);
1515                         break;
1516                 }
1517         }
1518
1519         if (host->pwr == pwr)
1520                 return;
1521
1522         host->pwr = pwr;
1523
1524         if (pwr == 0) {
1525                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1526                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1527                         sdhci_runtime_pm_bus_off(host);
1528         } else {
1529                 /*
1530                  * Spec says that we should clear the power reg before setting
1531                  * a new value. Some controllers don't seem to like this though.
1532                  */
1533                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1534                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1535
1536                 /*
1537                  * At least the Marvell CaFe chip gets confused if we set the
1538                  * voltage and set turn on power at the same time, so set the
1539                  * voltage first.
1540                  */
1541                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1542                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1543
1544                 pwr |= SDHCI_POWER_ON;
1545
1546                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1547
1548                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1549                         sdhci_runtime_pm_bus_on(host);
1550
1551                 /*
1552                  * Some controllers need an extra 10ms delay of 10ms before
1553                  * they can apply clock after applying power
1554                  */
1555                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1556                         mdelay(10);
1557         }
1558 }
1559 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1560
1561 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1562                      unsigned short vdd)
1563 {
1564         if (IS_ERR(host->mmc->supply.vmmc))
1565                 sdhci_set_power_noreg(host, mode, vdd);
1566         else
1567                 sdhci_set_power_reg(host, mode, vdd);
1568 }
1569 EXPORT_SYMBOL_GPL(sdhci_set_power);
1570
1571 /*****************************************************************************\
1572  *                                                                           *
1573  * MMC callbacks                                                             *
1574  *                                                                           *
1575 \*****************************************************************************/
1576
1577 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1578 {
1579         struct sdhci_host *host;
1580         int present;
1581         unsigned long flags;
1582
1583         host = mmc_priv(mmc);
1584
1585         /* Firstly check card presence */
1586         present = mmc->ops->get_cd(mmc);
1587
1588         spin_lock_irqsave(&host->lock, flags);
1589
1590         sdhci_led_activate(host);
1591
1592         /*
1593          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1594          * requests if Auto-CMD12 is enabled.
1595          */
1596         if (sdhci_auto_cmd12(host, mrq)) {
1597                 if (mrq->stop) {
1598                         mrq->data->stop = NULL;
1599                         mrq->stop = NULL;
1600                 }
1601         }
1602
1603         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1604                 mrq->cmd->error = -ENOMEDIUM;
1605                 sdhci_finish_mrq(host, mrq);
1606         } else {
1607                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1608                         sdhci_send_command(host, mrq->sbc);
1609                 else
1610                         sdhci_send_command(host, mrq->cmd);
1611         }
1612
1613         mmiowb();
1614         spin_unlock_irqrestore(&host->lock, flags);
1615 }
1616
1617 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1618 {
1619         u8 ctrl;
1620
1621         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1622         if (width == MMC_BUS_WIDTH_8) {
1623                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1624                 ctrl |= SDHCI_CTRL_8BITBUS;
1625         } else {
1626                 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
1627                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1628                 if (width == MMC_BUS_WIDTH_4)
1629                         ctrl |= SDHCI_CTRL_4BITBUS;
1630                 else
1631                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1632         }
1633         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1634 }
1635 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1636
1637 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1638 {
1639         u16 ctrl_2;
1640
1641         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1642         /* Select Bus Speed Mode for host */
1643         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1644         if ((timing == MMC_TIMING_MMC_HS200) ||
1645             (timing == MMC_TIMING_UHS_SDR104))
1646                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1647         else if (timing == MMC_TIMING_UHS_SDR12)
1648                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1649         else if (timing == MMC_TIMING_UHS_SDR25)
1650                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1651         else if (timing == MMC_TIMING_UHS_SDR50)
1652                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1653         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1654                  (timing == MMC_TIMING_MMC_DDR52))
1655                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1656         else if (timing == MMC_TIMING_MMC_HS400)
1657                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1658         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1659 }
1660 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1661
1662 static bool sdhci_timing_has_preset(unsigned char timing)
1663 {
1664         switch (timing) {
1665         case MMC_TIMING_UHS_SDR12:
1666         case MMC_TIMING_UHS_SDR25:
1667         case MMC_TIMING_UHS_SDR50:
1668         case MMC_TIMING_UHS_SDR104:
1669         case MMC_TIMING_UHS_DDR50:
1670         case MMC_TIMING_MMC_DDR52:
1671                 return true;
1672         };
1673         return false;
1674 }
1675
1676 static bool sdhci_preset_needed(struct sdhci_host *host, unsigned char timing)
1677 {
1678         return !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1679                sdhci_timing_has_preset(timing);
1680 }
1681
1682 static bool sdhci_presetable_values_change(struct sdhci_host *host, struct mmc_ios *ios)
1683 {
1684         /*
1685          * Preset Values are: Driver Strength, Clock Generator and SDCLK/RCLK
1686          * Frequency. Check if preset values need to be enabled, or the Driver
1687          * Strength needs updating. Note, clock changes are handled separately.
1688          */
1689         return !host->preset_enabled &&
1690                (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type);
1691 }
1692
1693 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1694 {
1695         struct sdhci_host *host = mmc_priv(mmc);
1696         bool reinit_uhs = host->reinit_uhs;
1697         bool turning_on_clk = false;
1698         u8 ctrl;
1699
1700         host->reinit_uhs = false;
1701
1702         if (ios->power_mode == MMC_POWER_UNDEFINED)
1703                 return;
1704
1705         if (host->flags & SDHCI_DEVICE_DEAD) {
1706                 if (!IS_ERR(mmc->supply.vmmc) &&
1707                     ios->power_mode == MMC_POWER_OFF)
1708                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1709                 return;
1710         }
1711
1712         /*
1713          * Reset the chip on each power off.
1714          * Should clear out any weird states.
1715          */
1716         if (ios->power_mode == MMC_POWER_OFF) {
1717                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1718                 sdhci_reinit(host);
1719         }
1720
1721         if (host->version >= SDHCI_SPEC_300 &&
1722                 (ios->power_mode == MMC_POWER_UP) &&
1723                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1724                 sdhci_enable_preset_value(host, false);
1725
1726         if (!ios->clock || ios->clock != host->clock) {
1727                 turning_on_clk = ios->clock && !host->clock;
1728
1729                 host->ops->set_clock(host, ios->clock);
1730                 host->clock = ios->clock;
1731
1732                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1733                     host->clock) {
1734                         host->timeout_clk = host->mmc->actual_clock ?
1735                                                 host->mmc->actual_clock / 1000 :
1736                                                 host->clock / 1000;
1737                         host->mmc->max_busy_timeout =
1738                                 host->ops->get_max_timeout_count ?
1739                                 host->ops->get_max_timeout_count(host) :
1740                                 1 << 27;
1741                         host->mmc->max_busy_timeout /= host->timeout_clk;
1742                 }
1743         }
1744
1745         if (host->ops->set_power)
1746                 host->ops->set_power(host, ios->power_mode, ios->vdd);
1747         else
1748                 sdhci_set_power(host, ios->power_mode, ios->vdd);
1749
1750         if (host->ops->platform_send_init_74_clocks)
1751                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1752
1753         host->ops->set_bus_width(host, ios->bus_width);
1754
1755         /*
1756          * Special case to avoid multiple clock changes during voltage
1757          * switching.
1758          */
1759         if (!reinit_uhs &&
1760             turning_on_clk &&
1761             host->timing == ios->timing &&
1762             host->version >= SDHCI_SPEC_300 &&
1763             !sdhci_presetable_values_change(host, ios))
1764                 return;
1765
1766         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1767
1768         if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
1769                 if (ios->timing == MMC_TIMING_SD_HS ||
1770                      ios->timing == MMC_TIMING_MMC_HS ||
1771                      ios->timing == MMC_TIMING_MMC_HS400 ||
1772                      ios->timing == MMC_TIMING_MMC_HS200 ||
1773                      ios->timing == MMC_TIMING_MMC_DDR52 ||
1774                      ios->timing == MMC_TIMING_UHS_SDR50 ||
1775                      ios->timing == MMC_TIMING_UHS_SDR104 ||
1776                      ios->timing == MMC_TIMING_UHS_DDR50 ||
1777                      ios->timing == MMC_TIMING_UHS_SDR25)
1778                         ctrl |= SDHCI_CTRL_HISPD;
1779                 else
1780                         ctrl &= ~SDHCI_CTRL_HISPD;
1781         }
1782
1783         if (host->version >= SDHCI_SPEC_300) {
1784                 u16 clk, ctrl_2;
1785
1786                 if (!host->preset_enabled) {
1787                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1788                         /*
1789                          * We only need to set Driver Strength if the
1790                          * preset value enable is not set.
1791                          */
1792                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1793                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1794                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1795                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1796                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1797                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1798                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1799                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1800                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1801                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1802                         else {
1803                                 pr_warn("%s: invalid driver type, default to driver type B\n",
1804                                         mmc_hostname(mmc));
1805                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1806                         }
1807
1808                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1809                         host->drv_type = ios->drv_type;
1810                 } else {
1811                         /*
1812                          * According to SDHC Spec v3.00, if the Preset Value
1813                          * Enable in the Host Control 2 register is set, we
1814                          * need to reset SD Clock Enable before changing High
1815                          * Speed Enable to avoid generating clock gliches.
1816                          */
1817
1818                         /* Reset SD Clock Enable */
1819                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1820                         clk &= ~SDHCI_CLOCK_CARD_EN;
1821                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1822
1823                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1824
1825                         /* Re-enable SD Clock */
1826                         host->ops->set_clock(host, host->clock);
1827                 }
1828
1829                 /* Reset SD Clock Enable */
1830                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1831                 clk &= ~SDHCI_CLOCK_CARD_EN;
1832                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1833
1834                 host->ops->set_uhs_signaling(host, ios->timing);
1835                 host->timing = ios->timing;
1836
1837                 if (sdhci_preset_needed(host, ios->timing)) {
1838                         u16 preset;
1839
1840                         sdhci_enable_preset_value(host, true);
1841                         preset = sdhci_get_preset_value(host);
1842                         ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
1843                                                   preset);
1844                         host->drv_type = ios->drv_type;
1845                 }
1846
1847                 /* Re-enable SD Clock */
1848                 host->ops->set_clock(host, host->clock);
1849         } else
1850                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1851
1852         /*
1853          * Some (ENE) controllers go apeshit on some ios operation,
1854          * signalling timeout and CRC errors even on CMD0. Resetting
1855          * it on each ios seems to solve the problem.
1856          */
1857         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1858                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1859
1860         mmiowb();
1861 }
1862 EXPORT_SYMBOL_GPL(sdhci_set_ios);
1863
1864 static int sdhci_get_cd(struct mmc_host *mmc)
1865 {
1866         struct sdhci_host *host = mmc_priv(mmc);
1867         int gpio_cd = mmc_gpio_get_cd(mmc);
1868
1869         if (host->flags & SDHCI_DEVICE_DEAD)
1870                 return 0;
1871
1872         /* If nonremovable, assume that the card is always present. */
1873         if (!mmc_card_is_removable(host->mmc))
1874                 return 1;
1875
1876         /*
1877          * Try slot gpio detect, if defined it take precedence
1878          * over build in controller functionality
1879          */
1880         if (gpio_cd >= 0)
1881                 return !!gpio_cd;
1882
1883         /* If polling, assume that the card is always present. */
1884         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1885                 return 1;
1886
1887         /* Host native card detect */
1888         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1889 }
1890
1891 static int sdhci_check_ro(struct sdhci_host *host)
1892 {
1893         unsigned long flags;
1894         int is_readonly;
1895
1896         spin_lock_irqsave(&host->lock, flags);
1897
1898         if (host->flags & SDHCI_DEVICE_DEAD)
1899                 is_readonly = 0;
1900         else if (host->ops->get_ro)
1901                 is_readonly = host->ops->get_ro(host);
1902         else
1903                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1904                                 & SDHCI_WRITE_PROTECT);
1905
1906         spin_unlock_irqrestore(&host->lock, flags);
1907
1908         /* This quirk needs to be replaced by a callback-function later */
1909         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1910                 !is_readonly : is_readonly;
1911 }
1912
1913 #define SAMPLE_COUNT    5
1914
1915 static int sdhci_get_ro(struct mmc_host *mmc)
1916 {
1917         struct sdhci_host *host = mmc_priv(mmc);
1918         int i, ro_count;
1919
1920         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1921                 return sdhci_check_ro(host);
1922
1923         ro_count = 0;
1924         for (i = 0; i < SAMPLE_COUNT; i++) {
1925                 if (sdhci_check_ro(host)) {
1926                         if (++ro_count > SAMPLE_COUNT / 2)
1927                                 return 1;
1928                 }
1929                 msleep(30);
1930         }
1931         return 0;
1932 }
1933
1934 static void sdhci_hw_reset(struct mmc_host *mmc)
1935 {
1936         struct sdhci_host *host = mmc_priv(mmc);
1937
1938         if (host->ops && host->ops->hw_reset)
1939                 host->ops->hw_reset(host);
1940 }
1941
1942 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1943 {
1944         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1945                 if (enable)
1946                         host->ier |= SDHCI_INT_CARD_INT;
1947                 else
1948                         host->ier &= ~SDHCI_INT_CARD_INT;
1949
1950                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1951                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1952                 mmiowb();
1953         }
1954 }
1955
1956 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1957 {
1958         struct sdhci_host *host = mmc_priv(mmc);
1959         unsigned long flags;
1960
1961         if (enable)
1962                 pm_runtime_get_noresume(host->mmc->parent);
1963
1964         spin_lock_irqsave(&host->lock, flags);
1965         if (enable)
1966                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1967         else
1968                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1969
1970         sdhci_enable_sdio_irq_nolock(host, enable);
1971         spin_unlock_irqrestore(&host->lock, flags);
1972
1973         if (!enable)
1974                 pm_runtime_put_noidle(host->mmc->parent);
1975 }
1976 EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
1977
1978 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1979                                       struct mmc_ios *ios)
1980 {
1981         struct sdhci_host *host = mmc_priv(mmc);
1982         u16 ctrl;
1983         int ret;
1984
1985         /*
1986          * Signal Voltage Switching is only applicable for Host Controllers
1987          * v3.00 and above.
1988          */
1989         if (host->version < SDHCI_SPEC_300)
1990                 return 0;
1991
1992         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1993
1994         switch (ios->signal_voltage) {
1995         case MMC_SIGNAL_VOLTAGE_330:
1996                 if (!(host->flags & SDHCI_SIGNALING_330))
1997                         return -EINVAL;
1998                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1999                 ctrl &= ~SDHCI_CTRL_VDD_180;
2000                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2001
2002                 if (!IS_ERR(mmc->supply.vqmmc)) {
2003                         ret = mmc_regulator_set_vqmmc(mmc, ios);
2004                         if (ret) {
2005                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2006                                         mmc_hostname(mmc));
2007                                 return -EIO;
2008                         }
2009                 }
2010                 /* Wait for 5ms */
2011                 usleep_range(5000, 5500);
2012
2013                 /* 3.3V regulator output should be stable within 5 ms */
2014                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2015                 if (!(ctrl & SDHCI_CTRL_VDD_180))
2016                         return 0;
2017
2018                 pr_warn("%s: 3.3V regulator output did not became stable\n",
2019                         mmc_hostname(mmc));
2020
2021                 return -EAGAIN;
2022         case MMC_SIGNAL_VOLTAGE_180:
2023                 if (!(host->flags & SDHCI_SIGNALING_180))
2024                         return -EINVAL;
2025                 if (!IS_ERR(mmc->supply.vqmmc)) {
2026                         ret = mmc_regulator_set_vqmmc(mmc, ios);
2027                         if (ret) {
2028                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2029                                         mmc_hostname(mmc));
2030                                 return -EIO;
2031                         }
2032                 }
2033
2034                 /*
2035                  * Enable 1.8V Signal Enable in the Host Control2
2036                  * register
2037                  */
2038                 ctrl |= SDHCI_CTRL_VDD_180;
2039                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2040
2041                 /* Some controller need to do more when switching */
2042                 if (host->ops->voltage_switch)
2043                         host->ops->voltage_switch(host);
2044
2045                 /* 1.8V regulator output should be stable within 5 ms */
2046                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2047                 if (ctrl & SDHCI_CTRL_VDD_180)
2048                         return 0;
2049
2050                 pr_warn("%s: 1.8V regulator output did not became stable\n",
2051                         mmc_hostname(mmc));
2052
2053                 return -EAGAIN;
2054         case MMC_SIGNAL_VOLTAGE_120:
2055                 if (!(host->flags & SDHCI_SIGNALING_120))
2056                         return -EINVAL;
2057                 if (!IS_ERR(mmc->supply.vqmmc)) {
2058                         ret = mmc_regulator_set_vqmmc(mmc, ios);
2059                         if (ret) {
2060                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2061                                         mmc_hostname(mmc));
2062                                 return -EIO;
2063                         }
2064                 }
2065                 return 0;
2066         default:
2067                 /* No signal voltage switch required */
2068                 return 0;
2069         }
2070 }
2071 EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2072
2073 static int sdhci_card_busy(struct mmc_host *mmc)
2074 {
2075         struct sdhci_host *host = mmc_priv(mmc);
2076         u32 present_state;
2077
2078         /* Check whether DAT[0] is 0 */
2079         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2080
2081         return !(present_state & SDHCI_DATA_0_LVL_MASK);
2082 }
2083
2084 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2085 {
2086         struct sdhci_host *host = mmc_priv(mmc);
2087         unsigned long flags;
2088
2089         spin_lock_irqsave(&host->lock, flags);
2090         host->flags |= SDHCI_HS400_TUNING;
2091         spin_unlock_irqrestore(&host->lock, flags);
2092
2093         return 0;
2094 }
2095
2096 static void sdhci_start_tuning(struct sdhci_host *host)
2097 {
2098         u16 ctrl;
2099
2100         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2101         ctrl |= SDHCI_CTRL_EXEC_TUNING;
2102         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2103                 ctrl |= SDHCI_CTRL_TUNED_CLK;
2104         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2105
2106         /*
2107          * As per the Host Controller spec v3.00, tuning command
2108          * generates Buffer Read Ready interrupt, so enable that.
2109          *
2110          * Note: The spec clearly says that when tuning sequence
2111          * is being performed, the controller does not generate
2112          * interrupts other than Buffer Read Ready interrupt. But
2113          * to make sure we don't hit a controller bug, we _only_
2114          * enable Buffer Read Ready interrupt here.
2115          */
2116         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2117         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2118 }
2119
2120 static void sdhci_end_tuning(struct sdhci_host *host)
2121 {
2122         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2123         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2124 }
2125
2126 static void sdhci_reset_tuning(struct sdhci_host *host)
2127 {
2128         u16 ctrl;
2129
2130         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2131         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2132         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2133         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2134 }
2135
2136 static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2137 {
2138         sdhci_reset_tuning(host);
2139
2140         sdhci_do_reset(host, SDHCI_RESET_CMD);
2141         sdhci_do_reset(host, SDHCI_RESET_DATA);
2142
2143         sdhci_end_tuning(host);
2144
2145         mmc_abort_tuning(host->mmc, opcode);
2146 }
2147
2148 /*
2149  * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2150  * tuning command does not have a data payload (or rather the hardware does it
2151  * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2152  * interrupt setup is different to other commands and there is no timeout
2153  * interrupt so special handling is needed.
2154  */
2155 static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2156 {
2157         struct mmc_host *mmc = host->mmc;
2158         struct mmc_command cmd = {};
2159         struct mmc_request mrq = {};
2160         unsigned long flags;
2161         u32 b = host->sdma_boundary;
2162
2163         spin_lock_irqsave(&host->lock, flags);
2164
2165         cmd.opcode = opcode;
2166         cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2167         cmd.mrq = &mrq;
2168
2169         mrq.cmd = &cmd;
2170         /*
2171          * In response to CMD19, the card sends 64 bytes of tuning
2172          * block to the Host Controller. So we set the block size
2173          * to 64 here.
2174          */
2175         if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2176             mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2177                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2178         else
2179                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2180
2181         /*
2182          * The tuning block is sent by the card to the host controller.
2183          * So we set the TRNS_READ bit in the Transfer Mode register.
2184          * This also takes care of setting DMA Enable and Multi Block
2185          * Select in the same register to 0.
2186          */
2187         sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2188
2189         sdhci_send_command(host, &cmd);
2190
2191         host->cmd = NULL;
2192
2193         sdhci_del_timer(host, &mrq);
2194
2195         host->tuning_done = 0;
2196
2197         mmiowb();
2198         spin_unlock_irqrestore(&host->lock, flags);
2199
2200         /* Wait for Buffer Read Ready interrupt */
2201         wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2202                            msecs_to_jiffies(50));
2203
2204 }
2205
2206 static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2207 {
2208         int i;
2209
2210         /*
2211          * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2212          * of loops reaches 40 times.
2213          */
2214         for (i = 0; i < MAX_TUNING_LOOP; i++) {
2215                 u16 ctrl;
2216
2217                 sdhci_send_tuning(host, opcode);
2218
2219                 if (!host->tuning_done) {
2220                         pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2221                                  mmc_hostname(host->mmc));
2222                         sdhci_abort_tuning(host, opcode);
2223                         return;
2224                 }
2225
2226                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2227                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2228                         if (ctrl & SDHCI_CTRL_TUNED_CLK)
2229                                 return; /* Success! */
2230                         break;
2231                 }
2232
2233                 /* Spec does not require a delay between tuning cycles */
2234                 if (host->tuning_delay > 0)
2235                         mdelay(host->tuning_delay);
2236         }
2237
2238         pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2239                 mmc_hostname(host->mmc));
2240         sdhci_reset_tuning(host);
2241 }
2242
2243 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2244 {
2245         struct sdhci_host *host = mmc_priv(mmc);
2246         int err = 0;
2247         unsigned int tuning_count = 0;
2248         bool hs400_tuning;
2249
2250         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2251
2252         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2253                 tuning_count = host->tuning_count;
2254
2255         /*
2256          * The Host Controller needs tuning in case of SDR104 and DDR50
2257          * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2258          * the Capabilities register.
2259          * If the Host Controller supports the HS200 mode then the
2260          * tuning function has to be executed.
2261          */
2262         switch (host->timing) {
2263         /* HS400 tuning is done in HS200 mode */
2264         case MMC_TIMING_MMC_HS400:
2265                 err = -EINVAL;
2266                 goto out;
2267
2268         case MMC_TIMING_MMC_HS200:
2269                 /*
2270                  * Periodic re-tuning for HS400 is not expected to be needed, so
2271                  * disable it here.
2272                  */
2273                 if (hs400_tuning)
2274                         tuning_count = 0;
2275                 break;
2276
2277         case MMC_TIMING_UHS_SDR104:
2278         case MMC_TIMING_UHS_DDR50:
2279                 break;
2280
2281         case MMC_TIMING_UHS_SDR50:
2282                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2283                         break;
2284                 /* FALLTHROUGH */
2285
2286         default:
2287                 goto out;
2288         }
2289
2290         if (host->ops->platform_execute_tuning) {
2291                 err = host->ops->platform_execute_tuning(host, opcode);
2292                 goto out;
2293         }
2294
2295         host->mmc->retune_period = tuning_count;
2296
2297         if (host->tuning_delay < 0)
2298                 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2299
2300         sdhci_start_tuning(host);
2301
2302         __sdhci_execute_tuning(host, opcode);
2303
2304         sdhci_end_tuning(host);
2305 out:
2306         host->flags &= ~SDHCI_HS400_TUNING;
2307
2308         return err;
2309 }
2310 EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2311
2312 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2313 {
2314         /* Host Controller v3.00 defines preset value registers */
2315         if (host->version < SDHCI_SPEC_300)
2316                 return;
2317
2318         /*
2319          * We only enable or disable Preset Value if they are not already
2320          * enabled or disabled respectively. Otherwise, we bail out.
2321          */
2322         if (host->preset_enabled != enable) {
2323                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2324
2325                 if (enable)
2326                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2327                 else
2328                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2329
2330                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2331
2332                 if (enable)
2333                         host->flags |= SDHCI_PV_ENABLED;
2334                 else
2335                         host->flags &= ~SDHCI_PV_ENABLED;
2336
2337                 host->preset_enabled = enable;
2338         }
2339 }
2340
2341 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2342                                 int err)
2343 {
2344         struct sdhci_host *host = mmc_priv(mmc);
2345         struct mmc_data *data = mrq->data;
2346
2347         if (data->host_cookie != COOKIE_UNMAPPED)
2348                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2349                              mmc_get_dma_dir(data));
2350
2351         data->host_cookie = COOKIE_UNMAPPED;
2352 }
2353
2354 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2355 {
2356         struct sdhci_host *host = mmc_priv(mmc);
2357
2358         mrq->data->host_cookie = COOKIE_UNMAPPED;
2359
2360         /*
2361          * No pre-mapping in the pre hook if we're using the bounce buffer,
2362          * for that we would need two bounce buffers since one buffer is
2363          * in flight when this is getting called.
2364          */
2365         if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2366                 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2367 }
2368
2369 static inline bool sdhci_has_requests(struct sdhci_host *host)
2370 {
2371         return host->cmd || host->data_cmd;
2372 }
2373
2374 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2375 {
2376         if (host->data_cmd) {
2377                 host->data_cmd->error = err;
2378                 sdhci_finish_mrq(host, host->data_cmd->mrq);
2379         }
2380
2381         if (host->cmd) {
2382                 host->cmd->error = err;
2383                 sdhci_finish_mrq(host, host->cmd->mrq);
2384         }
2385 }
2386
2387 static void sdhci_card_event(struct mmc_host *mmc)
2388 {
2389         struct sdhci_host *host = mmc_priv(mmc);
2390         unsigned long flags;
2391         int present;
2392
2393         /* First check if client has provided their own card event */
2394         if (host->ops->card_event)
2395                 host->ops->card_event(host);
2396
2397         present = mmc->ops->get_cd(mmc);
2398
2399         spin_lock_irqsave(&host->lock, flags);
2400
2401         /* Check sdhci_has_requests() first in case we are runtime suspended */
2402         if (sdhci_has_requests(host) && !present) {
2403                 pr_err("%s: Card removed during transfer!\n",
2404                         mmc_hostname(host->mmc));
2405                 pr_err("%s: Resetting controller.\n",
2406                         mmc_hostname(host->mmc));
2407
2408                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2409                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2410
2411                 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2412         }
2413
2414         spin_unlock_irqrestore(&host->lock, flags);
2415 }
2416
2417 static const struct mmc_host_ops sdhci_ops = {
2418         .request        = sdhci_request,
2419         .post_req       = sdhci_post_req,
2420         .pre_req        = sdhci_pre_req,
2421         .set_ios        = sdhci_set_ios,
2422         .get_cd         = sdhci_get_cd,
2423         .get_ro         = sdhci_get_ro,
2424         .hw_reset       = sdhci_hw_reset,
2425         .enable_sdio_irq = sdhci_enable_sdio_irq,
2426         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2427         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2428         .execute_tuning                 = sdhci_execute_tuning,
2429         .card_event                     = sdhci_card_event,
2430         .card_busy      = sdhci_card_busy,
2431 };
2432
2433 /*****************************************************************************\
2434  *                                                                           *
2435  * Tasklets                                                                  *
2436  *                                                                           *
2437 \*****************************************************************************/
2438
2439 static bool sdhci_request_done(struct sdhci_host *host)
2440 {
2441         unsigned long flags;
2442         struct mmc_request *mrq;
2443         int i;
2444
2445         spin_lock_irqsave(&host->lock, flags);
2446
2447         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2448                 mrq = host->mrqs_done[i];
2449                 if (mrq)
2450                         break;
2451         }
2452
2453         if (!mrq) {
2454                 spin_unlock_irqrestore(&host->lock, flags);
2455                 return true;
2456         }
2457
2458         sdhci_del_timer(host, mrq);
2459
2460         /*
2461          * Always unmap the data buffers if they were mapped by
2462          * sdhci_prepare_data() whenever we finish with a request.
2463          * This avoids leaking DMA mappings on error.
2464          */
2465         if (host->flags & SDHCI_REQ_USE_DMA) {
2466                 struct mmc_data *data = mrq->data;
2467
2468                 if (data && data->host_cookie == COOKIE_MAPPED) {
2469                         if (host->bounce_buffer) {
2470                                 /*
2471                                  * On reads, copy the bounced data into the
2472                                  * sglist
2473                                  */
2474                                 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
2475                                         unsigned int length = data->bytes_xfered;
2476
2477                                         if (length > host->bounce_buffer_size) {
2478                                                 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
2479                                                        mmc_hostname(host->mmc),
2480                                                        host->bounce_buffer_size,
2481                                                        data->bytes_xfered);
2482                                                 /* Cap it down and continue */
2483                                                 length = host->bounce_buffer_size;
2484                                         }
2485                                         dma_sync_single_for_cpu(
2486                                                 host->mmc->parent,
2487                                                 host->bounce_addr,
2488                                                 host->bounce_buffer_size,
2489                                                 DMA_FROM_DEVICE);
2490                                         sg_copy_from_buffer(data->sg,
2491                                                 data->sg_len,
2492                                                 host->bounce_buffer,
2493                                                 length);
2494                                 } else {
2495                                         /* No copying, just switch ownership */
2496                                         dma_sync_single_for_cpu(
2497                                                 host->mmc->parent,
2498                                                 host->bounce_addr,
2499                                                 host->bounce_buffer_size,
2500                                                 mmc_get_dma_dir(data));
2501                                 }
2502                         } else {
2503                                 /* Unmap the raw data */
2504                                 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
2505                                              data->sg_len,
2506                                              mmc_get_dma_dir(data));
2507                         }
2508                         data->host_cookie = COOKIE_UNMAPPED;
2509                 }
2510         }
2511
2512         /*
2513          * The controller needs a reset of internal state machines
2514          * upon error conditions.
2515          */
2516         if (sdhci_needs_reset(host, mrq)) {
2517                 /*
2518                  * Do not finish until command and data lines are available for
2519                  * reset. Note there can only be one other mrq, so it cannot
2520                  * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2521                  * would both be null.
2522                  */
2523                 if (host->cmd || host->data_cmd) {
2524                         spin_unlock_irqrestore(&host->lock, flags);
2525                         return true;
2526                 }
2527
2528                 /* Some controllers need this kick or reset won't work here */
2529                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2530                         /* This is to force an update */
2531                         host->ops->set_clock(host, host->clock);
2532
2533                 /* Spec says we should do both at the same time, but Ricoh
2534                    controllers do not like that. */
2535                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2536                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2537
2538                 host->pending_reset = false;
2539         }
2540
2541         if (!sdhci_has_requests(host))
2542                 sdhci_led_deactivate(host);
2543
2544         host->mrqs_done[i] = NULL;
2545
2546         mmiowb();
2547         spin_unlock_irqrestore(&host->lock, flags);
2548
2549         mmc_request_done(host->mmc, mrq);
2550
2551         return false;
2552 }
2553
2554 static void sdhci_tasklet_finish(unsigned long param)
2555 {
2556         struct sdhci_host *host = (struct sdhci_host *)param;
2557
2558         while (!sdhci_request_done(host))
2559                 ;
2560 }
2561
2562 static void sdhci_timeout_timer(unsigned long data)
2563 {
2564         struct sdhci_host *host;
2565         unsigned long flags;
2566
2567         host = (struct sdhci_host*)data;
2568
2569         spin_lock_irqsave(&host->lock, flags);
2570
2571         if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2572                 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2573                        mmc_hostname(host->mmc));
2574                 sdhci_dumpregs(host);
2575
2576                 host->cmd->error = -ETIMEDOUT;
2577                 sdhci_finish_mrq(host, host->cmd->mrq);
2578         }
2579
2580         mmiowb();
2581         spin_unlock_irqrestore(&host->lock, flags);
2582 }
2583
2584 static void sdhci_timeout_data_timer(unsigned long data)
2585 {
2586         struct sdhci_host *host;
2587         unsigned long flags;
2588
2589         host = (struct sdhci_host *)data;
2590
2591         spin_lock_irqsave(&host->lock, flags);
2592
2593         if (host->data || host->data_cmd ||
2594             (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2595                 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2596                        mmc_hostname(host->mmc));
2597                 sdhci_dumpregs(host);
2598
2599                 if (host->data) {
2600                         host->data->error = -ETIMEDOUT;
2601                         sdhci_finish_data(host);
2602                 } else if (host->data_cmd) {
2603                         host->data_cmd->error = -ETIMEDOUT;
2604                         sdhci_finish_mrq(host, host->data_cmd->mrq);
2605                 } else {
2606                         host->cmd->error = -ETIMEDOUT;
2607                         sdhci_finish_mrq(host, host->cmd->mrq);
2608                 }
2609         }
2610
2611         mmiowb();
2612         spin_unlock_irqrestore(&host->lock, flags);
2613 }
2614
2615 /*****************************************************************************\
2616  *                                                                           *
2617  * Interrupt handling                                                        *
2618  *                                                                           *
2619 \*****************************************************************************/
2620
2621 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
2622 {
2623         /* Handle auto-CMD12 error */
2624         if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
2625                 struct mmc_request *mrq = host->data_cmd->mrq;
2626                 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
2627                 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
2628                                    SDHCI_INT_DATA_TIMEOUT :
2629                                    SDHCI_INT_DATA_CRC;
2630
2631                 /* Treat auto-CMD12 error the same as data error */
2632                 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
2633                         *intmask_p |= data_err_bit;
2634                         return;
2635                 }
2636         }
2637
2638         if (!host->cmd) {
2639                 /*
2640                  * SDHCI recovers from errors by resetting the cmd and data
2641                  * circuits.  Until that is done, there very well might be more
2642                  * interrupts, so ignore them in that case.
2643                  */
2644                 if (host->pending_reset)
2645                         return;
2646                 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2647                        mmc_hostname(host->mmc), (unsigned)intmask);
2648                 sdhci_dumpregs(host);
2649                 return;
2650         }
2651
2652         if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2653                        SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2654                 if (intmask & SDHCI_INT_TIMEOUT)
2655                         host->cmd->error = -ETIMEDOUT;
2656                 else
2657                         host->cmd->error = -EILSEQ;
2658
2659                 /* Treat data command CRC error the same as data CRC error */
2660                 if (host->cmd->data &&
2661                     (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2662                      SDHCI_INT_CRC) {
2663                         host->cmd = NULL;
2664                         *intmask_p |= SDHCI_INT_DATA_CRC;
2665                         return;
2666                 }
2667
2668                 sdhci_finish_mrq(host, host->cmd->mrq);
2669                 return;
2670         }
2671
2672         /* Handle auto-CMD23 error */
2673         if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
2674                 struct mmc_request *mrq = host->cmd->mrq;
2675                 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
2676                 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
2677                           -ETIMEDOUT :
2678                           -EILSEQ;
2679
2680                 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
2681                         mrq->sbc->error = err;
2682                         sdhci_finish_mrq(host, mrq);
2683                         return;
2684                 }
2685         }
2686
2687         if (intmask & SDHCI_INT_RESPONSE)
2688                 sdhci_finish_command(host);
2689 }
2690
2691 static void sdhci_adma_show_error(struct sdhci_host *host)
2692 {
2693         void *desc = host->adma_table;
2694         dma_addr_t dma = host->adma_addr;
2695
2696         sdhci_dumpregs(host);
2697
2698         while (true) {
2699                 struct sdhci_adma2_64_desc *dma_desc = desc;
2700
2701                 if (host->flags & SDHCI_USE_64_BIT_DMA)
2702                         SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2703                             (unsigned long long)dma,
2704                             le32_to_cpu(dma_desc->addr_hi),
2705                             le32_to_cpu(dma_desc->addr_lo),
2706                             le16_to_cpu(dma_desc->len),
2707                             le16_to_cpu(dma_desc->cmd));
2708                 else
2709                         SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2710                             (unsigned long long)dma,
2711                             le32_to_cpu(dma_desc->addr_lo),
2712                             le16_to_cpu(dma_desc->len),
2713                             le16_to_cpu(dma_desc->cmd));
2714
2715                 desc += host->desc_sz;
2716                 dma += host->desc_sz;
2717
2718                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2719                         break;
2720         }
2721 }
2722
2723 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2724 {
2725         u32 command;
2726
2727         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2728         if (intmask & SDHCI_INT_DATA_AVAIL) {
2729                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2730                 if (command == MMC_SEND_TUNING_BLOCK ||
2731                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2732                         host->tuning_done = 1;
2733                         wake_up(&host->buf_ready_int);
2734                         return;
2735                 }
2736         }
2737
2738         if (!host->data) {
2739                 struct mmc_command *data_cmd = host->data_cmd;
2740
2741                 /*
2742                  * The "data complete" interrupt is also used to
2743                  * indicate that a busy state has ended. See comment
2744                  * above in sdhci_cmd_irq().
2745                  */
2746                 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2747                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2748                                 host->data_cmd = NULL;
2749                                 data_cmd->error = -ETIMEDOUT;
2750                                 sdhci_finish_mrq(host, data_cmd->mrq);
2751                                 return;
2752                         }
2753                         if (intmask & SDHCI_INT_DATA_END) {
2754                                 host->data_cmd = NULL;
2755                                 /*
2756                                  * Some cards handle busy-end interrupt
2757                                  * before the command completed, so make
2758                                  * sure we do things in the proper order.
2759                                  */
2760                                 if (host->cmd == data_cmd)
2761                                         return;
2762
2763                                 sdhci_finish_mrq(host, data_cmd->mrq);
2764                                 return;
2765                         }
2766                 }
2767
2768                 /*
2769                  * SDHCI recovers from errors by resetting the cmd and data
2770                  * circuits. Until that is done, there very well might be more
2771                  * interrupts, so ignore them in that case.
2772                  */
2773                 if (host->pending_reset)
2774                         return;
2775
2776                 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2777                        mmc_hostname(host->mmc), (unsigned)intmask);
2778                 sdhci_dumpregs(host);
2779
2780                 return;
2781         }
2782
2783         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2784                 host->data->error = -ETIMEDOUT;
2785         else if (intmask & SDHCI_INT_DATA_END_BIT)
2786                 host->data->error = -EILSEQ;
2787         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2788                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2789                         != MMC_BUS_TEST_R)
2790                 host->data->error = -EILSEQ;
2791         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2792                 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
2793                        intmask);
2794                 sdhci_adma_show_error(host);
2795                 host->data->error = -EIO;
2796                 if (host->ops->adma_workaround)
2797                         host->ops->adma_workaround(host, intmask);
2798         }
2799
2800         if (host->data->error)
2801                 sdhci_finish_data(host);
2802         else {
2803                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2804                         sdhci_transfer_pio(host);
2805
2806                 /*
2807                  * We currently don't do anything fancy with DMA
2808                  * boundaries, but as we can't disable the feature
2809                  * we need to at least restart the transfer.
2810                  *
2811                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2812                  * should return a valid address to continue from, but as
2813                  * some controllers are faulty, don't trust them.
2814                  */
2815                 if (intmask & SDHCI_INT_DMA_END) {
2816                         u32 dmastart, dmanow;
2817
2818                         dmastart = sdhci_sdma_address(host);
2819                         dmanow = dmastart + host->data->bytes_xfered;
2820                         /*
2821                          * Force update to the next DMA block boundary.
2822                          */
2823                         dmanow = (dmanow &
2824                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2825                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2826                         host->data->bytes_xfered = dmanow - dmastart;
2827                         DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
2828                             dmastart, host->data->bytes_xfered, dmanow);
2829                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2830                 }
2831
2832                 if (intmask & SDHCI_INT_DATA_END) {
2833                         if (host->cmd == host->data_cmd) {
2834                                 /*
2835                                  * Data managed to finish before the
2836                                  * command completed. Make sure we do
2837                                  * things in the proper order.
2838                                  */
2839                                 host->data_early = 1;
2840                         } else {
2841                                 sdhci_finish_data(host);
2842                         }
2843                 }
2844         }
2845 }
2846
2847 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2848 {
2849         irqreturn_t result = IRQ_NONE;
2850         struct sdhci_host *host = dev_id;
2851         u32 intmask, mask, unexpected = 0;
2852         int max_loops = 16;
2853
2854         spin_lock(&host->lock);
2855
2856         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2857                 spin_unlock(&host->lock);
2858                 return IRQ_NONE;
2859         }
2860
2861         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2862         if (!intmask || intmask == 0xffffffff) {
2863                 result = IRQ_NONE;
2864                 goto out;
2865         }
2866
2867         do {
2868                 DBG("IRQ status 0x%08x\n", intmask);
2869
2870                 if (host->ops->irq) {
2871                         intmask = host->ops->irq(host, intmask);
2872                         if (!intmask)
2873                                 goto cont;
2874                 }
2875
2876                 /* Clear selected interrupts. */
2877                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2878                                   SDHCI_INT_BUS_POWER);
2879                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2880
2881                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2882                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2883                                       SDHCI_CARD_PRESENT;
2884
2885                         /*
2886                          * There is a observation on i.mx esdhc.  INSERT
2887                          * bit will be immediately set again when it gets
2888                          * cleared, if a card is inserted.  We have to mask
2889                          * the irq to prevent interrupt storm which will
2890                          * freeze the system.  And the REMOVE gets the
2891                          * same situation.
2892                          *
2893                          * More testing are needed here to ensure it works
2894                          * for other platforms though.
2895                          */
2896                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2897                                        SDHCI_INT_CARD_REMOVE);
2898                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2899                                                SDHCI_INT_CARD_INSERT;
2900                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2901                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2902
2903                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2904                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2905
2906                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2907                                                        SDHCI_INT_CARD_REMOVE);
2908                         result = IRQ_WAKE_THREAD;
2909                 }
2910
2911                 if (intmask & SDHCI_INT_CMD_MASK)
2912                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
2913
2914                 if (intmask & SDHCI_INT_DATA_MASK)
2915                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2916
2917                 if (intmask & SDHCI_INT_BUS_POWER)
2918                         pr_err("%s: Card is consuming too much power!\n",
2919                                 mmc_hostname(host->mmc));
2920
2921                 if (intmask & SDHCI_INT_RETUNE)
2922                         mmc_retune_needed(host->mmc);
2923
2924                 if ((intmask & SDHCI_INT_CARD_INT) &&
2925                     (host->ier & SDHCI_INT_CARD_INT)) {
2926                         sdhci_enable_sdio_irq_nolock(host, false);
2927                         host->thread_isr |= SDHCI_INT_CARD_INT;
2928                         result = IRQ_WAKE_THREAD;
2929                 }
2930
2931                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2932                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2933                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2934                              SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2935
2936                 if (intmask) {
2937                         unexpected |= intmask;
2938                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2939                 }
2940 cont:
2941                 if (result == IRQ_NONE)
2942                         result = IRQ_HANDLED;
2943
2944                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2945         } while (intmask && --max_loops);
2946 out:
2947         spin_unlock(&host->lock);
2948
2949         if (unexpected) {
2950                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2951                            mmc_hostname(host->mmc), unexpected);
2952                 sdhci_dumpregs(host);
2953         }
2954
2955         return result;
2956 }
2957
2958 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2959 {
2960         struct sdhci_host *host = dev_id;
2961         unsigned long flags;
2962         u32 isr;
2963
2964         spin_lock_irqsave(&host->lock, flags);
2965         isr = host->thread_isr;
2966         host->thread_isr = 0;
2967         spin_unlock_irqrestore(&host->lock, flags);
2968
2969         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2970                 struct mmc_host *mmc = host->mmc;
2971
2972                 mmc->ops->card_event(mmc);
2973                 mmc_detect_change(mmc, msecs_to_jiffies(200));
2974         }
2975
2976         if (isr & SDHCI_INT_CARD_INT) {
2977                 sdio_run_irqs(host->mmc);
2978
2979                 spin_lock_irqsave(&host->lock, flags);
2980                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2981                         sdhci_enable_sdio_irq_nolock(host, true);
2982                 spin_unlock_irqrestore(&host->lock, flags);
2983         }
2984
2985         return isr ? IRQ_HANDLED : IRQ_NONE;
2986 }
2987
2988 /*****************************************************************************\
2989  *                                                                           *
2990  * Suspend/resume                                                            *
2991  *                                                                           *
2992 \*****************************************************************************/
2993
2994 #ifdef CONFIG_PM
2995 /*
2996  * To enable wakeup events, the corresponding events have to be enabled in
2997  * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2998  * Table' in the SD Host Controller Standard Specification.
2999  * It is useless to restore SDHCI_INT_ENABLE state in
3000  * sdhci_disable_irq_wakeups() since it will be set by
3001  * sdhci_enable_card_detection() or sdhci_init().
3002  */
3003 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
3004 {
3005         u8 val;
3006         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3007                         | SDHCI_WAKE_ON_INT;
3008         u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3009                       SDHCI_INT_CARD_INT;
3010
3011         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3012         val |= mask ;
3013         /* Avoid fake wake up */
3014         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
3015                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
3016                 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
3017         }
3018         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3019         sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3020 }
3021 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
3022
3023 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3024 {
3025         u8 val;
3026         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3027                         | SDHCI_WAKE_ON_INT;
3028
3029         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3030         val &= ~mask;
3031         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3032 }
3033
3034 int sdhci_suspend_host(struct sdhci_host *host)
3035 {
3036         sdhci_disable_card_detection(host);
3037
3038         mmc_retune_timer_stop(host->mmc);
3039
3040         if (!device_may_wakeup(mmc_dev(host->mmc))) {
3041                 host->ier = 0;
3042                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3043                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3044                 free_irq(host->irq, host);
3045         } else {
3046                 sdhci_enable_irq_wakeups(host);
3047                 enable_irq_wake(host->irq);
3048         }
3049         return 0;
3050 }
3051
3052 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3053
3054 int sdhci_resume_host(struct sdhci_host *host)
3055 {
3056         struct mmc_host *mmc = host->mmc;
3057         int ret = 0;
3058
3059         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3060                 if (host->ops->enable_dma)
3061                         host->ops->enable_dma(host);
3062         }
3063
3064         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3065             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3066                 /* Card keeps power but host controller does not */
3067                 sdhci_init(host, 0);
3068                 host->pwr = 0;
3069                 host->clock = 0;
3070                 host->reinit_uhs = true;
3071                 mmc->ops->set_ios(mmc, &mmc->ios);
3072         } else {
3073                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3074                 mmiowb();
3075         }
3076
3077         if (!device_may_wakeup(mmc_dev(host->mmc))) {
3078                 ret = request_threaded_irq(host->irq, sdhci_irq,
3079                                            sdhci_thread_irq, IRQF_SHARED,
3080                                            mmc_hostname(host->mmc), host);
3081                 if (ret)
3082                         return ret;
3083         } else {
3084                 sdhci_disable_irq_wakeups(host);
3085                 disable_irq_wake(host->irq);
3086         }
3087
3088         sdhci_enable_card_detection(host);
3089
3090         return ret;
3091 }
3092
3093 EXPORT_SYMBOL_GPL(sdhci_resume_host);
3094
3095 int sdhci_runtime_suspend_host(struct sdhci_host *host)
3096 {
3097         unsigned long flags;
3098
3099         mmc_retune_timer_stop(host->mmc);
3100
3101         spin_lock_irqsave(&host->lock, flags);
3102         host->ier &= SDHCI_INT_CARD_INT;
3103         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3104         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3105         spin_unlock_irqrestore(&host->lock, flags);
3106
3107         synchronize_hardirq(host->irq);
3108
3109         spin_lock_irqsave(&host->lock, flags);
3110         host->runtime_suspended = true;
3111         spin_unlock_irqrestore(&host->lock, flags);
3112
3113         return 0;
3114 }
3115 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3116
3117 int sdhci_runtime_resume_host(struct sdhci_host *host)
3118 {
3119         struct mmc_host *mmc = host->mmc;
3120         unsigned long flags;
3121         int host_flags = host->flags;
3122
3123         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3124                 if (host->ops->enable_dma)
3125                         host->ops->enable_dma(host);
3126         }
3127
3128         sdhci_init(host, 0);
3129
3130         if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3131             mmc->ios.power_mode != MMC_POWER_OFF) {
3132                 /* Force clock and power re-program */
3133                 host->pwr = 0;
3134                 host->clock = 0;
3135                 host->reinit_uhs = true;
3136                 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3137                 mmc->ops->set_ios(mmc, &mmc->ios);
3138
3139                 if ((host_flags & SDHCI_PV_ENABLED) &&
3140                     !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3141                         spin_lock_irqsave(&host->lock, flags);
3142                         sdhci_enable_preset_value(host, true);
3143                         spin_unlock_irqrestore(&host->lock, flags);
3144                 }
3145
3146                 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3147                     mmc->ops->hs400_enhanced_strobe)
3148                         mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3149         }
3150
3151         spin_lock_irqsave(&host->lock, flags);
3152
3153         host->runtime_suspended = false;
3154
3155         /* Enable SDIO IRQ */
3156         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
3157                 sdhci_enable_sdio_irq_nolock(host, true);
3158
3159         /* Enable Card Detection */
3160         sdhci_enable_card_detection(host);
3161
3162         spin_unlock_irqrestore(&host->lock, flags);
3163
3164         return 0;
3165 }
3166 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3167
3168 #endif /* CONFIG_PM */
3169
3170 /*****************************************************************************\
3171  *                                                                           *
3172  * Command Queue Engine (CQE) helpers                                        *
3173  *                                                                           *
3174 \*****************************************************************************/
3175
3176 void sdhci_cqe_enable(struct mmc_host *mmc)
3177 {
3178         struct sdhci_host *host = mmc_priv(mmc);
3179         unsigned long flags;
3180         u8 ctrl;
3181
3182         spin_lock_irqsave(&host->lock, flags);
3183
3184         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3185         ctrl &= ~SDHCI_CTRL_DMA_MASK;
3186         if (host->flags & SDHCI_USE_64_BIT_DMA)
3187                 ctrl |= SDHCI_CTRL_ADMA64;
3188         else
3189                 ctrl |= SDHCI_CTRL_ADMA32;
3190         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3191
3192         sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3193                      SDHCI_BLOCK_SIZE);
3194
3195         /* Set maximum timeout */
3196         sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
3197
3198         host->ier = host->cqe_ier;
3199
3200         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3201         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3202
3203         host->cqe_on = true;
3204
3205         pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3206                  mmc_hostname(mmc), host->ier,
3207                  sdhci_readl(host, SDHCI_INT_STATUS));
3208
3209         mmiowb();
3210         spin_unlock_irqrestore(&host->lock, flags);
3211 }
3212 EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3213
3214 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3215 {
3216         struct sdhci_host *host = mmc_priv(mmc);
3217         unsigned long flags;
3218
3219         spin_lock_irqsave(&host->lock, flags);
3220
3221         sdhci_set_default_irqs(host);
3222
3223         host->cqe_on = false;
3224
3225         if (recovery) {
3226                 sdhci_do_reset(host, SDHCI_RESET_CMD);
3227                 sdhci_do_reset(host, SDHCI_RESET_DATA);
3228         }
3229
3230         pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3231                  mmc_hostname(mmc), host->ier,
3232                  sdhci_readl(host, SDHCI_INT_STATUS));
3233
3234         mmiowb();
3235         spin_unlock_irqrestore(&host->lock, flags);
3236 }
3237 EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3238
3239 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3240                    int *data_error)
3241 {
3242         u32 mask;
3243
3244         if (!host->cqe_on)
3245                 return false;
3246
3247         if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3248                 *cmd_error = -EILSEQ;
3249         else if (intmask & SDHCI_INT_TIMEOUT)
3250                 *cmd_error = -ETIMEDOUT;
3251         else
3252                 *cmd_error = 0;
3253
3254         if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3255                 *data_error = -EILSEQ;
3256         else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3257                 *data_error = -ETIMEDOUT;
3258         else if (intmask & SDHCI_INT_ADMA_ERROR)
3259                 *data_error = -EIO;
3260         else
3261                 *data_error = 0;
3262
3263         /* Clear selected interrupts. */
3264         mask = intmask & host->cqe_ier;
3265         sdhci_writel(host, mask, SDHCI_INT_STATUS);
3266
3267         if (intmask & SDHCI_INT_BUS_POWER)
3268                 pr_err("%s: Card is consuming too much power!\n",
3269                        mmc_hostname(host->mmc));
3270
3271         intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3272         if (intmask) {
3273                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3274                 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3275                        mmc_hostname(host->mmc), intmask);
3276                 sdhci_dumpregs(host);
3277         }
3278
3279         return true;
3280 }
3281 EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3282
3283 /*****************************************************************************\
3284  *                                                                           *
3285  * Device allocation/registration                                            *
3286  *                                                                           *
3287 \*****************************************************************************/
3288
3289 struct sdhci_host *sdhci_alloc_host(struct device *dev,
3290         size_t priv_size)
3291 {
3292         struct mmc_host *mmc;
3293         struct sdhci_host *host;
3294
3295         WARN_ON(dev == NULL);
3296
3297         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3298         if (!mmc)
3299                 return ERR_PTR(-ENOMEM);
3300
3301         host = mmc_priv(mmc);
3302         host->mmc = mmc;
3303         host->mmc_host_ops = sdhci_ops;
3304         mmc->ops = &host->mmc_host_ops;
3305
3306         host->flags = SDHCI_SIGNALING_330;
3307
3308         host->cqe_ier     = SDHCI_CQE_INT_MASK;
3309         host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3310
3311         host->tuning_delay = -1;
3312
3313         host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3314
3315         return host;
3316 }
3317
3318 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3319
3320 static int sdhci_set_dma_mask(struct sdhci_host *host)
3321 {
3322         struct mmc_host *mmc = host->mmc;
3323         struct device *dev = mmc_dev(mmc);
3324         int ret = -EINVAL;
3325
3326         if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3327                 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3328
3329         /* Try 64-bit mask if hardware is capable  of it */
3330         if (host->flags & SDHCI_USE_64_BIT_DMA) {
3331                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3332                 if (ret) {
3333                         pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3334                                 mmc_hostname(mmc));
3335                         host->flags &= ~SDHCI_USE_64_BIT_DMA;
3336                 }
3337         }
3338
3339         /* 32-bit mask as default & fallback */
3340         if (ret) {
3341                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3342                 if (ret)
3343                         pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3344                                 mmc_hostname(mmc));
3345         }
3346
3347         return ret;
3348 }
3349
3350 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3351 {
3352         u16 v;
3353         u64 dt_caps_mask = 0;
3354         u64 dt_caps = 0;
3355
3356         if (host->read_caps)
3357                 return;
3358
3359         host->read_caps = true;
3360
3361         if (debug_quirks)
3362                 host->quirks = debug_quirks;
3363
3364         if (debug_quirks2)
3365                 host->quirks2 = debug_quirks2;
3366
3367         sdhci_do_reset(host, SDHCI_RESET_ALL);
3368
3369         of_property_read_u64(mmc_dev(host->mmc)->of_node,
3370                              "sdhci-caps-mask", &dt_caps_mask);
3371         of_property_read_u64(mmc_dev(host->mmc)->of_node,
3372                              "sdhci-caps", &dt_caps);
3373
3374         v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3375         host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3376
3377         if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3378                 return;
3379
3380         if (caps) {
3381                 host->caps = *caps;
3382         } else {
3383                 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3384                 host->caps &= ~lower_32_bits(dt_caps_mask);
3385                 host->caps |= lower_32_bits(dt_caps);
3386         }
3387
3388         if (host->version < SDHCI_SPEC_300)
3389                 return;
3390
3391         if (caps1) {
3392                 host->caps1 = *caps1;
3393         } else {
3394                 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3395                 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3396                 host->caps1 |= upper_32_bits(dt_caps);
3397         }
3398 }
3399 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3400
3401 static int sdhci_allocate_bounce_buffer(struct sdhci_host *host)
3402 {
3403         struct mmc_host *mmc = host->mmc;
3404         unsigned int max_blocks;
3405         unsigned int bounce_size;
3406         int ret;
3407
3408         /*
3409          * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
3410          * has diminishing returns, this is probably because SD/MMC
3411          * cards are usually optimized to handle this size of requests.
3412          */
3413         bounce_size = SZ_64K;
3414         /*
3415          * Adjust downwards to maximum request size if this is less
3416          * than our segment size, else hammer down the maximum
3417          * request size to the maximum buffer size.
3418          */
3419         if (mmc->max_req_size < bounce_size)
3420                 bounce_size = mmc->max_req_size;
3421         max_blocks = bounce_size / 512;
3422
3423         /*
3424          * When we just support one segment, we can get significant
3425          * speedups by the help of a bounce buffer to group scattered
3426          * reads/writes together.
3427          */
3428         host->bounce_buffer = devm_kmalloc(mmc->parent,
3429                                            bounce_size,
3430                                            GFP_KERNEL);
3431         if (!host->bounce_buffer) {
3432                 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
3433                        mmc_hostname(mmc),
3434                        bounce_size);
3435                 /*
3436                  * Exiting with zero here makes sure we proceed with
3437                  * mmc->max_segs == 1.
3438                  */
3439                 return 0;
3440         }
3441
3442         host->bounce_addr = dma_map_single(mmc->parent,
3443                                            host->bounce_buffer,
3444                                            bounce_size,
3445                                            DMA_BIDIRECTIONAL);
3446         ret = dma_mapping_error(mmc->parent, host->bounce_addr);
3447         if (ret)
3448                 /* Again fall back to max_segs == 1 */
3449                 return 0;
3450         host->bounce_buffer_size = bounce_size;
3451
3452         /* Lie about this since we're bouncing */
3453         mmc->max_segs = max_blocks;
3454         mmc->max_seg_size = bounce_size;
3455         mmc->max_req_size = bounce_size;
3456
3457         pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
3458                 mmc_hostname(mmc), max_blocks, bounce_size);
3459
3460         return 0;
3461 }
3462
3463 int sdhci_setup_host(struct sdhci_host *host)
3464 {
3465         struct mmc_host *mmc;
3466         u32 max_current_caps;
3467         unsigned int ocr_avail;
3468         unsigned int override_timeout_clk;
3469         u32 max_clk;
3470         int ret;
3471
3472         WARN_ON(host == NULL);
3473         if (host == NULL)
3474                 return -EINVAL;
3475
3476         mmc = host->mmc;
3477
3478         /*
3479          * If there are external regulators, get them. Note this must be done
3480          * early before resetting the host and reading the capabilities so that
3481          * the host can take the appropriate action if regulators are not
3482          * available.
3483          */
3484         ret = mmc_regulator_get_supply(mmc);
3485         if (ret == -EPROBE_DEFER)
3486                 return ret;
3487
3488         DBG("Version:   0x%08x | Present:  0x%08x\n",
3489             sdhci_readw(host, SDHCI_HOST_VERSION),
3490             sdhci_readl(host, SDHCI_PRESENT_STATE));
3491         DBG("Caps:      0x%08x | Caps_1:   0x%08x\n",
3492             sdhci_readl(host, SDHCI_CAPABILITIES),
3493             sdhci_readl(host, SDHCI_CAPABILITIES_1));
3494
3495         sdhci_read_caps(host);
3496
3497         override_timeout_clk = host->timeout_clk;
3498
3499         if (host->version > SDHCI_SPEC_300) {
3500                 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3501                        mmc_hostname(mmc), host->version);
3502         }
3503
3504         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3505                 host->flags |= SDHCI_USE_SDMA;
3506         else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3507                 DBG("Controller doesn't have SDMA capability\n");
3508         else
3509                 host->flags |= SDHCI_USE_SDMA;
3510
3511         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3512                 (host->flags & SDHCI_USE_SDMA)) {
3513                 DBG("Disabling DMA as it is marked broken\n");
3514                 host->flags &= ~SDHCI_USE_SDMA;
3515         }
3516
3517         if ((host->version >= SDHCI_SPEC_200) &&
3518                 (host->caps & SDHCI_CAN_DO_ADMA2))
3519                 host->flags |= SDHCI_USE_ADMA;
3520
3521         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3522                 (host->flags & SDHCI_USE_ADMA)) {
3523                 DBG("Disabling ADMA as it is marked broken\n");
3524                 host->flags &= ~SDHCI_USE_ADMA;
3525         }
3526
3527         /*
3528          * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3529          * and *must* do 64-bit DMA.  A driver has the opportunity to change
3530          * that during the first call to ->enable_dma().  Similarly
3531          * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3532          * implement.
3533          */
3534         if (host->caps & SDHCI_CAN_64BIT)
3535                 host->flags |= SDHCI_USE_64_BIT_DMA;
3536
3537         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3538                 ret = sdhci_set_dma_mask(host);
3539
3540                 if (!ret && host->ops->enable_dma)
3541                         ret = host->ops->enable_dma(host);
3542
3543                 if (ret) {
3544                         pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3545                                 mmc_hostname(mmc));
3546                         host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3547
3548                         ret = 0;
3549                 }
3550         }
3551
3552         /* SDMA does not support 64-bit DMA */
3553         if (host->flags & SDHCI_USE_64_BIT_DMA)
3554                 host->flags &= ~SDHCI_USE_SDMA;
3555
3556         if (host->flags & SDHCI_USE_ADMA) {
3557                 dma_addr_t dma;
3558                 void *buf;
3559
3560                 /*
3561                  * The DMA descriptor table size is calculated as the maximum
3562                  * number of segments times 2, to allow for an alignment
3563                  * descriptor for each segment, plus 1 for a nop end descriptor,
3564                  * all multipled by the descriptor size.
3565                  */
3566                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3567                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3568                                               SDHCI_ADMA2_64_DESC_SZ;
3569                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3570                 } else {
3571                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3572                                               SDHCI_ADMA2_32_DESC_SZ;
3573                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3574                 }
3575
3576                 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3577                 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3578                                          host->adma_table_sz, &dma, GFP_KERNEL);
3579                 if (!buf) {
3580                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3581                                 mmc_hostname(mmc));
3582                         host->flags &= ~SDHCI_USE_ADMA;
3583                 } else if ((dma + host->align_buffer_sz) &
3584                            (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3585                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3586                                 mmc_hostname(mmc));
3587                         host->flags &= ~SDHCI_USE_ADMA;
3588                         dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3589                                           host->adma_table_sz, buf, dma);
3590                 } else {
3591                         host->align_buffer = buf;
3592                         host->align_addr = dma;
3593
3594                         host->adma_table = buf + host->align_buffer_sz;
3595                         host->adma_addr = dma + host->align_buffer_sz;
3596                 }
3597         }
3598
3599         /*
3600          * If we use DMA, then it's up to the caller to set the DMA
3601          * mask, but PIO does not need the hw shim so we set a new
3602          * mask here in that case.
3603          */
3604         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3605                 host->dma_mask = DMA_BIT_MASK(64);
3606                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3607         }
3608
3609         if (host->version >= SDHCI_SPEC_300)
3610                 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3611                         >> SDHCI_CLOCK_BASE_SHIFT;
3612         else
3613                 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3614                         >> SDHCI_CLOCK_BASE_SHIFT;
3615
3616         host->max_clk *= 1000000;
3617         if (host->max_clk == 0 || host->quirks &
3618                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3619                 if (!host->ops->get_max_clock) {
3620                         pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3621                                mmc_hostname(mmc));
3622                         ret = -ENODEV;
3623                         goto undma;
3624                 }
3625                 host->max_clk = host->ops->get_max_clock(host);
3626         }
3627
3628         /*
3629          * In case of Host Controller v3.00, find out whether clock
3630          * multiplier is supported.
3631          */
3632         host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3633                         SDHCI_CLOCK_MUL_SHIFT;
3634
3635         /*
3636          * In case the value in Clock Multiplier is 0, then programmable
3637          * clock mode is not supported, otherwise the actual clock
3638          * multiplier is one more than the value of Clock Multiplier
3639          * in the Capabilities Register.
3640          */
3641         if (host->clk_mul)
3642                 host->clk_mul += 1;
3643
3644         /*
3645          * Set host parameters.
3646          */
3647         max_clk = host->max_clk;
3648
3649         if (host->ops->get_min_clock)
3650                 mmc->f_min = host->ops->get_min_clock(host);
3651         else if (host->version >= SDHCI_SPEC_300) {
3652                 if (host->clk_mul)
3653                         max_clk = host->max_clk * host->clk_mul;
3654                 /*
3655                  * Divided Clock Mode minimum clock rate is always less than
3656                  * Programmable Clock Mode minimum clock rate.
3657                  */
3658                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3659         } else
3660                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3661
3662         if (!mmc->f_max || mmc->f_max > max_clk)
3663                 mmc->f_max = max_clk;
3664
3665         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3666                 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3667                                         SDHCI_TIMEOUT_CLK_SHIFT;
3668
3669                 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3670                         host->timeout_clk *= 1000;
3671
3672                 if (host->timeout_clk == 0) {
3673                         if (!host->ops->get_timeout_clock) {
3674                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3675                                         mmc_hostname(mmc));
3676                                 ret = -ENODEV;
3677                                 goto undma;
3678                         }
3679
3680                         host->timeout_clk =
3681                                 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
3682                                              1000);
3683                 }
3684
3685                 if (override_timeout_clk)
3686                         host->timeout_clk = override_timeout_clk;
3687
3688                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3689                         host->ops->get_max_timeout_count(host) : 1 << 27;
3690                 mmc->max_busy_timeout /= host->timeout_clk;
3691         }
3692
3693         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3694         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3695
3696         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3697                 host->flags |= SDHCI_AUTO_CMD12;
3698
3699         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3700         if ((host->version >= SDHCI_SPEC_300) &&
3701             ((host->flags & SDHCI_USE_ADMA) ||
3702              !(host->flags & SDHCI_USE_SDMA)) &&
3703              !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3704                 host->flags |= SDHCI_AUTO_CMD23;
3705                 DBG("Auto-CMD23 available\n");
3706         } else {
3707                 DBG("Auto-CMD23 unavailable\n");
3708         }
3709
3710         /*
3711          * A controller may support 8-bit width, but the board itself
3712          * might not have the pins brought out.  Boards that support
3713          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3714          * their platform code before calling sdhci_add_host(), and we
3715          * won't assume 8-bit width for hosts without that CAP.
3716          */
3717         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3718                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3719
3720         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3721                 mmc->caps &= ~MMC_CAP_CMD23;
3722
3723         if (host->caps & SDHCI_CAN_DO_HISPD)
3724                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3725
3726         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3727             mmc_card_is_removable(mmc) &&
3728             mmc_gpio_get_cd(host->mmc) < 0)
3729                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3730
3731         if (!IS_ERR(mmc->supply.vqmmc)) {
3732                 ret = regulator_enable(mmc->supply.vqmmc);
3733
3734                 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
3735                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3736                                                     1950000))
3737                         host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3738                                          SDHCI_SUPPORT_SDR50 |
3739                                          SDHCI_SUPPORT_DDR50);
3740
3741                 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
3742                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
3743                                                     3600000))
3744                         host->flags &= ~SDHCI_SIGNALING_330;
3745
3746                 if (ret) {
3747                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3748                                 mmc_hostname(mmc), ret);
3749                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3750                 }
3751         }
3752
3753         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3754                 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3755                                  SDHCI_SUPPORT_DDR50);
3756         }
3757
3758         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3759         if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3760                            SDHCI_SUPPORT_DDR50))
3761                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3762
3763         /* SDR104 supports also implies SDR50 support */
3764         if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3765                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3766                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3767                  * field can be promoted to support HS200.
3768                  */
3769                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3770                         mmc->caps2 |= MMC_CAP2_HS200;
3771         } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3772                 mmc->caps |= MMC_CAP_UHS_SDR50;
3773         }
3774
3775         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3776             (host->caps1 & SDHCI_SUPPORT_HS400))
3777                 mmc->caps2 |= MMC_CAP2_HS400;
3778
3779         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3780             (IS_ERR(mmc->supply.vqmmc) ||
3781              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3782                                              1300000)))
3783                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3784
3785         if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3786             !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3787                 mmc->caps |= MMC_CAP_UHS_DDR50;
3788
3789         /* Does the host need tuning for SDR50? */
3790         if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3791                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3792
3793         /* Driver Type(s) (A, C, D) supported by the host */
3794         if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3795                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3796         if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3797                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3798         if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3799                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3800
3801         /* Initial value for re-tuning timer count */
3802         host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3803                              SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3804
3805         /*
3806          * In case Re-tuning Timer is not disabled, the actual value of
3807          * re-tuning timer will be 2 ^ (n - 1).
3808          */
3809         if (host->tuning_count)
3810                 host->tuning_count = 1 << (host->tuning_count - 1);
3811
3812         /* Re-tuning mode supported by the Host Controller */
3813         host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3814                              SDHCI_RETUNING_MODE_SHIFT;
3815
3816         ocr_avail = 0;
3817
3818         /*
3819          * According to SD Host Controller spec v3.00, if the Host System
3820          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3821          * the value is meaningful only if Voltage Support in the Capabilities
3822          * register is set. The actual current value is 4 times the register
3823          * value.
3824          */
3825         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3826         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3827                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3828                 if (curr > 0) {
3829
3830                         /* convert to SDHCI_MAX_CURRENT format */
3831                         curr = curr/1000;  /* convert to mA */
3832                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3833
3834                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3835                         max_current_caps =
3836                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3837                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3838                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3839                 }
3840         }
3841
3842         if (host->caps & SDHCI_CAN_VDD_330) {
3843                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3844
3845                 mmc->max_current_330 = ((max_current_caps &
3846                                    SDHCI_MAX_CURRENT_330_MASK) >>
3847                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3848                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3849         }
3850         if (host->caps & SDHCI_CAN_VDD_300) {
3851                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3852
3853                 mmc->max_current_300 = ((max_current_caps &
3854                                    SDHCI_MAX_CURRENT_300_MASK) >>
3855                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3856                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3857         }
3858         if (host->caps & SDHCI_CAN_VDD_180) {
3859                 ocr_avail |= MMC_VDD_165_195;
3860
3861                 mmc->max_current_180 = ((max_current_caps &
3862                                    SDHCI_MAX_CURRENT_180_MASK) >>
3863                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3864                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3865         }
3866
3867         /* If OCR set by host, use it instead. */
3868         if (host->ocr_mask)
3869                 ocr_avail = host->ocr_mask;
3870
3871         /* If OCR set by external regulators, give it highest prio. */
3872         if (mmc->ocr_avail)
3873                 ocr_avail = mmc->ocr_avail;
3874
3875         mmc->ocr_avail = ocr_avail;
3876         mmc->ocr_avail_sdio = ocr_avail;
3877         if (host->ocr_avail_sdio)
3878                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3879         mmc->ocr_avail_sd = ocr_avail;
3880         if (host->ocr_avail_sd)
3881                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3882         else /* normal SD controllers don't support 1.8V */
3883                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3884         mmc->ocr_avail_mmc = ocr_avail;
3885         if (host->ocr_avail_mmc)
3886                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3887
3888         if (mmc->ocr_avail == 0) {
3889                 pr_err("%s: Hardware doesn't report any support voltages.\n",
3890                        mmc_hostname(mmc));
3891                 ret = -ENODEV;
3892                 goto unreg;
3893         }
3894
3895         if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3896                           MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3897                           MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3898             (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3899                 host->flags |= SDHCI_SIGNALING_180;
3900
3901         if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3902                 host->flags |= SDHCI_SIGNALING_120;
3903
3904         spin_lock_init(&host->lock);
3905
3906         /*
3907          * Maximum number of sectors in one transfer. Limited by SDMA boundary
3908          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3909          * is less anyway.
3910          */
3911         mmc->max_req_size = 524288;
3912
3913         /*
3914          * Maximum number of segments. Depends on if the hardware
3915          * can do scatter/gather or not.
3916          */
3917         if (host->flags & SDHCI_USE_ADMA) {
3918                 mmc->max_segs = SDHCI_MAX_SEGS;
3919         } else if (host->flags & SDHCI_USE_SDMA) {
3920                 mmc->max_segs = 1;
3921                 if (swiotlb_max_segment()) {
3922                         unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
3923                                                 IO_TLB_SEGSIZE;
3924                         mmc->max_req_size = min(mmc->max_req_size,
3925                                                 max_req_size);
3926                 }
3927         } else { /* PIO */
3928                 mmc->max_segs = SDHCI_MAX_SEGS;
3929         }
3930
3931         /*
3932          * Maximum segment size. Could be one segment with the maximum number
3933          * of bytes. When doing hardware scatter/gather, each entry cannot
3934          * be larger than 64 KiB though.
3935          */
3936         if (host->flags & SDHCI_USE_ADMA) {
3937                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3938                         mmc->max_seg_size = 65535;
3939                 else
3940                         mmc->max_seg_size = 65536;
3941         } else {
3942                 mmc->max_seg_size = mmc->max_req_size;
3943         }
3944
3945         /*
3946          * Maximum block size. This varies from controller to controller and
3947          * is specified in the capabilities register.
3948          */
3949         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3950                 mmc->max_blk_size = 2;
3951         } else {
3952                 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
3953                                 SDHCI_MAX_BLOCK_SHIFT;
3954                 if (mmc->max_blk_size >= 3) {
3955                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3956                                 mmc_hostname(mmc));
3957                         mmc->max_blk_size = 0;
3958                 }
3959         }
3960
3961         mmc->max_blk_size = 512 << mmc->max_blk_size;
3962
3963         /*
3964          * Maximum block count.
3965          */
3966         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3967
3968         if (mmc->max_segs == 1) {
3969                 /* This may alter mmc->*_blk_* parameters */
3970                 ret = sdhci_allocate_bounce_buffer(host);
3971                 if (ret)
3972                         return ret;
3973         }
3974
3975         return 0;
3976
3977 unreg:
3978         if (!IS_ERR(mmc->supply.vqmmc))
3979                 regulator_disable(mmc->supply.vqmmc);
3980 undma:
3981         if (host->align_buffer)
3982                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3983                                   host->adma_table_sz, host->align_buffer,
3984                                   host->align_addr);
3985         host->adma_table = NULL;
3986         host->align_buffer = NULL;
3987
3988         return ret;
3989 }
3990 EXPORT_SYMBOL_GPL(sdhci_setup_host);
3991
3992 void sdhci_cleanup_host(struct sdhci_host *host)
3993 {
3994         struct mmc_host *mmc = host->mmc;
3995
3996         if (!IS_ERR(mmc->supply.vqmmc))
3997                 regulator_disable(mmc->supply.vqmmc);
3998
3999         if (host->align_buffer)
4000                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4001                                   host->adma_table_sz, host->align_buffer,
4002                                   host->align_addr);
4003         host->adma_table = NULL;
4004         host->align_buffer = NULL;
4005 }
4006 EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4007
4008 int __sdhci_add_host(struct sdhci_host *host)
4009 {
4010         struct mmc_host *mmc = host->mmc;
4011         int ret;
4012
4013         /*
4014          * Init tasklets.
4015          */
4016         tasklet_init(&host->finish_tasklet,
4017                 sdhci_tasklet_finish, (unsigned long)host);
4018
4019         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
4020         setup_timer(&host->data_timer, sdhci_timeout_data_timer,
4021                     (unsigned long)host);
4022
4023         init_waitqueue_head(&host->buf_ready_int);
4024
4025         sdhci_init(host, 0);
4026
4027         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4028                                    IRQF_SHARED, mmc_hostname(mmc), host);
4029         if (ret) {
4030                 pr_err("%s: Failed to request IRQ %d: %d\n",
4031                        mmc_hostname(mmc), host->irq, ret);
4032                 goto untasklet;
4033         }
4034
4035         ret = sdhci_led_register(host);
4036         if (ret) {
4037                 pr_err("%s: Failed to register LED device: %d\n",
4038                        mmc_hostname(mmc), ret);
4039                 goto unirq;
4040         }
4041
4042         mmiowb();
4043
4044         ret = mmc_add_host(mmc);
4045         if (ret)
4046                 goto unled;
4047
4048         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4049                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4050                 (host->flags & SDHCI_USE_ADMA) ?
4051                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4052                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4053
4054         sdhci_enable_card_detection(host);
4055
4056         return 0;
4057
4058 unled:
4059         sdhci_led_unregister(host);
4060 unirq:
4061         sdhci_do_reset(host, SDHCI_RESET_ALL);
4062         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4063         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4064         free_irq(host->irq, host);
4065 untasklet:
4066         tasklet_kill(&host->finish_tasklet);
4067
4068         return ret;
4069 }
4070 EXPORT_SYMBOL_GPL(__sdhci_add_host);
4071
4072 int sdhci_add_host(struct sdhci_host *host)
4073 {
4074         int ret;
4075
4076         ret = sdhci_setup_host(host);
4077         if (ret)
4078                 return ret;
4079
4080         ret = __sdhci_add_host(host);
4081         if (ret)
4082                 goto cleanup;
4083
4084         return 0;
4085
4086 cleanup:
4087         sdhci_cleanup_host(host);
4088
4089         return ret;
4090 }
4091 EXPORT_SYMBOL_GPL(sdhci_add_host);
4092
4093 void sdhci_remove_host(struct sdhci_host *host, int dead)
4094 {
4095         struct mmc_host *mmc = host->mmc;
4096         unsigned long flags;
4097
4098         if (dead) {
4099                 spin_lock_irqsave(&host->lock, flags);
4100
4101                 host->flags |= SDHCI_DEVICE_DEAD;
4102
4103                 if (sdhci_has_requests(host)) {
4104                         pr_err("%s: Controller removed during "
4105                                 " transfer!\n", mmc_hostname(mmc));
4106                         sdhci_error_out_mrqs(host, -ENOMEDIUM);
4107                 }
4108
4109                 spin_unlock_irqrestore(&host->lock, flags);
4110         }
4111
4112         sdhci_disable_card_detection(host);
4113
4114         mmc_remove_host(mmc);
4115
4116         sdhci_led_unregister(host);
4117
4118         if (!dead)
4119                 sdhci_do_reset(host, SDHCI_RESET_ALL);
4120
4121         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4122         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4123         free_irq(host->irq, host);
4124
4125         del_timer_sync(&host->timer);
4126         del_timer_sync(&host->data_timer);
4127
4128         tasklet_kill(&host->finish_tasklet);
4129
4130         if (!IS_ERR(mmc->supply.vqmmc))
4131                 regulator_disable(mmc->supply.vqmmc);
4132
4133         if (host->align_buffer)
4134                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4135                                   host->adma_table_sz, host->align_buffer,
4136                                   host->align_addr);
4137
4138         host->adma_table = NULL;
4139         host->align_buffer = NULL;
4140 }
4141
4142 EXPORT_SYMBOL_GPL(sdhci_remove_host);
4143
4144 void sdhci_free_host(struct sdhci_host *host)
4145 {
4146         mmc_free_host(host->mmc);
4147 }
4148
4149 EXPORT_SYMBOL_GPL(sdhci_free_host);
4150
4151 /*****************************************************************************\
4152  *                                                                           *
4153  * Driver init/exit                                                          *
4154  *                                                                           *
4155 \*****************************************************************************/
4156
4157 static int __init sdhci_drv_init(void)
4158 {
4159         pr_info(DRIVER_NAME
4160                 ": Secure Digital Host Controller Interface driver\n");
4161         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4162
4163         return 0;
4164 }
4165
4166 static void __exit sdhci_drv_exit(void)
4167 {
4168 }
4169
4170 module_init(sdhci_drv_init);
4171 module_exit(sdhci_drv_exit);
4172
4173 module_param(debug_quirks, uint, 0444);
4174 module_param(debug_quirks2, uint, 0444);
4175
4176 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4177 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4178 MODULE_LICENSE("GPL");
4179
4180 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4181 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");