2 * Driver for Marvell Xenon SDHC as a platform device
4 * Copyright (C) 2016 Marvell, All Rights Reserved.
6 * Author: Hu Ziji <huziji@marvell.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
13 * Inspired by Jisheng Zhang <jszhang@marvell.com>
14 * Special thanks to Video BG4 project team.
17 #include <linux/delay.h>
18 #include <linux/ktime.h>
19 #include <linux/module.h>
22 #include <linux/pm_runtime.h>
24 #include "sdhci-pltfm.h"
25 #include "sdhci-xenon.h"
27 static int xenon_enable_internal_clk(struct sdhci_host *host)
32 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
33 reg |= SDHCI_CLOCK_INT_EN;
34 sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
36 timeout = ktime_add_ms(ktime_get(), 20);
38 bool timedout = ktime_after(ktime_get(), timeout);
40 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
41 if (reg & SDHCI_CLOCK_INT_STABLE)
44 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n");
47 usleep_range(900, 1100);
53 /* Set SDCLK-off-while-idle */
54 static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
55 unsigned char sdhc_id, bool enable)
60 reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
61 /* Get the bit shift basing on the SDHC index */
62 mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
68 sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
71 /* Enable/Disable the Auto Clock Gating function */
72 static void xenon_set_acg(struct sdhci_host *host, bool enable)
76 reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
78 reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK;
80 reg |= XENON_AUTO_CLKGATE_DISABLE_MASK;
81 sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
84 /* Enable this SDHC */
85 static void xenon_enable_sdhc(struct sdhci_host *host,
86 unsigned char sdhc_id)
90 reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
91 reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
92 sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
94 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
96 * Force to clear BUS_TEST to
97 * skip bus_test_pre and bus_test_post
99 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST;
102 /* Disable this SDHC */
103 static void xenon_disable_sdhc(struct sdhci_host *host,
104 unsigned char sdhc_id)
108 reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
109 reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
110 sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
113 /* Enable Parallel Transfer Mode */
114 static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host,
115 unsigned char sdhc_id)
119 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
121 sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
124 /* Mask command conflict error */
125 static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
129 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
130 reg |= XENON_MASK_CMD_CONFLICT_ERR;
131 sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
134 static void xenon_retune_setup(struct sdhci_host *host)
136 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
137 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
140 /* Disable the Re-Tuning Request functionality */
141 reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL);
142 reg &= ~XENON_RETUNING_COMPATIBLE;
143 sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL);
145 /* Disable the Re-tuning Interrupt */
146 reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
147 reg &= ~SDHCI_INT_RETUNE;
148 sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE);
149 reg = sdhci_readl(host, SDHCI_INT_ENABLE);
150 reg &= ~SDHCI_INT_RETUNE;
151 sdhci_writel(host, reg, SDHCI_INT_ENABLE);
153 /* Force to use Tuning Mode 1 */
154 host->tuning_mode = SDHCI_TUNING_MODE_1;
155 /* Set re-tuning period */
156 host->tuning_count = 1 << (priv->tuning_count - 1);
160 * Operations inside struct sdhci_ops
162 /* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
163 static void xenon_reset_exit(struct sdhci_host *host,
164 unsigned char sdhc_id, u8 mask)
166 /* Only SOFTWARE RESET ALL will clear the register setting */
167 if (!(mask & SDHCI_RESET_ALL))
170 /* Disable tuning request and auto-retuning again */
171 xenon_retune_setup(host);
174 * The ACG should be turned off at the early init time, in order
175 * to solve a possible issues with the 1.8V regulator stabilization.
176 * The feature is enabled in later stage.
178 xenon_set_acg(host, false);
180 xenon_set_sdclk_off_idle(host, sdhc_id, false);
182 xenon_mask_cmd_conflict_err(host);
185 static void xenon_reset(struct sdhci_host *host, u8 mask)
187 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
188 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
190 sdhci_reset(host, mask);
191 xenon_reset_exit(host, priv->sdhc_id, mask);
195 * Xenon defines different values for HS200 and HS400
198 static void xenon_set_uhs_signaling(struct sdhci_host *host,
203 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
204 /* Select Bus Speed Mode for host */
205 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
206 if (timing == MMC_TIMING_MMC_HS200)
207 ctrl_2 |= XENON_CTRL_HS200;
208 else if (timing == MMC_TIMING_UHS_SDR104)
209 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
210 else if (timing == MMC_TIMING_UHS_SDR12)
211 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
212 else if (timing == MMC_TIMING_UHS_SDR25)
213 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
214 else if (timing == MMC_TIMING_UHS_SDR50)
215 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
216 else if ((timing == MMC_TIMING_UHS_DDR50) ||
217 (timing == MMC_TIMING_MMC_DDR52))
218 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
219 else if (timing == MMC_TIMING_MMC_HS400)
220 ctrl_2 |= XENON_CTRL_HS400;
221 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
224 static void xenon_set_power(struct sdhci_host *host, unsigned char mode,
227 struct mmc_host *mmc = host->mmc;
230 sdhci_set_power_noreg(host, mode, vdd);
232 if (host->pwr == pwr)
238 if (!IS_ERR(mmc->supply.vmmc))
239 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
242 static void xenon_voltage_switch(struct sdhci_host *host)
244 /* Wait for 5ms after set 1.8V signal enable bit */
245 usleep_range(5000, 5500);
248 * For some reason the controller's Host Control2 register reports
249 * the bit representing 1.8V signaling as 0 when read after it was
250 * written as 1. Subsequent read reports 1.
252 * Since this may cause some issues, do an empty read of the Host
253 * Control2 register here to circumvent this.
255 sdhci_readw(host, SDHCI_HOST_CONTROL2);
258 static const struct sdhci_ops sdhci_xenon_ops = {
259 .voltage_switch = xenon_voltage_switch,
260 .set_clock = sdhci_set_clock,
261 .set_power = xenon_set_power,
262 .set_bus_width = sdhci_set_bus_width,
263 .reset = xenon_reset,
264 .set_uhs_signaling = xenon_set_uhs_signaling,
265 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
268 static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
269 .ops = &sdhci_xenon_ops,
270 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
271 SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
272 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
276 * Xenon Specific Operations in mmc_host_ops
278 static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
280 struct sdhci_host *host = mmc_priv(mmc);
281 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
282 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
286 * HS400/HS200/eMMC HS doesn't have Preset Value register.
287 * However, sdhci_set_ios will read HS400/HS200 Preset register.
288 * Disable Preset Value register for HS400/HS200.
289 * eMMC HS with preset_enabled set will trigger a bug in
290 * get_preset_value().
292 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
293 (ios->timing == MMC_TIMING_MMC_HS200) ||
294 (ios->timing == MMC_TIMING_MMC_HS)) {
295 host->preset_enabled = false;
296 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
297 host->flags &= ~SDHCI_PV_ENABLED;
299 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
300 reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
301 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
303 host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
306 sdhci_set_ios(mmc, ios);
307 xenon_phy_adj(host, ios);
309 if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
310 xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
313 static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
316 struct sdhci_host *host = mmc_priv(mmc);
319 * Before SD/SDIO set signal voltage, SD bus clock should be
320 * disabled. However, sdhci_set_clock will also disable the Internal
321 * clock in mmc_set_signal_voltage().
322 * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated.
323 * Thus here manually enable internal clock.
325 * After switch completes, it is unnecessary to disable internal clock,
326 * since keeping internal clock active obeys SD spec.
328 xenon_enable_internal_clk(host);
330 xenon_soc_pad_ctrl(host, ios->signal_voltage);
333 * If Vqmmc is fixed on platform, vqmmc regulator should be unavailable.
334 * Thus SDHCI_CTRL_VDD_180 bit might not work then.
335 * Skip the standard voltage switch to avoid any issue.
337 if (PTR_ERR(mmc->supply.vqmmc) == -ENODEV)
340 return sdhci_start_signal_voltage_switch(mmc, ios);
345 * priv->init_card_type will be used in PHY timing adjustment.
347 static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card)
349 struct sdhci_host *host = mmc_priv(mmc);
350 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
351 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
353 /* Update card type*/
354 priv->init_card_type = card->type;
357 static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode)
359 struct sdhci_host *host = mmc_priv(mmc);
361 if (host->timing == MMC_TIMING_UHS_DDR50 ||
362 host->timing == MMC_TIMING_MMC_DDR52)
366 * Currently force Xenon driver back to support mode 1 only,
367 * even though Xenon might claim to support mode 2 or mode 3.
368 * It requires more time to test mode 2/mode 3 on more platforms.
370 if (host->tuning_mode != SDHCI_TUNING_MODE_1)
371 xenon_retune_setup(host);
373 return sdhci_execute_tuning(mmc, opcode);
376 static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable)
378 struct sdhci_host *host = mmc_priv(mmc);
379 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
380 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
382 u8 sdhc_id = priv->sdhc_id;
384 sdhci_enable_sdio_irq(mmc, enable);
388 * Set SDIO Card Inserted indication
389 * to enable detecting SDIO async irq.
391 reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
392 reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
393 sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
395 /* Clear SDIO Card Inserted indication */
396 reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
397 reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
398 sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
402 static void xenon_replace_mmc_host_ops(struct sdhci_host *host)
404 host->mmc_host_ops.set_ios = xenon_set_ios;
405 host->mmc_host_ops.start_signal_voltage_switch =
406 xenon_start_signal_voltage_switch;
407 host->mmc_host_ops.init_card = xenon_init_card;
408 host->mmc_host_ops.execute_tuning = xenon_execute_tuning;
409 host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq;
413 * Parse Xenon specific DT properties:
414 * sdhc-id: the index of current SDHC.
415 * Refer to XENON_SYS_CFG_INFO register
416 * tun-count: the interval between re-tuning
418 static int xenon_probe_dt(struct platform_device *pdev)
420 struct device_node *np = pdev->dev.of_node;
421 struct sdhci_host *host = platform_get_drvdata(pdev);
422 struct mmc_host *mmc = host->mmc;
423 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
424 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
425 u32 sdhc_id, nr_sdhc;
428 /* Disable HS200 on Armada AP806 */
429 if (of_device_is_compatible(np, "marvell,armada-ap806-sdhci"))
430 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
433 if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) {
434 nr_sdhc = sdhci_readl(host, XENON_SYS_CFG_INFO);
435 nr_sdhc &= XENON_NR_SUPPORTED_SLOT_MASK;
436 if (unlikely(sdhc_id > nr_sdhc)) {
437 dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n",
442 priv->sdhc_id = sdhc_id;
444 tuning_count = XENON_DEF_TUNING_COUNT;
445 if (!of_property_read_u32(np, "marvell,xenon-tun-count",
447 if (unlikely(tuning_count >= XENON_TMR_RETUN_NO_PRESENT)) {
448 dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n",
449 XENON_DEF_TUNING_COUNT);
450 tuning_count = XENON_DEF_TUNING_COUNT;
453 priv->tuning_count = tuning_count;
455 return xenon_phy_parse_dt(np, host);
458 static int xenon_sdhc_prepare(struct sdhci_host *host)
460 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
461 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
462 u8 sdhc_id = priv->sdhc_id;
465 xenon_enable_sdhc(host, sdhc_id);
468 xenon_set_acg(host, true);
470 /* Enable Parallel Transfer Mode */
471 xenon_enable_sdhc_parallel_tran(host, sdhc_id);
473 /* Disable SDCLK-Off-While-Idle before card init */
474 xenon_set_sdclk_off_idle(host, sdhc_id, false);
476 xenon_mask_cmd_conflict_err(host);
481 static void xenon_sdhc_unprepare(struct sdhci_host *host)
483 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
484 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
485 u8 sdhc_id = priv->sdhc_id;
488 xenon_disable_sdhc(host, sdhc_id);
491 static int xenon_probe(struct platform_device *pdev)
493 struct sdhci_pltfm_host *pltfm_host;
494 struct sdhci_host *host;
495 struct xenon_priv *priv;
498 host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
499 sizeof(struct xenon_priv));
501 return PTR_ERR(host);
503 pltfm_host = sdhci_priv(host);
504 priv = sdhci_pltfm_priv(pltfm_host);
507 * Link Xenon specific mmc_host_ops function,
508 * to replace standard ones in sdhci_ops.
510 xenon_replace_mmc_host_ops(host);
512 pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
513 if (IS_ERR(pltfm_host->clk)) {
514 err = PTR_ERR(pltfm_host->clk);
515 dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err);
518 err = clk_prepare_enable(pltfm_host->clk);
522 priv->axi_clk = devm_clk_get(&pdev->dev, "axi");
523 if (IS_ERR(priv->axi_clk)) {
524 err = PTR_ERR(priv->axi_clk);
525 if (err == -EPROBE_DEFER)
528 err = clk_prepare_enable(priv->axi_clk);
533 err = mmc_of_parse(host->mmc);
537 sdhci_get_of_property(pdev);
539 xenon_set_acg(host, false);
541 /* Xenon specific dt parse */
542 err = xenon_probe_dt(pdev);
546 err = xenon_sdhc_prepare(host);
550 pm_runtime_get_noresume(&pdev->dev);
551 pm_runtime_set_active(&pdev->dev);
552 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
553 pm_runtime_use_autosuspend(&pdev->dev);
554 pm_runtime_enable(&pdev->dev);
555 pm_suspend_ignore_children(&pdev->dev, 1);
557 err = sdhci_add_host(host);
561 pm_runtime_put_autosuspend(&pdev->dev);
566 pm_runtime_disable(&pdev->dev);
567 pm_runtime_put_noidle(&pdev->dev);
568 xenon_sdhc_unprepare(host);
570 clk_disable_unprepare(priv->axi_clk);
572 clk_disable_unprepare(pltfm_host->clk);
574 sdhci_pltfm_free(pdev);
578 static int xenon_remove(struct platform_device *pdev)
580 struct sdhci_host *host = platform_get_drvdata(pdev);
581 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
582 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
584 pm_runtime_get_sync(&pdev->dev);
585 pm_runtime_disable(&pdev->dev);
586 pm_runtime_put_noidle(&pdev->dev);
588 sdhci_remove_host(host, 0);
590 xenon_sdhc_unprepare(host);
591 clk_disable_unprepare(priv->axi_clk);
592 clk_disable_unprepare(pltfm_host->clk);
594 sdhci_pltfm_free(pdev);
599 #ifdef CONFIG_PM_SLEEP
600 static int xenon_suspend(struct device *dev)
602 struct sdhci_host *host = dev_get_drvdata(dev);
603 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
604 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
607 ret = pm_runtime_force_suspend(dev);
609 priv->restore_needed = true;
615 static int xenon_runtime_suspend(struct device *dev)
617 struct sdhci_host *host = dev_get_drvdata(dev);
618 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
619 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
622 ret = sdhci_runtime_suspend_host(host);
626 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
627 mmc_retune_needed(host->mmc);
629 clk_disable_unprepare(pltfm_host->clk);
631 * Need to update the priv->clock here, or when runtime resume
632 * back, phy don't aware the clock change and won't adjust phy
633 * which will cause cmd err
639 static int xenon_runtime_resume(struct device *dev)
641 struct sdhci_host *host = dev_get_drvdata(dev);
642 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
643 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
646 ret = clk_prepare_enable(pltfm_host->clk);
648 dev_err(dev, "can't enable mainck\n");
652 if (priv->restore_needed) {
653 ret = xenon_sdhc_prepare(host);
656 priv->restore_needed = false;
659 ret = sdhci_runtime_resume_host(host);
664 clk_disable_unprepare(pltfm_host->clk);
667 #endif /* CONFIG_PM */
669 static const struct dev_pm_ops sdhci_xenon_dev_pm_ops = {
670 SET_SYSTEM_SLEEP_PM_OPS(xenon_suspend,
671 pm_runtime_force_resume)
672 SET_RUNTIME_PM_OPS(xenon_runtime_suspend,
673 xenon_runtime_resume,
677 static const struct of_device_id sdhci_xenon_dt_ids[] = {
678 { .compatible = "marvell,armada-ap806-sdhci",},
679 { .compatible = "marvell,armada-cp110-sdhci",},
680 { .compatible = "marvell,armada-3700-sdhci",},
683 MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
685 static struct platform_driver sdhci_xenon_driver = {
687 .name = "xenon-sdhci",
688 .of_match_table = sdhci_xenon_dt_ids,
689 .pm = &sdhci_xenon_dev_pm_ops,
691 .probe = xenon_probe,
692 .remove = xenon_remove,
695 module_platform_driver(sdhci_xenon_driver);
697 MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
698 MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>");
699 MODULE_LICENSE("GPL v2");