drivers/mmc/host/sdhci-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2010 Google, Inc.
   4  */
   5
   6 #include <linux/delay.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/err.h>
   9 #include <linux/module.h>
  10 #include <linux/init.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/clk.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/pinctrl/consumer.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/reset.h>
  20 #include <linux/mmc/card.h>
  21 #include <linux/mmc/host.h>
  22 #include <linux/mmc/mmc.h>
  23 #include <linux/mmc/slot-gpio.h>
  24 #include <linux/gpio/consumer.h>
  25 #include <linux/ktime.h>
  26
  27 #include "sdhci-pltfm.h"
  28 #include "cqhci.h"
  29
  30 /* Tegra SDHOST controller vendor register definitions */
  31 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL                   0x100
  32 #define SDHCI_CLOCK_CTRL_TAP_MASK                       0x00ff0000
  33 #define SDHCI_CLOCK_CTRL_TAP_SHIFT                      16
  34 #define SDHCI_CLOCK_CTRL_TRIM_MASK                      0x1f000000
  35 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT                     24
  36 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE          BIT(5)
  37 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE         BIT(3)
  38 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE        BIT(2)
  39
  40 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL                  0x104
  41 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE         BIT(31)
  42
  43 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES                0x10c
  44 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK         0x00003f00
  45 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT        8
  46
  47 #define SDHCI_TEGRA_VENDOR_MISC_CTRL                    0x120
  48 #define SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT             BIT(0)
  49 #define SDHCI_MISC_CTRL_ENABLE_SDR104                   0x8
  50 #define SDHCI_MISC_CTRL_ENABLE_SDR50                    0x10
  51 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300           0x20
  52 #define SDHCI_MISC_CTRL_ENABLE_DDR50                    0x200
  53
  54 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG                   0x1b0
  55 #define SDHCI_TEGRA_DLLCAL_CALIBRATE                    BIT(31)
  56
  57 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA                   0x1bc
  58 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE                   BIT(31)
  59
  60 #define SDHCI_VNDR_TUN_CTRL0_0                          0x1c0
  61 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP                 0x20000
  62 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK         0x03fc0000
  63 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT        18
  64 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK                 0x00001fc0
  65 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT                6
  66 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK              0x000e000
  67 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT             13
  68 #define TRIES_128                                       2
  69 #define TRIES_256                                       4
  70 #define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK          0x7
  71
  72 #define SDHCI_TEGRA_VNDR_TUN_CTRL1_0                    0x1c4
  73 #define SDHCI_TEGRA_VNDR_TUN_STATUS0                    0x1C8
  74 #define SDHCI_TEGRA_VNDR_TUN_STATUS1                    0x1CC
  75 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK           0xFF
  76 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT      0x8
  77 #define TUNING_WORD_BIT_SIZE                            32
  78
  79 #define SDHCI_TEGRA_AUTO_CAL_CONFIG                     0x1e4
  80 #define SDHCI_AUTO_CAL_START                            BIT(31)
  81 #define SDHCI_AUTO_CAL_ENABLE                           BIT(29)
  82 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK                 0x0000ffff
  83
  84 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL                  0x1e0
  85 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK    0x0000000f
  86 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL     0x7
  87 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD   BIT(31)
  88 #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK          0x07FFF000
  89
  90 #define SDHCI_TEGRA_AUTO_CAL_STATUS                     0x1ec
  91 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE                     BIT(31)
  92
  93 #define NVQUIRK_FORCE_SDHCI_SPEC_200                    BIT(0)
  94 #define NVQUIRK_ENABLE_BLOCK_GAP_DET                    BIT(1)
  95 #define NVQUIRK_ENABLE_SDHCI_SPEC_300                   BIT(2)
  96 #define NVQUIRK_ENABLE_SDR50                            BIT(3)
  97 #define NVQUIRK_ENABLE_SDR104                           BIT(4)
  98 #define NVQUIRK_ENABLE_DDR50                            BIT(5)
  99 /*
 100  * HAS_PADCALIB NVQUIRK is for SoC's supporting auto calibration of pads
 101  * drive strength.
 102  */
 103 #define NVQUIRK_HAS_PADCALIB                            BIT(6)
 104 /*
 105  * NEEDS_PAD_CONTROL NVQUIRK is for SoC's having separate 3V3 and 1V8 pads.
 106  * 3V3/1V8 pad selection happens through pinctrl state selection depending
 107  * on the signaling mode.
 108  */
 109 #define NVQUIRK_NEEDS_PAD_CONTROL                       BIT(7)
 110 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP                 BIT(8)
 111 #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING               BIT(9)
 112
 113 /*
 114  * NVQUIRK_HAS_TMCLK is for SoC's having separate timeout clock for Tegra
 115  * SDMMC hardware data timeout.
 116  */
 117 #define NVQUIRK_HAS_TMCLK                               BIT(10)
 118
 119 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */
 120 #define SDHCI_TEGRA_CQE_BASE_ADDR                       0xF000
 121
 122 #define SDHCI_TEGRA_CQE_TRNS_MODE       (SDHCI_TRNS_MULTI | \
 123                                          SDHCI_TRNS_BLK_CNT_EN | \
 124                                          SDHCI_TRNS_DMA)
 125
 126 struct sdhci_tegra_soc_data {
 127         const struct sdhci_pltfm_data *pdata;
 128         u64 dma_mask;
 129         u32 nvquirks;
 130         u8 min_tap_delay;
 131         u8 max_tap_delay;
 132 };
 133
 134 /* Magic pull up and pull down pad calibration offsets */
 135 struct sdhci_tegra_autocal_offsets {
 136         u32 pull_up_3v3;
 137         u32 pull_down_3v3;
 138         u32 pull_up_3v3_timeout;
 139         u32 pull_down_3v3_timeout;
 140         u32 pull_up_1v8;
 141         u32 pull_down_1v8;
 142         u32 pull_up_1v8_timeout;
 143         u32 pull_down_1v8_timeout;
 144         u32 pull_up_sdr104;
 145         u32 pull_down_sdr104;
 146         u32 pull_up_hs400;
 147         u32 pull_down_hs400;
 148 };
 149
 150 struct sdhci_tegra {
 151         const struct sdhci_tegra_soc_data *soc_data;
 152         struct gpio_desc *power_gpio;
 153         struct clk *tmclk;
 154         bool ddr_signaling;
 155         bool pad_calib_required;
 156         bool pad_control_available;
 157
 158         struct reset_control *rst;
 159         struct pinctrl *pinctrl_sdmmc;
 160         struct pinctrl_state *pinctrl_state_3v3;
 161         struct pinctrl_state *pinctrl_state_1v8;
 162         struct pinctrl_state *pinctrl_state_3v3_drv;
 163         struct pinctrl_state *pinctrl_state_1v8_drv;
 164
 165         struct sdhci_tegra_autocal_offsets autocal_offsets;
 166         ktime_t last_calib;
 167
 168         u32 default_tap;
 169         u32 default_trim;
 170         u32 dqs_trim;
 171         bool enable_hwcq;
 172         unsigned long curr_clk_rate;
 173         u8 tuned_tap_delay;
 174 };
 175
 176 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
 177 {
 178         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 179         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 180         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 181
 182         if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
 183                         (reg == SDHCI_HOST_VERSION))) {
 184                 /* Erratum: Version register is invalid in HW. */
 185                 return SDHCI_SPEC_200;
 186         }
 187
 188         return readw(host->ioaddr + reg);
 189 }
 190
 191 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 192 {
 193         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 194
 195         switch (reg) {
 196         case SDHCI_TRANSFER_MODE:
 197                 /*
 198                  * Postpone this write, we must do it together with a
 199                  * command write that is down below.
 200                  */
 201                 pltfm_host->xfer_mode_shadow = val;
 202                 return;
 203         case SDHCI_COMMAND:
 204                 writel((val << 16) | pltfm_host->xfer_mode_shadow,
 205                         host->ioaddr + SDHCI_TRANSFER_MODE);
 206                 return;
 207         }
 208
 209         writew(val, host->ioaddr + reg);
 210 }
 211
 212 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 213 {
 214         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 215         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 216         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 217
 218         /* Seems like we're getting spurious timeout and crc errors, so
 219          * disable signalling of them. In case of real errors software
 220          * timers should take care of eventually detecting them.
 221          */
 222         if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
 223                 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
 224
 225         writel(val, host->ioaddr + reg);
 226
 227         if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
 228                         (reg == SDHCI_INT_ENABLE))) {
 229                 /* Erratum: Must enable block gap interrupt detection */
 230                 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
 231                 if (val & SDHCI_INT_CARD_INT)
 232                         gap_ctrl |= 0x8;
 233                 else
 234                         gap_ctrl &= ~0x8;
 235                 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
 236         }
 237 }
 238
 239 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable)
 240 {
 241         bool status;
 242         u32 reg;
 243
 244         reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 245         status = !!(reg & SDHCI_CLOCK_CARD_EN);
 246
 247         if (status == enable)
 248                 return status;
 249
 250         if (enable)
 251                 reg |= SDHCI_CLOCK_CARD_EN;
 252         else
 253                 reg &= ~SDHCI_CLOCK_CARD_EN;
 254
 255         sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
 256
 257         return status;
 258 }
 259
 260 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 261 {
 262         bool is_tuning_cmd = 0;
 263         bool clk_enabled;
 264         u8 cmd;
 265
 266         if (reg == SDHCI_COMMAND) {
 267                 cmd = SDHCI_GET_CMD(val);
 268                 is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK ||
 269                                 cmd == MMC_SEND_TUNING_BLOCK_HS200;
 270         }
 271
 272         if (is_tuning_cmd)
 273                 clk_enabled = tegra_sdhci_configure_card_clk(host, 0);
 274
 275         writew(val, host->ioaddr + reg);
 276
 277         if (is_tuning_cmd) {
 278                 udelay(1);
 279                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 280                 tegra_sdhci_configure_card_clk(host, clk_enabled);
 281         }
 282 }
 283
 284 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
 285 {
 286         /*
 287          * Write-enable shall be assumed if GPIO is missing in a board's
 288          * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on
 289          * Tegra.
 290          */
 291         return mmc_gpio_get_ro(host->mmc);
 292 }
 293
 294 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host)
 295 {
 296         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 297         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 298         int has_1v8, has_3v3;
 299
 300         /*
 301          * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad
 302          * voltage configuration in order to perform voltage switching. This
 303          * means that valid pinctrl info is required on SDHCI instances capable
 304          * of performing voltage switching. Whether or not an SDHCI instance is
 305          * capable of voltage switching is determined based on the regulator.
 306          */
 307
 308         if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))
 309                 return true;
 310
 311         if (IS_ERR(host->mmc->supply.vqmmc))
 312                 return false;
 313
 314         has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
 315                                                  1700000, 1950000);
 316
 317         has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
 318                                                  2700000, 3600000);
 319
 320         if (has_1v8 == 1 && has_3v3 == 1)
 321                 return tegra_host->pad_control_available;
 322
 323         /* Fixed voltage, no pad control required. */
 324         return true;
 325 }
 326
 327 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
 328 {
 329         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 330         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 331         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 332         bool card_clk_enabled = false;
 333         u32 reg;
 334
 335         /*
 336          * Touching the tap values is a bit tricky on some SoC generations.
 337          * The quirk enables a workaround for a glitch that sometimes occurs if
 338          * the tap values are changed.
 339          */
 340
 341         if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP)
 342                 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
 343
 344         reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 345         reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
 346         reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
 347         sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 348
 349         if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP &&
 350             card_clk_enabled) {
 351                 udelay(1);
 352                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 353                 tegra_sdhci_configure_card_clk(host, card_clk_enabled);
 354         }
 355 }
 356
 357 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
 358 {
 359         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 360         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 361         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 362         u32 misc_ctrl, clk_ctrl, pad_ctrl;
 363
 364         sdhci_reset(host, mask);
 365
 366         if (!(mask & SDHCI_RESET_ALL))
 367                 return;
 368
 369         tegra_sdhci_set_tap(host, tegra_host->default_tap);
 370
 371         misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
 372         clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 373
 374         misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 |
 375                        SDHCI_MISC_CTRL_ENABLE_SDR50 |
 376                        SDHCI_MISC_CTRL_ENABLE_DDR50 |
 377                        SDHCI_MISC_CTRL_ENABLE_SDR104);
 378
 379         clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK |
 380                       SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE);
 381
 382         if (tegra_sdhci_is_pad_and_regulator_valid(host)) {
 383                 /* Erratum: Enable SDHCI spec v3.00 support */
 384                 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
 385                         misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
 386                 /* Advertise UHS modes as supported by host */
 387                 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
 388                         misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
 389                 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
 390                         misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
 391                 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
 392                         misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
 393                 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
 394                         clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
 395         }
 396
 397         clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT;
 398
 399         sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
 400         sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 401
 402         if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) {
 403                 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
 404                 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK;
 405                 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL;
 406                 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
 407
 408                 tegra_host->pad_calib_required = true;
 409         }
 410
 411         tegra_host->ddr_signaling = false;
 412 }
 413
 414 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable)
 415 {
 416         u32 val;
 417
 418         /*
 419          * Enable or disable the additional I/O pad used by the drive strength
 420          * calibration process.
 421          */
 422         val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
 423
 424         if (enable)
 425                 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD;
 426         else
 427                 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD;
 428
 429         sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
 430
 431         if (enable)
 432                 usleep_range(1, 2);
 433 }
 434
 435 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host,
 436                                                u16 pdpu)
 437 {
 438         u32 reg;
 439
 440         reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 441         reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK;
 442         reg |= pdpu;
 443         sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 444 }
 445
 446 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage,
 447                                    bool state_drvupdn)
 448 {
 449         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 450         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 451         struct sdhci_tegra_autocal_offsets *offsets =
 452                                                 &tegra_host->autocal_offsets;
 453         struct pinctrl_state *pinctrl_drvupdn = NULL;
 454         int ret = 0;
 455         u8 drvup = 0, drvdn = 0;
 456         u32 reg;
 457
 458         if (!state_drvupdn) {
 459                 /* PADS Drive Strength */
 460                 if (voltage == MMC_SIGNAL_VOLTAGE_180) {
 461                         if (tegra_host->pinctrl_state_1v8_drv) {
 462                                 pinctrl_drvupdn =
 463                                         tegra_host->pinctrl_state_1v8_drv;
 464                         } else {
 465                                 drvup = offsets->pull_up_1v8_timeout;
 466                                 drvdn = offsets->pull_down_1v8_timeout;
 467                         }
 468                 } else {
 469                         if (tegra_host->pinctrl_state_3v3_drv) {
 470                                 pinctrl_drvupdn =
 471                                         tegra_host->pinctrl_state_3v3_drv;
 472                         } else {
 473                                 drvup = offsets->pull_up_3v3_timeout;
 474                                 drvdn = offsets->pull_down_3v3_timeout;
 475                         }
 476                 }
 477
 478                 if (pinctrl_drvupdn != NULL) {
 479                         ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
 480                                                         pinctrl_drvupdn);
 481                         if (ret < 0)
 482                                 dev_err(mmc_dev(host->mmc),
 483                                         "failed pads drvupdn, ret: %d\n", ret);
 484                 } else if ((drvup) || (drvdn)) {
 485                         reg = sdhci_readl(host,
 486                                         SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
 487                         reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK;
 488                         reg |= (drvup << 20) | (drvdn << 12);
 489                         sdhci_writel(host, reg,
 490                                         SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
 491                 }
 492
 493         } else {
 494                 /* Dual Voltage PADS Voltage selection */
 495                 if (!tegra_host->pad_control_available)
 496                         return 0;
 497
 498                 if (voltage == MMC_SIGNAL_VOLTAGE_180) {
 499                         ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
 500                                                 tegra_host->pinctrl_state_1v8);
 501                         if (ret < 0)
 502                                 dev_err(mmc_dev(host->mmc),
 503                                         "setting 1.8V failed, ret: %d\n", ret);
 504                 } else {
 505                         ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
 506                                                 tegra_host->pinctrl_state_3v3);
 507                         if (ret < 0)
 508                                 dev_err(mmc_dev(host->mmc),
 509                                         "setting 3.3V failed, ret: %d\n", ret);
 510                 }
 511         }
 512
 513         return ret;
 514 }
 515
 516 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
 517 {
 518         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 519         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 520         struct sdhci_tegra_autocal_offsets offsets =
 521                         tegra_host->autocal_offsets;
 522         struct mmc_ios *ios = &host->mmc->ios;
 523         bool card_clk_enabled;
 524         u16 pdpu;
 525         u32 reg;
 526         int ret;
 527
 528         switch (ios->timing) {
 529         case MMC_TIMING_UHS_SDR104:
 530                 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104;
 531                 break;
 532         case MMC_TIMING_MMC_HS400:
 533                 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400;
 534                 break;
 535         default:
 536                 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
 537                         pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8;
 538                 else
 539                         pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3;
 540         }
 541
 542         /* Set initial offset before auto-calibration */
 543         tegra_sdhci_set_pad_autocal_offset(host, pdpu);
 544
 545         card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
 546
 547         tegra_sdhci_configure_cal_pad(host, true);
 548
 549         reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 550         reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
 551         sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 552
 553         usleep_range(1, 2);
 554         /* 10 ms timeout */
 555         ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS,
 556                                  reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE),
 557                                  1000, 10000);
 558
 559         tegra_sdhci_configure_cal_pad(host, false);
 560
 561         tegra_sdhci_configure_card_clk(host, card_clk_enabled);
 562
 563         if (ret) {
 564                 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n");
 565
 566                 /* Disable automatic cal and use fixed Drive Strengths */
 567                 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 568                 reg &= ~SDHCI_AUTO_CAL_ENABLE;
 569                 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 570
 571                 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false);
 572                 if (ret < 0)
 573                         dev_err(mmc_dev(host->mmc),
 574                                 "Setting drive strengths failed: %d\n", ret);
 575         }
 576 }
 577
 578 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host)
 579 {
 580         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 581         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 582         struct sdhci_tegra_autocal_offsets *autocal =
 583                         &tegra_host->autocal_offsets;
 584         int err;
 585
 586         err = device_property_read_u32(host->mmc->parent,
 587                         "nvidia,pad-autocal-pull-up-offset-3v3",
 588                         &autocal->pull_up_3v3);
 589         if (err)
 590                 autocal->pull_up_3v3 = 0;
 591
 592         err = device_property_read_u32(host->mmc->parent,
 593                         "nvidia,pad-autocal-pull-down-offset-3v3",
 594                         &autocal->pull_down_3v3);
 595         if (err)
 596                 autocal->pull_down_3v3 = 0;
 597
 598         err = device_property_read_u32(host->mmc->parent,
 599                         "nvidia,pad-autocal-pull-up-offset-1v8",
 600                         &autocal->pull_up_1v8);
 601         if (err)
 602                 autocal->pull_up_1v8 = 0;
 603
 604         err = device_property_read_u32(host->mmc->parent,
 605                         "nvidia,pad-autocal-pull-down-offset-1v8",
 606                         &autocal->pull_down_1v8);
 607         if (err)
 608                 autocal->pull_down_1v8 = 0;
 609
 610         err = device_property_read_u32(host->mmc->parent,
 611                         "nvidia,pad-autocal-pull-up-offset-sdr104",
 612                         &autocal->pull_up_sdr104);
 613         if (err)
 614                 autocal->pull_up_sdr104 = autocal->pull_up_1v8;
 615
 616         err = device_property_read_u32(host->mmc->parent,
 617                         "nvidia,pad-autocal-pull-down-offset-sdr104",
 618                         &autocal->pull_down_sdr104);
 619         if (err)
 620                 autocal->pull_down_sdr104 = autocal->pull_down_1v8;
 621
 622         err = device_property_read_u32(host->mmc->parent,
 623                         "nvidia,pad-autocal-pull-up-offset-hs400",
 624                         &autocal->pull_up_hs400);
 625         if (err)
 626                 autocal->pull_up_hs400 = autocal->pull_up_1v8;
 627
 628         err = device_property_read_u32(host->mmc->parent,
 629                         "nvidia,pad-autocal-pull-down-offset-hs400",
 630                         &autocal->pull_down_hs400);
 631         if (err)
 632                 autocal->pull_down_hs400 = autocal->pull_down_1v8;
 633
 634         /*
 635          * Different fail-safe drive strength values based on the signaling
 636          * voltage are applicable for SoCs supporting 3V3 and 1V8 pad controls.
 637          * So, avoid reading below device tree properties for SoCs that don't
 638          * have NVQUIRK_NEEDS_PAD_CONTROL.
 639          */
 640         if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))
 641                 return;
 642
 643         err = device_property_read_u32(host->mmc->parent,
 644                         "nvidia,pad-autocal-pull-up-offset-3v3-timeout",
 645                         &autocal->pull_up_3v3_timeout);
 646         if (err) {
 647                 if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
 648                         (tegra_host->pinctrl_state_3v3_drv == NULL))
 649                         pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
 650                                 mmc_hostname(host->mmc));
 651                 autocal->pull_up_3v3_timeout = 0;
 652         }
 653
 654         err = device_property_read_u32(host->mmc->parent,
 655                         "nvidia,pad-autocal-pull-down-offset-3v3-timeout",
 656                         &autocal->pull_down_3v3_timeout);
 657         if (err) {
 658                 if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
 659                         (tegra_host->pinctrl_state_3v3_drv == NULL))
 660                         pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
 661                                 mmc_hostname(host->mmc));
 662                 autocal->pull_down_3v3_timeout = 0;
 663         }
 664
 665         err = device_property_read_u32(host->mmc->parent,
 666                         "nvidia,pad-autocal-pull-up-offset-1v8-timeout",
 667                         &autocal->pull_up_1v8_timeout);
 668         if (err) {
 669                 if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
 670                         (tegra_host->pinctrl_state_1v8_drv == NULL))
 671                         pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
 672                                 mmc_hostname(host->mmc));
 673                 autocal->pull_up_1v8_timeout = 0;
 674         }
 675
 676         err = device_property_read_u32(host->mmc->parent,
 677                         "nvidia,pad-autocal-pull-down-offset-1v8-timeout",
 678                         &autocal->pull_down_1v8_timeout);
 679         if (err) {
 680                 if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
 681                         (tegra_host->pinctrl_state_1v8_drv == NULL))
 682                         pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
 683                                 mmc_hostname(host->mmc));
 684                 autocal->pull_down_1v8_timeout = 0;
 685         }
 686 }
 687
 688 static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 689 {
 690         struct sdhci_host *host = mmc_priv(mmc);
 691         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 692         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 693         ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib);
 694
 695         /* 100 ms calibration interval is specified in the TRM */
 696         if (ktime_to_ms(since_calib) > 100) {
 697                 tegra_sdhci_pad_autocalib(host);
 698                 tegra_host->last_calib = ktime_get();
 699         }
 700
 701         sdhci_request(mmc, mrq);
 702 }
 703
 704 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host)
 705 {
 706         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 707         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 708         int err;
 709
 710         err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap",
 711                                        &tegra_host->default_tap);
 712         if (err)
 713                 tegra_host->default_tap = 0;
 714
 715         err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim",
 716                                        &tegra_host->default_trim);
 717         if (err)
 718                 tegra_host->default_trim = 0;
 719
 720         err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim",
 721                                        &tegra_host->dqs_trim);
 722         if (err)
 723                 tegra_host->dqs_trim = 0x11;
 724 }
 725
 726 static void tegra_sdhci_parse_dt(struct sdhci_host *host)
 727 {
 728         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 729         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 730
 731         if (device_property_read_bool(host->mmc->parent, "supports-cqe"))
 732                 tegra_host->enable_hwcq = true;
 733         else
 734                 tegra_host->enable_hwcq = false;
 735
 736         tegra_sdhci_parse_pad_autocal_dt(host);
 737         tegra_sdhci_parse_tap_and_trim(host);
 738 }
 739
 740 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 741 {
 742         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 743         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 744         unsigned long host_clk;
 745
 746         if (!clock)
 747                 return sdhci_set_clock(host, clock);
 748
 749         /*
 750          * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI
 751          * divider to be configured to divided the host clock by two. The SDHCI
 752          * clock divider is calculated as part of sdhci_set_clock() by
 753          * sdhci_calc_clk(). The divider is calculated from host->max_clk and
 754          * the requested clock rate.
 755          *
 756          * By setting the host->max_clk to clock * 2 the divider calculation
 757          * will always result in the correct value for DDR50/52 modes,
 758          * regardless of clock rate rounding, which may happen if the value
 759          * from clk_get_rate() is used.
 760          */
 761         host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
 762         clk_set_rate(pltfm_host->clk, host_clk);
 763         tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk);
 764         if (tegra_host->ddr_signaling)
 765                 host->max_clk = host_clk;
 766         else
 767                 host->max_clk = clk_get_rate(pltfm_host->clk);
 768
 769         sdhci_set_clock(host, clock);
 770
 771         if (tegra_host->pad_calib_required) {
 772                 tegra_sdhci_pad_autocalib(host);
 773                 tegra_host->pad_calib_required = false;
 774         }
 775 }
 776
 777 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
 778                                               struct mmc_ios *ios)
 779 {
 780         struct sdhci_host *host = mmc_priv(mmc);
 781         u32 val;
 782
 783         val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
 784
 785         if (ios->enhanced_strobe) {
 786                 val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
 787                 /*
 788                  * When CMD13 is sent from mmc_select_hs400es() after
 789                  * switching to HS400ES mode, the bus is operating at
 790                  * either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR.
 791                  * To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI
 792                  * interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host
 793                  * controller CAR clock and the interface clock are rate matched.
 794                  */
 795                 tegra_sdhci_set_clock(host, MMC_HS200_MAX_DTR);
 796         } else {
 797                 val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
 798         }
 799
 800         sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
 801 }
 802
 803 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
 804 {
 805         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 806
 807         return clk_round_rate(pltfm_host->clk, UINT_MAX);
 808 }
 809
 810 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim)
 811 {
 812         u32 val;
 813
 814         val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
 815         val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK;
 816         val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT;
 817         sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
 818 }
 819
 820 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host)
 821 {
 822         u32 reg;
 823         int err;
 824
 825         reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
 826         reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE;
 827         sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
 828
 829         /* 1 ms sleep, 5 ms timeout */
 830         err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA,
 831                                  reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE),
 832                                  1000, 5000);
 833         if (err)
 834                 dev_err(mmc_dev(host->mmc),
 835                         "HS400 delay line calibration timed out\n");
 836 }
 837
 838 static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 thd_up,
 839                                        u8 thd_low, u8 fixed_tap)
 840 {
 841         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 842         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 843         u32 val, tun_status;
 844         u8 word, bit, edge1, tap, window;
 845         bool tap_result;
 846         bool start_fail = false;
 847         bool start_pass = false;
 848         bool end_pass = false;
 849         bool first_fail = false;
 850         bool first_pass = false;
 851         u8 start_pass_tap = 0;
 852         u8 end_pass_tap = 0;
 853         u8 first_fail_tap = 0;
 854         u8 first_pass_tap = 0;
 855         u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE;
 856
 857         /*
 858          * Read auto-tuned results and extract good valid passing window by
 859          * filtering out un-wanted bubble/partial/merged windows.
 860          */
 861         for (word = 0; word < total_tuning_words; word++) {
 862                 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
 863                 val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK;
 864                 val |= word;
 865                 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0);
 866                 tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0);
 867                 bit = 0;
 868                 while (bit < TUNING_WORD_BIT_SIZE) {
 869                         tap = word * TUNING_WORD_BIT_SIZE + bit;
 870                         tap_result = tun_status & (1 << bit);
 871                         if (!tap_result && !start_fail) {
 872                                 start_fail = true;
 873                                 if (!first_fail) {
 874                                         first_fail_tap = tap;
 875                                         first_fail = true;
 876                                 }
 877
 878                         } else if (tap_result && start_fail && !start_pass) {
 879                                 start_pass_tap = tap;
 880                                 start_pass = true;
 881                                 if (!first_pass) {
 882                                         first_pass_tap = tap;
 883                                         first_pass = true;
 884                                 }
 885
 886                         } else if (!tap_result && start_fail && start_pass &&
 887                                    !end_pass) {
 888                                 end_pass_tap = tap - 1;
 889                                 end_pass = true;
 890                         } else if (tap_result && start_pass && start_fail &&
 891                                    end_pass) {
 892                                 window = end_pass_tap - start_pass_tap;
 893                                 /* discard merged window and bubble window */
 894                                 if (window >= thd_up || window < thd_low) {
 895                                         start_pass_tap = tap;
 896                                         end_pass = false;
 897                                 } else {
 898                                         /* set tap at middle of valid window */
 899                                         tap = start_pass_tap + window / 2;
 900                                         tegra_host->tuned_tap_delay = tap;
 901                                         return;
 902                                 }
 903                         }
 904
 905                         bit++;
 906                 }
 907         }
 908
 909         if (!first_fail) {
 910                 WARN(1, "no edge detected, continue with hw tuned delay.\n");
 911         } else if (first_pass) {
 912                 /* set tap location at fixed tap relative to the first edge */
 913                 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2;
 914                 if (edge1 - 1 > fixed_tap)
 915                         tegra_host->tuned_tap_delay = edge1 - fixed_tap;
 916                 else
 917                         tegra_host->tuned_tap_delay = edge1 + fixed_tap;
 918         }
 919 }
 920
 921 static void tegra_sdhci_post_tuning(struct sdhci_host *host)
 922 {
 923         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 924         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 925         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 926         u32 avg_tap_dly, val, min_tap_dly, max_tap_dly;
 927         u8 fixed_tap, start_tap, end_tap, window_width;
 928         u8 thdupper, thdlower;
 929         u8 num_iter;
 930         u32 clk_rate_mhz, period_ps, bestcase, worstcase;
 931
 932         /* retain HW tuned tap to use incase if no correction is needed */
 933         val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 934         tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >>
 935                                       SDHCI_CLOCK_CTRL_TAP_SHIFT;
 936         if (soc_data->min_tap_delay && soc_data->max_tap_delay) {
 937                 min_tap_dly = soc_data->min_tap_delay;
 938                 max_tap_dly = soc_data->max_tap_delay;
 939                 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC;
 940                 period_ps = USEC_PER_SEC / clk_rate_mhz;
 941                 bestcase = period_ps / min_tap_dly;
 942                 worstcase = period_ps / max_tap_dly;
 943                 /*
 944                  * Upper and Lower bound thresholds used to detect merged and
 945                  * bubble windows
 946                  */
 947                 thdupper = (2 * worstcase + bestcase) / 2;
 948                 thdlower = worstcase / 4;
 949                 /*
 950                  * fixed tap is used when HW tuning result contains single edge
 951                  * and tap is set at fixed tap delay relative to the first edge
 952                  */
 953                 avg_tap_dly = (period_ps * 2) / (min_tap_dly + max_tap_dly);
 954                 fixed_tap = avg_tap_dly / 2;
 955
 956                 val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1);
 957                 start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK;
 958                 end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) &
 959                           SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK;
 960                 window_width = end_tap - start_tap;
 961                 num_iter = host->tuning_loop_count;
 962                 /*
 963                  * partial window includes edges of the tuning range.
 964                  * merged window includes more taps so window width is higher
 965                  * than upper threshold.
 966                  */
 967                 if (start_tap == 0 || (end_tap == (num_iter - 1)) ||
 968                     (end_tap == num_iter - 2) || window_width >= thdupper) {
 969                         pr_debug("%s: Apply tuning correction\n",
 970                                  mmc_hostname(host->mmc));
 971                         tegra_sdhci_tap_correction(host, thdupper, thdlower,
 972                                                    fixed_tap);
 973                 }
 974         }
 975
 976         tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
 977 }
 978
 979 static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode)
 980 {
 981         struct sdhci_host *host = mmc_priv(mmc);
 982         int err;
 983
 984         err = sdhci_execute_tuning(mmc, opcode);
 985         if (!err && !host->tuning_err)
 986                 tegra_sdhci_post_tuning(host);
 987
 988         return err;
 989 }
 990
 991 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
 992                                           unsigned timing)
 993 {
 994         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 995         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 996         bool set_default_tap = false;
 997         bool set_dqs_trim = false;
 998         bool do_hs400_dll_cal = false;
 999         u8 iter = TRIES_256;
1000         u32 val;
1001
1002         tegra_host->ddr_signaling = false;
1003         switch (timing) {
1004         case MMC_TIMING_UHS_SDR50:
1005                 break;
1006         case MMC_TIMING_UHS_SDR104:
1007         case MMC_TIMING_MMC_HS200:
1008                 /* Don't set default tap on tunable modes. */
1009                 iter = TRIES_128;
1010                 break;
1011         case MMC_TIMING_MMC_HS400:
1012                 set_dqs_trim = true;
1013                 do_hs400_dll_cal = true;
1014                 iter = TRIES_128;
1015                 break;
1016         case MMC_TIMING_MMC_DDR52:
1017         case MMC_TIMING_UHS_DDR50:
1018                 tegra_host->ddr_signaling = true;
1019                 set_default_tap = true;
1020                 break;
1021         default:
1022                 set_default_tap = true;
1023                 break;
1024         }
1025
1026         val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
1027         val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK |
1028                  SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK |
1029                  SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK);
1030         val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT |
1031                 0 << SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT |
1032                 1 << SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT);
1033         sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0);
1034         sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0);
1035
1036         host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256;
1037
1038         sdhci_set_uhs_signaling(host, timing);
1039
1040         tegra_sdhci_pad_autocalib(host);
1041
1042         if (tegra_host->tuned_tap_delay && !set_default_tap)
1043                 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
1044         else
1045                 tegra_sdhci_set_tap(host, tegra_host->default_tap);
1046
1047         if (set_dqs_trim)
1048                 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim);
1049
1050         if (do_hs400_dll_cal)
1051                 tegra_sdhci_hs400_dll_cal(host);
1052 }
1053
1054 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
1055 {
1056         unsigned int min, max;
1057
1058         /*
1059          * Start search for minimum tap value at 10, as smaller values are
1060          * may wrongly be reported as working but fail at higher speeds,
1061          * according to the TRM.
1062          */
1063         min = 10;
1064         while (min < 255) {
1065                 tegra_sdhci_set_tap(host, min);
1066                 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1067                         break;
1068                 min++;
1069         }
1070
1071         /* Find the maximum tap value that still passes. */
1072         max = min + 1;
1073         while (max < 255) {
1074                 tegra_sdhci_set_tap(host, max);
1075                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1076                         max--;
1077                         break;
1078                 }
1079                 max++;
1080         }
1081
1082         /* The TRM states the ideal tap value is at 75% in the passing range. */
1083         tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
1084
1085         return mmc_send_tuning(host->mmc, opcode, NULL);
1086 }
1087
1088 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
1089                                                    struct mmc_ios *ios)
1090 {
1091         struct sdhci_host *host = mmc_priv(mmc);
1092         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1093         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1094         int ret = 0;
1095
1096         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1097                 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
1098                 if (ret < 0)
1099                         return ret;
1100                 ret = sdhci_start_signal_voltage_switch(mmc, ios);
1101         } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
1102                 ret = sdhci_start_signal_voltage_switch(mmc, ios);
1103                 if (ret < 0)
1104                         return ret;
1105                 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
1106         }
1107
1108         if (tegra_host->pad_calib_required)
1109                 tegra_sdhci_pad_autocalib(host);
1110
1111         return ret;
1112 }
1113
1114 static int tegra_sdhci_init_pinctrl_info(struct device *dev,
1115                                          struct sdhci_tegra *tegra_host)
1116 {
1117         tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev);
1118         if (IS_ERR(tegra_host->pinctrl_sdmmc)) {
1119                 dev_dbg(dev, "No pinctrl info, err: %ld\n",
1120                         PTR_ERR(tegra_host->pinctrl_sdmmc));
1121                 return -1;
1122         }
1123
1124         tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state(
1125                                 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv");
1126         if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) {
1127                 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV)
1128                         tegra_host->pinctrl_state_1v8_drv = NULL;
1129         }
1130
1131         tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state(
1132                                 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv");
1133         if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) {
1134                 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV)
1135                         tegra_host->pinctrl_state_3v3_drv = NULL;
1136         }
1137
1138         tegra_host->pinctrl_state_3v3 =
1139                 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3");
1140         if (IS_ERR(tegra_host->pinctrl_state_3v3)) {
1141                 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n",
1142                          PTR_ERR(tegra_host->pinctrl_state_3v3));
1143                 return -1;
1144         }
1145
1146         tegra_host->pinctrl_state_1v8 =
1147                 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8");
1148         if (IS_ERR(tegra_host->pinctrl_state_1v8)) {
1149                 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n",
1150                          PTR_ERR(tegra_host->pinctrl_state_1v8));
1151                 return -1;
1152         }
1153
1154         tegra_host->pad_control_available = true;
1155
1156         return 0;
1157 }
1158
1159 static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
1160 {
1161         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1162         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1163         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1164
1165         if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
1166                 tegra_host->pad_calib_required = true;
1167 }
1168
1169 static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg)
1170 {
1171         struct mmc_host *mmc = cq_host->mmc;
1172         struct sdhci_host *host = mmc_priv(mmc);
1173         u8 ctrl;
1174         ktime_t timeout;
1175         bool timed_out;
1176
1177         /*
1178          * During CQE resume/unhalt, CQHCI driver unhalts CQE prior to
1179          * cqhci_host_ops enable where SDHCI DMA and BLOCK_SIZE registers need
1180          * to be re-configured.
1181          * Tegra CQHCI/SDHCI prevents write access to block size register when
1182          * CQE is unhalted. So handling CQE resume sequence here to configure
1183          * SDHCI block registers prior to exiting CQE halt state.
1184          */
1185         if (reg == CQHCI_CTL && !(val & CQHCI_HALT) &&
1186             cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) {
1187                 sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
1188                 sdhci_cqe_enable(mmc);
1189                 writel(val, cq_host->mmio + reg);
1190                 timeout = ktime_add_us(ktime_get(), 50);
1191                 while (1) {
1192                         timed_out = ktime_compare(ktime_get(), timeout) > 0;
1193                         ctrl = cqhci_readl(cq_host, CQHCI_CTL);
1194                         if (!(ctrl & CQHCI_HALT) || timed_out)
1195                                 break;
1196                 }
1197                 /*
1198                  * CQE usually resumes very quick, but incase if Tegra CQE
1199                  * doesn't resume retry unhalt.
1200                  */
1201                 if (timed_out)
1202                         writel(val, cq_host->mmio + reg);
1203         } else {
1204                 writel(val, cq_host->mmio + reg);
1205         }
1206 }
1207
1208 static void sdhci_tegra_update_dcmd_desc(struct mmc_host *mmc,
1209                                          struct mmc_request *mrq, u64 *data)
1210 {
1211         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(mmc_priv(mmc));
1212         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1213         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1214
1215         if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING &&
1216             mrq->cmd->flags & MMC_RSP_R1B)
1217                 *data |= CQHCI_CMD_TIMING(1);
1218 }
1219
1220 static void sdhci_tegra_cqe_enable(struct mmc_host *mmc)
1221 {
1222         struct cqhci_host *cq_host = mmc->cqe_private;
1223         struct sdhci_host *host = mmc_priv(mmc);
1224         u32 val;
1225
1226         /*
1227          * Tegra CQHCI/SDMMC design prevents write access to sdhci block size
1228          * register when CQE is enabled and unhalted.
1229          * CQHCI driver enables CQE prior to activation, so disable CQE before
1230          * programming block size in sdhci controller and enable it back.
1231          */
1232         if (!cq_host->activated) {
1233                 val = cqhci_readl(cq_host, CQHCI_CFG);
1234                 if (val & CQHCI_ENABLE)
1235                         cqhci_writel(cq_host, (val & ~CQHCI_ENABLE),
1236                                      CQHCI_CFG);
1237                 sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
1238                 sdhci_cqe_enable(mmc);
1239                 if (val & CQHCI_ENABLE)
1240                         cqhci_writel(cq_host, val, CQHCI_CFG);
1241         }
1242
1243         /*
1244          * CMD CRC errors are seen sometimes with some eMMC devices when status
1245          * command is sent during transfer of last data block which is the
1246          * default case as send status command block counter (CBC) is 1.
1247          * Recommended fix to set CBC to 0 allowing send status command only
1248          * when data lines are idle.
1249          */
1250         val = cqhci_readl(cq_host, CQHCI_SSC1);
1251         val &= ~CQHCI_SSC1_CBC_MASK;
1252         cqhci_writel(cq_host, val, CQHCI_SSC1);
1253 }
1254
1255 static void sdhci_tegra_dumpregs(struct mmc_host *mmc)
1256 {
1257         sdhci_dumpregs(mmc_priv(mmc));
1258 }
1259
1260 static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask)
1261 {
1262         int cmd_error = 0;
1263         int data_error = 0;
1264
1265         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1266                 return intmask;
1267
1268         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1269
1270         return 0;
1271 }
1272
1273 static void tegra_sdhci_set_timeout(struct sdhci_host *host,
1274                                     struct mmc_command *cmd)
1275 {
1276         u32 val;
1277
1278         /*
1279          * HW busy detection timeout is based on programmed data timeout
1280          * counter and maximum supported timeout is 11s which may not be
1281          * enough for long operations like cache flush, sleep awake, erase.
1282          *
1283          * ERASE_TIMEOUT_LIMIT bit of VENDOR_MISC_CTRL register allows
1284          * host controller to wait for busy state until the card is busy
1285          * without HW timeout.
1286          *
1287          * So, use infinite busy wait mode for operations that may take
1288          * more than maximum HW busy timeout of 11s otherwise use finite
1289          * busy wait mode.
1290          */
1291         val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
1292         if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC)
1293                 val |= SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT;
1294         else
1295                 val &= ~SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT;
1296         sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_MISC_CTRL);
1297
1298         __sdhci_set_timeout(host, cmd);
1299 }
1300
1301 static void sdhci_tegra_cqe_pre_enable(struct mmc_host *mmc)
1302 {
1303         struct cqhci_host *cq_host = mmc->cqe_private;
1304         u32 reg;
1305
1306         reg = cqhci_readl(cq_host, CQHCI_CFG);
1307         reg |= CQHCI_ENABLE;
1308         cqhci_writel(cq_host, reg, CQHCI_CFG);
1309 }
1310
1311 static void sdhci_tegra_cqe_post_disable(struct mmc_host *mmc)
1312 {
1313         struct cqhci_host *cq_host = mmc->cqe_private;
1314         struct sdhci_host *host = mmc_priv(mmc);
1315         u32 reg;
1316
1317         reg = cqhci_readl(cq_host, CQHCI_CFG);
1318         reg &= ~CQHCI_ENABLE;
1319         cqhci_writel(cq_host, reg, CQHCI_CFG);
1320         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1321 }
1322
1323 static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = {
1324         .write_l    = tegra_cqhci_writel,
1325         .enable = sdhci_tegra_cqe_enable,
1326         .disable = sdhci_cqe_disable,
1327         .dumpregs = sdhci_tegra_dumpregs,
1328         .update_dcmd_desc = sdhci_tegra_update_dcmd_desc,
1329         .pre_enable = sdhci_tegra_cqe_pre_enable,
1330         .post_disable = sdhci_tegra_cqe_post_disable,
1331 };
1332
1333 static int tegra_sdhci_set_dma_mask(struct sdhci_host *host)
1334 {
1335         struct sdhci_pltfm_host *platform = sdhci_priv(host);
1336         struct sdhci_tegra *tegra = sdhci_pltfm_priv(platform);
1337         const struct sdhci_tegra_soc_data *soc = tegra->soc_data;
1338         struct device *dev = mmc_dev(host->mmc);
1339
1340         if (soc->dma_mask)
1341                 return dma_set_mask_and_coherent(dev, soc->dma_mask);
1342
1343         return 0;
1344 }
1345
1346 static const struct sdhci_ops tegra_sdhci_ops = {
1347         .get_ro     = tegra_sdhci_get_ro,
1348         .read_w     = tegra_sdhci_readw,
1349         .write_l    = tegra_sdhci_writel,
1350         .set_clock  = tegra_sdhci_set_clock,
1351         .set_dma_mask = tegra_sdhci_set_dma_mask,
1352         .set_bus_width = sdhci_set_bus_width,
1353         .reset      = tegra_sdhci_reset,
1354         .platform_execute_tuning = tegra_sdhci_execute_tuning,
1355         .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1356         .voltage_switch = tegra_sdhci_voltage_switch,
1357         .get_max_clock = tegra_sdhci_get_max_clock,
1358 };
1359
1360 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
1361         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1362                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1363                   SDHCI_QUIRK_NO_HISPD_BIT |
1364                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1365                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1366         .ops  = &tegra_sdhci_ops,
1367 };
1368
1369 static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
1370         .pdata = &sdhci_tegra20_pdata,
1371         .dma_mask = DMA_BIT_MASK(32),
1372         .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
1373                     NVQUIRK_ENABLE_BLOCK_GAP_DET,
1374 };
1375
1376 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
1377         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1378                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1379                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1380                   SDHCI_QUIRK_NO_HISPD_BIT |
1381                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1382                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1383         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1384                    SDHCI_QUIRK2_BROKEN_HS200 |
1385                    /*
1386                     * Auto-CMD23 leads to "Got command interrupt 0x00010000 even
1387                     * though no command operation was in progress."
1388                     *
1389                     * The exact reason is unknown, as the same hardware seems
1390                     * to support Auto CMD23 on a downstream 3.1 kernel.
1391                     */
1392                    SDHCI_QUIRK2_ACMD23_BROKEN,
1393         .ops  = &tegra_sdhci_ops,
1394 };
1395
1396 static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
1397         .pdata = &sdhci_tegra30_pdata,
1398         .dma_mask = DMA_BIT_MASK(32),
1399         .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
1400                     NVQUIRK_ENABLE_SDR50 |
1401                     NVQUIRK_ENABLE_SDR104 |
1402                     NVQUIRK_HAS_PADCALIB,
1403 };
1404
1405 static const struct sdhci_ops tegra114_sdhci_ops = {
1406         .get_ro     = tegra_sdhci_get_ro,
1407         .read_w     = tegra_sdhci_readw,
1408         .write_w    = tegra_sdhci_writew,
1409         .write_l    = tegra_sdhci_writel,
1410         .set_clock  = tegra_sdhci_set_clock,
1411         .set_dma_mask = tegra_sdhci_set_dma_mask,
1412         .set_bus_width = sdhci_set_bus_width,
1413         .reset      = tegra_sdhci_reset,
1414         .platform_execute_tuning = tegra_sdhci_execute_tuning,
1415         .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1416         .voltage_switch = tegra_sdhci_voltage_switch,
1417         .get_max_clock = tegra_sdhci_get_max_clock,
1418 };
1419
1420 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
1421         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1422                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1423                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1424                   SDHCI_QUIRK_NO_HISPD_BIT |
1425                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1426                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1427         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1428         .ops  = &tegra114_sdhci_ops,
1429 };
1430
1431 static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
1432         .pdata = &sdhci_tegra114_pdata,
1433         .dma_mask = DMA_BIT_MASK(32),
1434 };
1435
1436 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
1437         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1438                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1439                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1440                   SDHCI_QUIRK_NO_HISPD_BIT |
1441                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1442                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1443         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1444         .ops  = &tegra114_sdhci_ops,
1445 };
1446
1447 static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
1448         .pdata = &sdhci_tegra124_pdata,
1449         .dma_mask = DMA_BIT_MASK(34),
1450 };
1451
1452 static const struct sdhci_ops tegra210_sdhci_ops = {
1453         .get_ro     = tegra_sdhci_get_ro,
1454         .read_w     = tegra_sdhci_readw,
1455         .write_w    = tegra210_sdhci_writew,
1456         .write_l    = tegra_sdhci_writel,
1457         .set_clock  = tegra_sdhci_set_clock,
1458         .set_dma_mask = tegra_sdhci_set_dma_mask,
1459         .set_bus_width = sdhci_set_bus_width,
1460         .reset      = tegra_sdhci_reset,
1461         .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1462         .voltage_switch = tegra_sdhci_voltage_switch,
1463         .get_max_clock = tegra_sdhci_get_max_clock,
1464         .set_timeout = tegra_sdhci_set_timeout,
1465 };
1466
1467 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
1468         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1469                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1470                   SDHCI_QUIRK_NO_HISPD_BIT |
1471                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1472                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1473         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1474         .ops  = &tegra210_sdhci_ops,
1475 };
1476
1477 static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
1478         .pdata = &sdhci_tegra210_pdata,
1479         .dma_mask = DMA_BIT_MASK(34),
1480         .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1481                     NVQUIRK_HAS_PADCALIB |
1482                     NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1483                     NVQUIRK_ENABLE_SDR50 |
1484                     NVQUIRK_ENABLE_SDR104 |
1485                     NVQUIRK_HAS_TMCLK,
1486         .min_tap_delay = 106,
1487         .max_tap_delay = 185,
1488 };
1489
1490 static const struct sdhci_ops tegra186_sdhci_ops = {
1491         .get_ro     = tegra_sdhci_get_ro,
1492         .read_w     = tegra_sdhci_readw,
1493         .write_l    = tegra_sdhci_writel,
1494         .set_clock  = tegra_sdhci_set_clock,
1495         .set_dma_mask = tegra_sdhci_set_dma_mask,
1496         .set_bus_width = sdhci_set_bus_width,
1497         .reset      = tegra_sdhci_reset,
1498         .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1499         .voltage_switch = tegra_sdhci_voltage_switch,
1500         .get_max_clock = tegra_sdhci_get_max_clock,
1501         .irq = sdhci_tegra_cqhci_irq,
1502         .set_timeout = tegra_sdhci_set_timeout,
1503 };
1504
1505 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
1506         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1507                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1508                   SDHCI_QUIRK_NO_HISPD_BIT |
1509                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1510                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1511         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1512         .ops  = &tegra186_sdhci_ops,
1513 };
1514
1515 static const struct sdhci_tegra_soc_data soc_data_tegra186 = {
1516         .pdata = &sdhci_tegra186_pdata,
1517         .dma_mask = DMA_BIT_MASK(40),
1518         .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1519                     NVQUIRK_HAS_PADCALIB |
1520                     NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1521                     NVQUIRK_ENABLE_SDR50 |
1522                     NVQUIRK_ENABLE_SDR104 |
1523                     NVQUIRK_HAS_TMCLK |
1524                     NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING,
1525         .min_tap_delay = 84,
1526         .max_tap_delay = 136,
1527 };
1528
1529 static const struct sdhci_tegra_soc_data soc_data_tegra194 = {
1530         .pdata = &sdhci_tegra186_pdata,
1531         .dma_mask = DMA_BIT_MASK(39),
1532         .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1533                     NVQUIRK_HAS_PADCALIB |
1534                     NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1535                     NVQUIRK_ENABLE_SDR50 |
1536                     NVQUIRK_ENABLE_SDR104 |
1537                     NVQUIRK_HAS_TMCLK,
1538         .min_tap_delay = 96,
1539         .max_tap_delay = 139,
1540 };
1541
1542 static const struct of_device_id sdhci_tegra_dt_match[] = {
1543         { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
1544         { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
1545         { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
1546         { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
1547         { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
1548         { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1549         { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1550         {}
1551 };
1552 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
1553
1554 static int sdhci_tegra_add_host(struct sdhci_host *host)
1555 {
1556         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1557         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1558         struct cqhci_host *cq_host;
1559         bool dma64;
1560         int ret;
1561
1562         if (!tegra_host->enable_hwcq)
1563                 return sdhci_add_host(host);
1564
1565         sdhci_enable_v4_mode(host);
1566
1567         ret = sdhci_setup_host(host);
1568         if (ret)
1569                 return ret;
1570
1571         host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1572
1573         cq_host = devm_kzalloc(host->mmc->parent,
1574                                 sizeof(*cq_host), GFP_KERNEL);
1575         if (!cq_host) {
1576                 ret = -ENOMEM;
1577                 goto cleanup;
1578         }
1579
1580         cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR;
1581         cq_host->ops = &sdhci_tegra_cqhci_ops;
1582
1583         dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1584         if (dma64)
1585                 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1586
1587         ret = cqhci_init(cq_host, host->mmc, dma64);
1588         if (ret)
1589                 goto cleanup;
1590
1591         ret = __sdhci_add_host(host);
1592         if (ret)
1593                 goto cleanup;
1594
1595         return 0;
1596
1597 cleanup:
1598         sdhci_cleanup_host(host);
1599         return ret;
1600 }
1601
1602 static int sdhci_tegra_probe(struct platform_device *pdev)
1603 {
1604         const struct of_device_id *match;
1605         const struct sdhci_tegra_soc_data *soc_data;
1606         struct sdhci_host *host;
1607         struct sdhci_pltfm_host *pltfm_host;
1608         struct sdhci_tegra *tegra_host;
1609         struct clk *clk;
1610         int rc;
1611
1612         match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
1613         if (!match)
1614                 return -EINVAL;
1615         soc_data = match->data;
1616
1617         host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
1618         if (IS_ERR(host))
1619                 return PTR_ERR(host);
1620         pltfm_host = sdhci_priv(host);
1621
1622         tegra_host = sdhci_pltfm_priv(pltfm_host);
1623         tegra_host->ddr_signaling = false;
1624         tegra_host->pad_calib_required = false;
1625         tegra_host->pad_control_available = false;
1626         tegra_host->soc_data = soc_data;
1627
1628         if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) {
1629                 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host);
1630                 if (rc == 0)
1631                         host->mmc_host_ops.start_signal_voltage_switch =
1632                                 sdhci_tegra_start_signal_voltage_switch;
1633         }
1634
1635         /* Hook to periodically rerun pad calibration */
1636         if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
1637                 host->mmc_host_ops.request = tegra_sdhci_request;
1638
1639         host->mmc_host_ops.hs400_enhanced_strobe =
1640                         tegra_sdhci_hs400_enhanced_strobe;
1641
1642         if (!host->ops->platform_execute_tuning)
1643                 host->mmc_host_ops.execute_tuning =
1644                                 tegra_sdhci_execute_hw_tuning;
1645
1646         rc = mmc_of_parse(host->mmc);
1647         if (rc)
1648                 goto err_parse_dt;
1649
1650         if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
1651                 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1652
1653         /* HW busy detection is supported, but R1B responses are required. */
1654         host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
1655
1656         tegra_sdhci_parse_dt(host);
1657
1658         tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
1659                                                          GPIOD_OUT_HIGH);
1660         if (IS_ERR(tegra_host->power_gpio)) {
1661                 rc = PTR_ERR(tegra_host->power_gpio);
1662                 goto err_power_req;
1663         }
1664
1665         /*
1666          * Tegra210 has a separate SDMMC_LEGACY_TM clock used for host
1667          * timeout clock and SW can choose TMCLK or SDCLK for hardware
1668          * data timeout through the bit USE_TMCLK_FOR_DATA_TIMEOUT of
1669          * the register SDHCI_TEGRA_VENDOR_SYS_SW_CTRL.
1670          *
1671          * USE_TMCLK_FOR_DATA_TIMEOUT bit default is set to 1 and SDMMC uses
1672          * 12Mhz TMCLK which is advertised in host capability register.
1673          * With TMCLK of 12Mhz provides maximum data timeout period that can
1674          * be achieved is 11s better than using SDCLK for data timeout.
1675          *
1676          * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's
1677          * supporting separate TMCLK.
1678          */
1679
1680         if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) {
1681                 clk = devm_clk_get(&pdev->dev, "tmclk");
1682                 if (IS_ERR(clk)) {
1683                         rc = PTR_ERR(clk);
1684                         if (rc == -EPROBE_DEFER)
1685                                 goto err_power_req;
1686
1687                         dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc);
1688                         clk = NULL;
1689                 }
1690
1691                 clk_set_rate(clk, 12000000);
1692                 rc = clk_prepare_enable(clk);
1693                 if (rc) {
1694                         dev_err(&pdev->dev,
1695                                 "failed to enable tmclk: %d\n", rc);
1696                         goto err_power_req;
1697                 }
1698
1699                 tegra_host->tmclk = clk;
1700         }
1701
1702         clk = devm_clk_get(mmc_dev(host->mmc), NULL);
1703         if (IS_ERR(clk)) {
1704                 rc = dev_err_probe(&pdev->dev, PTR_ERR(clk),
1705                                    "failed to get clock\n");
1706                 goto err_clk_get;
1707         }
1708         clk_prepare_enable(clk);
1709         pltfm_host->clk = clk;
1710
1711         tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev,
1712                                                            "sdhci");
1713         if (IS_ERR(tegra_host->rst)) {
1714                 rc = PTR_ERR(tegra_host->rst);
1715                 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
1716                 goto err_rst_get;
1717         }
1718
1719         rc = reset_control_assert(tegra_host->rst);
1720         if (rc)
1721                 goto err_rst_get;
1722
1723         usleep_range(2000, 4000);
1724
1725         rc = reset_control_deassert(tegra_host->rst);
1726         if (rc)
1727                 goto err_rst_get;
1728
1729         usleep_range(2000, 4000);
1730
1731         rc = sdhci_tegra_add_host(host);
1732         if (rc)
1733                 goto err_add_host;
1734
1735         return 0;
1736
1737 err_add_host:
1738         reset_control_assert(tegra_host->rst);
1739 err_rst_get:
1740         clk_disable_unprepare(pltfm_host->clk);
1741 err_clk_get:
1742         clk_disable_unprepare(tegra_host->tmclk);
1743 err_power_req:
1744 err_parse_dt:
1745         sdhci_pltfm_free(pdev);
1746         return rc;
1747 }
1748
1749 static int sdhci_tegra_remove(struct platform_device *pdev)
1750 {
1751         struct sdhci_host *host = platform_get_drvdata(pdev);
1752         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1753         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1754
1755         sdhci_remove_host(host, 0);
1756
1757         reset_control_assert(tegra_host->rst);
1758         usleep_range(2000, 4000);
1759         clk_disable_unprepare(pltfm_host->clk);
1760         clk_disable_unprepare(tegra_host->tmclk);
1761
1762         sdhci_pltfm_free(pdev);
1763
1764         return 0;
1765 }
1766
1767 #ifdef CONFIG_PM_SLEEP
1768 static int __maybe_unused sdhci_tegra_suspend(struct device *dev)
1769 {
1770         struct sdhci_host *host = dev_get_drvdata(dev);
1771         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1772         int ret;
1773
1774         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1775                 ret = cqhci_suspend(host->mmc);
1776                 if (ret)
1777                         return ret;
1778         }
1779
1780         ret = sdhci_suspend_host(host);
1781         if (ret) {
1782                 cqhci_resume(host->mmc);
1783                 return ret;
1784         }
1785
1786         clk_disable_unprepare(pltfm_host->clk);
1787         return 0;
1788 }
1789
1790 static int __maybe_unused sdhci_tegra_resume(struct device *dev)
1791 {
1792         struct sdhci_host *host = dev_get_drvdata(dev);
1793         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1794         int ret;
1795
1796         ret = clk_prepare_enable(pltfm_host->clk);
1797         if (ret)
1798                 return ret;
1799
1800         ret = sdhci_resume_host(host);
1801         if (ret)
1802                 goto disable_clk;
1803
1804         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1805                 ret = cqhci_resume(host->mmc);
1806                 if (ret)
1807                         goto suspend_host;
1808         }
1809
1810         return 0;
1811
1812 suspend_host:
1813         sdhci_suspend_host(host);
1814 disable_clk:
1815         clk_disable_unprepare(pltfm_host->clk);
1816         return ret;
1817 }
1818 #endif
1819
1820 static SIMPLE_DEV_PM_OPS(sdhci_tegra_dev_pm_ops, sdhci_tegra_suspend,
1821                          sdhci_tegra_resume);
1822
1823 static struct platform_driver sdhci_tegra_driver = {
1824         .driver         = {
1825                 .name   = "sdhci-tegra",
1826                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1827                 .of_match_table = sdhci_tegra_dt_match,
1828                 .pm     = &sdhci_tegra_dev_pm_ops,
1829         },
1830         .probe          = sdhci_tegra_probe,
1831         .remove         = sdhci_tegra_remove,
1832 };
1833
1834 module_platform_driver(sdhci_tegra_driver);
1835
1836 MODULE_DESCRIPTION("SDHCI driver for Tegra");
1837 MODULE_AUTHOR("Google, Inc.");
1838 MODULE_LICENSE("GPL v2");