drivers/mmc/host/sdhci-sprd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Secure Digital Host Controller
   4 //
   5 // Copyright (C) 2018 Spreadtrum, Inc.
   6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
   7
   8 #include <linux/delay.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/highmem.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/mmc/host.h>
  13 #include <linux/mmc/mmc.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/pinctrl/consumer.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <linux/slab.h>
  22
  23 #include "sdhci-pltfm.h"
  24 #include "mmc_hsq.h"
  25
  26 /* SDHCI_ARGUMENT2 register high 16bit */
  27 #define SDHCI_SPRD_ARG2_STUFF           GENMASK(31, 16)
  28
  29 #define SDHCI_SPRD_REG_32_DLL_CFG       0x200
  30 #define  SDHCI_SPRD_DLL_ALL_CPST_EN     (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
  31 #define  SDHCI_SPRD_DLL_EN              BIT(21)
  32 #define  SDHCI_SPRD_DLL_SEARCH_MODE     BIT(16)
  33 #define  SDHCI_SPRD_DLL_INIT_COUNT      0xc00
  34 #define  SDHCI_SPRD_DLL_PHASE_INTERNAL  0x3
  35
  36 #define SDHCI_SPRD_REG_32_DLL_DLY       0x204
  37
  38 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET        0x208
  39 #define  SDHCIBSPRD_IT_WR_DLY_INV               BIT(5)
  40 #define  SDHCI_SPRD_BIT_CMD_DLY_INV             BIT(13)
  41 #define  SDHCI_SPRD_BIT_POSRD_DLY_INV           BIT(21)
  42 #define  SDHCI_SPRD_BIT_NEGRD_DLY_INV           BIT(29)
  43
  44 #define SDHCI_SPRD_REG_32_DLL_STS0      0x210
  45 #define SDHCI_SPRD_DLL_LOCKED           BIT(18)
  46
  47 #define SDHCI_SPRD_REG_32_BUSY_POSI             0x250
  48 #define  SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN        BIT(25)
  49 #define  SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN        BIT(24)
  50
  51 #define SDHCI_SPRD_REG_DEBOUNCE         0x28C
  52 #define  SDHCI_SPRD_BIT_DLL_BAK         BIT(0)
  53 #define  SDHCI_SPRD_BIT_DLL_VAL         BIT(1)
  54
  55 #define  SDHCI_SPRD_INT_SIGNAL_MASK     0x1B7F410B
  56
  57 /* SDHCI_HOST_CONTROL2 */
  58 #define  SDHCI_SPRD_CTRL_HS200          0x0005
  59 #define  SDHCI_SPRD_CTRL_HS400          0x0006
  60 #define  SDHCI_SPRD_CTRL_HS400ES        0x0007
  61
  62 /*
  63  * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
  64  * reserved, and only used on Spreadtrum's design, the hardware cannot work
  65  * if this bit is cleared.
  66  * 1 : normal work
  67  * 0 : hardware reset
  68  */
  69 #define  SDHCI_HW_RESET_CARD            BIT(3)
  70
  71 #define SDHCI_SPRD_MAX_CUR              0xFFFFFF
  72 #define SDHCI_SPRD_CLK_MAX_DIV          1023
  73
  74 #define SDHCI_SPRD_CLK_DEF_RATE         26000000
  75 #define SDHCI_SPRD_PHY_DLL_CLK          52000000
  76
  77 #define SDHCI_SPRD_MAX_RANGE            0xff
  78 #define SDHCI_SPRD_CMD_DLY_MASK         GENMASK(15, 8)
  79 #define SDHCI_SPRD_POSRD_DLY_MASK       GENMASK(23, 16)
  80 #define SDHCI_SPRD_CPST_EN              GENMASK(27, 24)
  81
  82 struct sdhci_sprd_host {
  83         u32 version;
  84         struct clk *clk_sdio;
  85         struct clk *clk_enable;
  86         struct clk *clk_2x_enable;
  87         struct pinctrl *pinctrl;
  88         struct pinctrl_state *pins_uhs;
  89         struct pinctrl_state *pins_default;
  90         u32 base_rate;
  91         int flags; /* backup of host attribute */
  92         u32 phy_delay[MMC_TIMING_MMC_HS400 + 2];
  93 };
  94
  95 enum sdhci_sprd_tuning_type {
  96         SDHCI_SPRD_TUNING_SD_HS_CMD,
  97         SDHCI_SPRD_TUNING_SD_HS_DATA,
  98 };
  99
 100 struct sdhci_sprd_phy_cfg {
 101         const char *property;
 102         u8 timing;
 103 };
 104
 105 static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = {
 106         { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
 107         { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
 108         { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
 109         { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
 110         { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
 111         { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
 112         { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, },
 113         { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, },
 114         { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, },
 115 };
 116
 117 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
 118
 119 static void sdhci_sprd_init_config(struct sdhci_host *host)
 120 {
 121         u16 val;
 122
 123         /* set dll backup mode */
 124         val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
 125         val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
 126         sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
 127 }
 128
 129 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
 130 {
 131         if (unlikely(reg == SDHCI_MAX_CURRENT))
 132                 return SDHCI_SPRD_MAX_CUR;
 133
 134         return readl_relaxed(host->ioaddr + reg);
 135 }
 136
 137 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
 138 {
 139         /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
 140         if (unlikely(reg == SDHCI_MAX_CURRENT))
 141                 return;
 142
 143         if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
 144                 val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
 145
 146         writel_relaxed(val, host->ioaddr + reg);
 147 }
 148
 149 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
 150 {
 151         /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
 152         if (unlikely(reg == SDHCI_BLOCK_COUNT))
 153                 return;
 154
 155         writew_relaxed(val, host->ioaddr + reg);
 156 }
 157
 158 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
 159 {
 160         /*
 161          * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
 162          * standard specification, sdhci_reset() write this register directly
 163          * without checking other reserved bits, that will clear BIT(3) which
 164          * is defined as hardware reset on Spreadtrum's platform and clearing
 165          * it by mistake will lead the card not work. So here we need to work
 166          * around it.
 167          */
 168         if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
 169                 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
 170                         val |= SDHCI_HW_RESET_CARD;
 171         }
 172
 173         writeb_relaxed(val, host->ioaddr + reg);
 174 }
 175
 176 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
 177 {
 178         u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 179
 180         ctrl &= ~SDHCI_CLOCK_CARD_EN;
 181         sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
 182 }
 183
 184 static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host)
 185 {
 186         u16 ctrl;
 187
 188         ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 189         ctrl |= SDHCI_CLOCK_CARD_EN;
 190         sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
 191 }
 192
 193 static inline void
 194 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
 195 {
 196         u32 dll_dly_offset;
 197
 198         dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
 199         if (en)
 200                 dll_dly_offset |= mask;
 201         else
 202                 dll_dly_offset &= ~mask;
 203         sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
 204 }
 205
 206 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
 207 {
 208         u32 div;
 209
 210         /* select 2x clock source */
 211         if (base_clk <= clk * 2)
 212                 return 0;
 213
 214         div = (u32) (base_clk / (clk * 2));
 215
 216         if ((base_clk / div) > (clk * 2))
 217                 div++;
 218
 219         if (div % 2)
 220                 div = (div + 1) / 2;
 221         else
 222                 div = div / 2;
 223
 224         if (div > SDHCI_SPRD_CLK_MAX_DIV)
 225                 div = SDHCI_SPRD_CLK_MAX_DIV;
 226
 227         return div;
 228 }
 229
 230 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
 231                                         unsigned int clk)
 232 {
 233         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 234         u32 div, val, mask;
 235
 236         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 237
 238         div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
 239         div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
 240         sdhci_enable_clk(host, div);
 241
 242         /* Enable CLK_AUTO when the clock is greater than 400K. */
 243         if (clk > 400000) {
 244                 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
 245                 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN |
 246                         SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
 247                 if (mask != (val & mask)) {
 248                         val |= mask;
 249                         sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
 250                 }
 251         }
 252 }
 253
 254 static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host)
 255 {
 256         u32 tmp;
 257
 258         tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
 259         tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN);
 260         sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
 261         /* wait 1ms */
 262         usleep_range(1000, 1250);
 263
 264         tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
 265         tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE |
 266                 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL;
 267         sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
 268         /* wait 1ms */
 269         usleep_range(1000, 1250);
 270
 271         tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
 272         tmp |= SDHCI_SPRD_DLL_EN;
 273         sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
 274         /* wait 1ms */
 275         usleep_range(1000, 1250);
 276
 277         if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED),
 278                 2000, USEC_PER_SEC, false, host, SDHCI_SPRD_REG_32_DLL_STS0)) {
 279                 pr_err("%s: DLL locked fail!\n", mmc_hostname(host->mmc));
 280                 pr_info("%s: DLL_STS0 : 0x%x, DLL_CFG : 0x%x\n",
 281                          mmc_hostname(host->mmc),
 282                          sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0),
 283                          sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG));
 284         }
 285 }
 286
 287 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
 288 {
 289         bool en = false, clk_changed = false;
 290
 291         if (clock == 0) {
 292                 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 293         } else if (clock != host->clock) {
 294                 sdhci_sprd_sd_clk_off(host);
 295                 _sdhci_sprd_set_clock(host, clock);
 296
 297                 if (clock <= 400000)
 298                         en = true;
 299                 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
 300                                           SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
 301                 clk_changed = true;
 302         } else {
 303                 _sdhci_sprd_set_clock(host, clock);
 304         }
 305
 306         /*
 307          * According to the Spreadtrum SD host specification, when we changed
 308          * the clock to be more than 52M, we should enable the PHY DLL which
 309          * is used to track the clock frequency to make the clock work more
 310          * stable. Otherwise deviation may occur of the higher clock.
 311          */
 312         if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK)
 313                 sdhci_sprd_enable_phy_dll(host);
 314 }
 315
 316 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
 317 {
 318         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 319
 320         return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
 321 }
 322
 323 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
 324 {
 325         return 100000;
 326 }
 327
 328 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
 329                                          unsigned int timing)
 330 {
 331         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 332         struct mmc_host *mmc = host->mmc;
 333         u32 *p = sprd_host->phy_delay;
 334         u16 ctrl_2;
 335
 336         if (timing == host->timing)
 337                 return;
 338
 339         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 340         /* Select Bus Speed Mode for host */
 341         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 342         switch (timing) {
 343         case MMC_TIMING_UHS_SDR12:
 344                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 345                 break;
 346         case MMC_TIMING_MMC_HS:
 347         case MMC_TIMING_SD_HS:
 348         case MMC_TIMING_UHS_SDR25:
 349                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 350                 break;
 351         case MMC_TIMING_UHS_SDR50:
 352                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 353                 break;
 354         case MMC_TIMING_UHS_SDR104:
 355                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 356                 break;
 357         case MMC_TIMING_UHS_DDR50:
 358         case MMC_TIMING_MMC_DDR52:
 359                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 360                 break;
 361         case MMC_TIMING_MMC_HS200:
 362                 ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
 363                 break;
 364         case MMC_TIMING_MMC_HS400:
 365                 ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
 366                 break;
 367         default:
 368                 break;
 369         }
 370
 371         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 372
 373         if (!mmc->ios.enhanced_strobe)
 374                 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
 375 }
 376
 377 static void sdhci_sprd_hw_reset(struct sdhci_host *host)
 378 {
 379         int val;
 380
 381         /*
 382          * Note: don't use sdhci_writeb() API here since it is redirected to
 383          * sdhci_sprd_writeb() in which we have a workaround for
 384          * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
 385          * not be cleared.
 386          */
 387         val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
 388         val &= ~SDHCI_HW_RESET_CARD;
 389         writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
 390         /* wait for 10 us */
 391         usleep_range(10, 20);
 392
 393         val |= SDHCI_HW_RESET_CARD;
 394         writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
 395         usleep_range(300, 500);
 396 }
 397
 398 static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
 399 {
 400         /* The Spredtrum controller actual maximum timeout count is 1 << 31 */
 401         return 1 << 31;
 402 }
 403
 404 static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host)
 405 {
 406         return 0;
 407 }
 408
 409 static void sdhci_sprd_request_done(struct sdhci_host *host,
 410                                     struct mmc_request *mrq)
 411 {
 412         /* Validate if the request was from software queue firstly. */
 413         if (mmc_hsq_finalize_request(host->mmc, mrq))
 414                 return;
 415
 416         mmc_request_done(host->mmc, mrq);
 417 }
 418
 419 static void sdhci_sprd_set_power(struct sdhci_host *host, unsigned char mode,
 420                                  unsigned short vdd)
 421 {
 422         struct mmc_host *mmc = host->mmc;
 423
 424         switch (mode) {
 425         case MMC_POWER_OFF:
 426                 mmc_regulator_set_ocr(host->mmc, mmc->supply.vmmc, 0);
 427
 428                 mmc_regulator_disable_vqmmc(mmc);
 429                 break;
 430         case MMC_POWER_ON:
 431                 mmc_regulator_enable_vqmmc(mmc);
 432                 break;
 433         case MMC_POWER_UP:
 434                 mmc_regulator_set_ocr(host->mmc, mmc->supply.vmmc, vdd);
 435                 break;
 436         }
 437 }
 438
 439 static struct sdhci_ops sdhci_sprd_ops = {
 440         .read_l = sdhci_sprd_readl,
 441         .write_l = sdhci_sprd_writel,
 442         .write_w = sdhci_sprd_writew,
 443         .write_b = sdhci_sprd_writeb,
 444         .set_clock = sdhci_sprd_set_clock,
 445         .set_power = sdhci_sprd_set_power,
 446         .get_max_clock = sdhci_sprd_get_max_clock,
 447         .get_min_clock = sdhci_sprd_get_min_clock,
 448         .set_bus_width = sdhci_set_bus_width,
 449         .reset = sdhci_reset,
 450         .set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
 451         .hw_reset = sdhci_sprd_hw_reset,
 452         .get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
 453         .get_ro = sdhci_sprd_get_ro,
 454         .request_done = sdhci_sprd_request_done,
 455 };
 456
 457 static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc,
 458                                         struct mmc_request *mrq)
 459 {
 460         struct sdhci_host *host = mmc_priv(mmc);
 461         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 462
 463         host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
 464
 465         /*
 466          * From version 4.10 onward, ARGUMENT2 register is also as 32-bit
 467          * block count register which doesn't support stuff bits of
 468          * CMD23 argument on Spreadtrum's sd host controller.
 469          */
 470         if (host->version >= SDHCI_SPEC_410 &&
 471             mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
 472             (host->flags & SDHCI_AUTO_CMD23))
 473                 host->flags &= ~SDHCI_AUTO_CMD23;
 474 }
 475
 476 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
 477 {
 478         sdhci_sprd_check_auto_cmd23(mmc, mrq);
 479
 480         sdhci_request(mmc, mrq);
 481 }
 482
 483 static int sdhci_sprd_request_atomic(struct mmc_host *mmc,
 484                                      struct mmc_request *mrq)
 485 {
 486         sdhci_sprd_check_auto_cmd23(mmc, mrq);
 487
 488         return sdhci_request_atomic(mmc, mrq);
 489 }
 490
 491 static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
 492 {
 493         struct sdhci_host *host = mmc_priv(mmc);
 494         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 495         int ret;
 496
 497         if (!IS_ERR(mmc->supply.vqmmc)) {
 498                 ret = mmc_regulator_set_vqmmc(mmc, ios);
 499                 if (ret < 0) {
 500                         pr_err("%s: Switching signalling voltage failed\n",
 501                                mmc_hostname(mmc));
 502                         return ret;
 503                 }
 504         }
 505
 506         if (IS_ERR(sprd_host->pinctrl))
 507                 goto reset;
 508
 509         switch (ios->signal_voltage) {
 510         case MMC_SIGNAL_VOLTAGE_180:
 511                 ret = pinctrl_select_state(sprd_host->pinctrl,
 512                                            sprd_host->pins_uhs);
 513                 if (ret) {
 514                         pr_err("%s: failed to select uhs pin state\n",
 515                                mmc_hostname(mmc));
 516                         return ret;
 517                 }
 518                 break;
 519
 520         default:
 521                 fallthrough;
 522         case MMC_SIGNAL_VOLTAGE_330:
 523                 ret = pinctrl_select_state(sprd_host->pinctrl,
 524                                            sprd_host->pins_default);
 525                 if (ret) {
 526                         pr_err("%s: failed to select default pin state\n",
 527                                mmc_hostname(mmc));
 528                         return ret;
 529                 }
 530                 break;
 531         }
 532
 533         /* Wait for 300 ~ 500 us for pin state stable */
 534         usleep_range(300, 500);
 535
 536 reset:
 537         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 538
 539         return 0;
 540 }
 541
 542 static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc,
 543                                              struct mmc_ios *ios)
 544 {
 545         struct sdhci_host *host = mmc_priv(mmc);
 546         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 547         u32 *p = sprd_host->phy_delay;
 548         u16 ctrl_2;
 549
 550         if (!ios->enhanced_strobe)
 551                 return;
 552
 553         sdhci_sprd_sd_clk_off(host);
 554
 555         /* Set HS400 enhanced strobe mode */
 556         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 557         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 558         ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES;
 559         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 560
 561         sdhci_sprd_sd_clk_on(host);
 562
 563         /* Set the PHY DLL delay value for HS400 enhanced strobe mode */
 564         sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1],
 565                      SDHCI_SPRD_REG_32_DLL_DLY);
 566 }
 567
 568 static int mmc_send_tuning_cmd(struct mmc_card *card)
 569 {
 570         return mmc_send_status(card, NULL);
 571 }
 572
 573 static int mmc_send_tuning_data(struct mmc_card *card)
 574 {
 575         u8 *status;
 576         int ret;
 577
 578         status = kmalloc(64, GFP_KERNEL);
 579         if (!status)
 580                 return -ENOMEM;
 581
 582         ret = mmc_sd_switch(card, 0, 0, 0, status);
 583
 584         kfree(status);
 585
 586         return ret;
 587 }
 588
 589 static int sdhci_sprd_get_best_clk_sample(struct mmc_host *mmc, u8 *value)
 590 {
 591         int range_end = SDHCI_SPRD_MAX_RANGE;
 592         int range_length = 0;
 593         int middle_range = 0;
 594         int count = 0;
 595         int i;
 596
 597         for (i = 0; i <= SDHCI_SPRD_MAX_RANGE; i++) {
 598                 if (value[i]) {
 599                         pr_debug("%s: tuning ok: %d\n", mmc_hostname(mmc), i);
 600                         count++;
 601                 } else {
 602                         pr_debug("%s: tuning fail: %d\n", mmc_hostname(mmc), i);
 603                         if (range_length < count) {
 604                                 range_length = count;
 605                                 range_end = i - 1;
 606                                 count = 0;
 607                         }
 608                 }
 609         }
 610
 611         if (!count)
 612                 return -EIO;
 613
 614         if (count > range_length) {
 615                 range_length = count;
 616                 range_end = i - 1;
 617         }
 618
 619         middle_range = range_end - (range_length - 1) / 2;
 620
 621         return middle_range;
 622 }
 623
 624 static int sdhci_sprd_tuning(struct mmc_host *mmc, struct mmc_card *card,
 625                         enum sdhci_sprd_tuning_type type)
 626 {
 627         struct sdhci_host *host = mmc_priv(mmc);
 628         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 629         u32 *p = sprd_host->phy_delay;
 630         u32 dll_cfg, dll_dly;
 631         int best_clk_sample;
 632         int err = 0;
 633         u8 *value;
 634         int i;
 635
 636         value = kmalloc(SDHCI_SPRD_MAX_RANGE + 1, GFP_KERNEL);
 637         if (!value)
 638                 return -ENOMEM;
 639
 640         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 641
 642         dll_cfg = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
 643         dll_cfg &= ~SDHCI_SPRD_CPST_EN;
 644         sdhci_writel(host, dll_cfg, SDHCI_SPRD_REG_32_DLL_CFG);
 645
 646         dll_dly = p[mmc->ios.timing];
 647
 648         for (i = 0; i <= SDHCI_SPRD_MAX_RANGE; i++) {
 649                 if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) {
 650                         dll_dly &= ~SDHCI_SPRD_CMD_DLY_MASK;
 651                         dll_dly |= ((i << 8) & SDHCI_SPRD_CMD_DLY_MASK);
 652                 } else {
 653                         dll_dly &= ~SDHCI_SPRD_POSRD_DLY_MASK;
 654                         dll_dly |= ((i << 16) & SDHCI_SPRD_POSRD_DLY_MASK);
 655                 }
 656
 657                 sdhci_writel(host, dll_dly, SDHCI_SPRD_REG_32_DLL_DLY);
 658
 659                 if (type == SDHCI_SPRD_TUNING_SD_HS_CMD)
 660                         value[i] = !mmc_send_tuning_cmd(card);
 661                 else
 662                         value[i] = !mmc_send_tuning_data(card);
 663         }
 664
 665         best_clk_sample = sdhci_sprd_get_best_clk_sample(mmc, value);
 666         if (best_clk_sample < 0) {
 667                 dev_err(mmc_dev(host->mmc), "all tuning phase fail!\n");
 668                 err = best_clk_sample;
 669                 goto out;
 670         }
 671
 672         if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) {
 673                 p[mmc->ios.timing] &= ~SDHCI_SPRD_CMD_DLY_MASK;
 674                 p[mmc->ios.timing] |= ((best_clk_sample << 8) & SDHCI_SPRD_CMD_DLY_MASK);
 675         } else {
 676                 p[mmc->ios.timing] &= ~(SDHCI_SPRD_POSRD_DLY_MASK);
 677                 p[mmc->ios.timing] |= ((best_clk_sample << 16) & SDHCI_SPRD_POSRD_DLY_MASK);
 678         }
 679
 680         pr_debug("%s: the best clk sample %d, delay value 0x%08x\n",
 681                         mmc_hostname(host->mmc), best_clk_sample, p[mmc->ios.timing]);
 682
 683 out:
 684         sdhci_writel(host, p[mmc->ios.timing], SDHCI_SPRD_REG_32_DLL_DLY);
 685
 686         kfree(value);
 687
 688         return err;
 689 }
 690
 691 static int sdhci_sprd_prepare_sd_hs_cmd_tuning(struct mmc_host *mmc, struct mmc_card *card)
 692 {
 693         return sdhci_sprd_tuning(mmc, card, SDHCI_SPRD_TUNING_SD_HS_CMD);
 694 }
 695
 696 static int sdhci_sprd_execute_sd_hs_data_tuning(struct mmc_host *mmc, struct mmc_card *card)
 697 {
 698         return sdhci_sprd_tuning(mmc, card, SDHCI_SPRD_TUNING_SD_HS_DATA);
 699 }
 700
 701 static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
 702                                        struct device_node *np)
 703 {
 704         u32 *p = sprd_host->phy_delay;
 705         int ret, i, index;
 706         u32 val[4];
 707
 708         for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) {
 709                 ret = of_property_read_u32_array(np,
 710                                 sdhci_sprd_phy_cfgs[i].property, val, 4);
 711                 if (ret)
 712                         continue;
 713
 714                 index = sdhci_sprd_phy_cfgs[i].timing;
 715                 p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24);
 716         }
 717 }
 718
 719 static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
 720         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 721                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
 722         .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
 723                    SDHCI_QUIRK2_USE_32BIT_BLK_CNT |
 724                    SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 725         .ops = &sdhci_sprd_ops,
 726 };
 727
 728 static int sdhci_sprd_probe(struct platform_device *pdev)
 729 {
 730         struct sdhci_host *host;
 731         struct sdhci_sprd_host *sprd_host;
 732         struct mmc_hsq *hsq;
 733         struct clk *clk;
 734         int ret = 0;
 735
 736         host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
 737         if (IS_ERR(host))
 738                 return PTR_ERR(host);
 739
 740         host->dma_mask = DMA_BIT_MASK(64);
 741         pdev->dev.dma_mask = &host->dma_mask;
 742         host->mmc_host_ops.request = sdhci_sprd_request;
 743         host->mmc_host_ops.hs400_enhanced_strobe =
 744                 sdhci_sprd_hs400_enhanced_strobe;
 745         host->mmc_host_ops.prepare_sd_hs_tuning =
 746                 sdhci_sprd_prepare_sd_hs_cmd_tuning;
 747         host->mmc_host_ops.execute_sd_hs_tuning =
 748                 sdhci_sprd_execute_sd_hs_data_tuning;
 749
 750         /*
 751          * We can not use the standard ops to change and detect the voltage
 752          * signal for Spreadtrum SD host controller, since our voltage regulator
 753          * for I/O is fixed in hardware, that means we do not need control
 754          * the standard SD host controller to change the I/O voltage.
 755          */
 756         host->mmc_host_ops.start_signal_voltage_switch =
 757                 sdhci_sprd_voltage_switch;
 758
 759         host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
 760                 MMC_CAP_WAIT_WHILE_BUSY;
 761
 762         ret = mmc_of_parse(host->mmc);
 763         if (ret)
 764                 goto pltfm_free;
 765
 766         if (!mmc_card_is_removable(host->mmc))
 767                 host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic;
 768         else
 769                 host->always_defer_done = true;
 770
 771         sprd_host = TO_SPRD_HOST(host);
 772         sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node);
 773
 774         sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev);
 775         if (!IS_ERR(sprd_host->pinctrl)) {
 776                 sprd_host->pins_uhs =
 777                         pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs");
 778                 if (IS_ERR(sprd_host->pins_uhs)) {
 779                         ret = PTR_ERR(sprd_host->pins_uhs);
 780                         goto pltfm_free;
 781                 }
 782
 783                 sprd_host->pins_default =
 784                         pinctrl_lookup_state(sprd_host->pinctrl, "default");
 785                 if (IS_ERR(sprd_host->pins_default)) {
 786                         ret = PTR_ERR(sprd_host->pins_default);
 787                         goto pltfm_free;
 788                 }
 789         }
 790
 791         clk = devm_clk_get(&pdev->dev, "sdio");
 792         if (IS_ERR(clk)) {
 793                 ret = PTR_ERR(clk);
 794                 goto pltfm_free;
 795         }
 796         sprd_host->clk_sdio = clk;
 797         sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
 798         if (!sprd_host->base_rate)
 799                 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
 800
 801         clk = devm_clk_get(&pdev->dev, "enable");
 802         if (IS_ERR(clk)) {
 803                 ret = PTR_ERR(clk);
 804                 goto pltfm_free;
 805         }
 806         sprd_host->clk_enable = clk;
 807
 808         clk = devm_clk_get(&pdev->dev, "2x_enable");
 809         if (!IS_ERR(clk))
 810                 sprd_host->clk_2x_enable = clk;
 811
 812         ret = clk_prepare_enable(sprd_host->clk_sdio);
 813         if (ret)
 814                 goto pltfm_free;
 815
 816         ret = clk_prepare_enable(sprd_host->clk_enable);
 817         if (ret)
 818                 goto clk_disable;
 819
 820         ret = clk_prepare_enable(sprd_host->clk_2x_enable);
 821         if (ret)
 822                 goto clk_disable2;
 823
 824         sdhci_sprd_init_config(host);
 825         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 826         sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
 827                                SDHCI_VENDOR_VER_SHIFT);
 828
 829         pm_runtime_get_noresume(&pdev->dev);
 830         pm_runtime_set_active(&pdev->dev);
 831         pm_runtime_enable(&pdev->dev);
 832         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
 833         pm_runtime_use_autosuspend(&pdev->dev);
 834         pm_suspend_ignore_children(&pdev->dev, 1);
 835
 836         sdhci_enable_v4_mode(host);
 837
 838         /*
 839          * Supply the existing CAPS, but clear the UHS-I modes. This
 840          * will allow these modes to be specified only by device
 841          * tree properties through mmc_of_parse().
 842          */
 843         sdhci_read_caps(host);
 844         host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
 845                          SDHCI_SUPPORT_DDR50);
 846
 847         ret = mmc_regulator_get_supply(host->mmc);
 848         if (ret)
 849                 goto pm_runtime_disable;
 850
 851         ret = sdhci_setup_host(host);
 852         if (ret)
 853                 goto pm_runtime_disable;
 854
 855         sprd_host->flags = host->flags;
 856
 857         hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
 858         if (!hsq) {
 859                 ret = -ENOMEM;
 860                 goto err_cleanup_host;
 861         }
 862
 863         ret = mmc_hsq_init(hsq, host->mmc);
 864         if (ret)
 865                 goto err_cleanup_host;
 866
 867         ret = __sdhci_add_host(host);
 868         if (ret)
 869                 goto err_cleanup_host;
 870
 871         pm_runtime_mark_last_busy(&pdev->dev);
 872         pm_runtime_put_autosuspend(&pdev->dev);
 873
 874         return 0;
 875
 876 err_cleanup_host:
 877         sdhci_cleanup_host(host);
 878
 879 pm_runtime_disable:
 880         pm_runtime_put_noidle(&pdev->dev);
 881         pm_runtime_disable(&pdev->dev);
 882         pm_runtime_set_suspended(&pdev->dev);
 883
 884         clk_disable_unprepare(sprd_host->clk_2x_enable);
 885
 886 clk_disable2:
 887         clk_disable_unprepare(sprd_host->clk_enable);
 888
 889 clk_disable:
 890         clk_disable_unprepare(sprd_host->clk_sdio);
 891
 892 pltfm_free:
 893         sdhci_pltfm_free(pdev);
 894         return ret;
 895 }
 896
 897 static void sdhci_sprd_remove(struct platform_device *pdev)
 898 {
 899         struct sdhci_host *host = platform_get_drvdata(pdev);
 900         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 901
 902         sdhci_remove_host(host, 0);
 903
 904         clk_disable_unprepare(sprd_host->clk_sdio);
 905         clk_disable_unprepare(sprd_host->clk_enable);
 906         clk_disable_unprepare(sprd_host->clk_2x_enable);
 907
 908         sdhci_pltfm_free(pdev);
 909 }
 910
 911 static const struct of_device_id sdhci_sprd_of_match[] = {
 912         { .compatible = "sprd,sdhci-r11", },
 913         { }
 914 };
 915 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
 916
 917 #ifdef CONFIG_PM
 918 static int sdhci_sprd_runtime_suspend(struct device *dev)
 919 {
 920         struct sdhci_host *host = dev_get_drvdata(dev);
 921         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 922
 923         mmc_hsq_suspend(host->mmc);
 924         sdhci_runtime_suspend_host(host);
 925
 926         clk_disable_unprepare(sprd_host->clk_sdio);
 927         clk_disable_unprepare(sprd_host->clk_enable);
 928         clk_disable_unprepare(sprd_host->clk_2x_enable);
 929
 930         return 0;
 931 }
 932
 933 static int sdhci_sprd_runtime_resume(struct device *dev)
 934 {
 935         struct sdhci_host *host = dev_get_drvdata(dev);
 936         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 937         int ret;
 938
 939         ret = clk_prepare_enable(sprd_host->clk_2x_enable);
 940         if (ret)
 941                 return ret;
 942
 943         ret = clk_prepare_enable(sprd_host->clk_enable);
 944         if (ret)
 945                 goto clk_2x_disable;
 946
 947         ret = clk_prepare_enable(sprd_host->clk_sdio);
 948         if (ret)
 949                 goto clk_disable;
 950
 951         sdhci_runtime_resume_host(host, 1);
 952         mmc_hsq_resume(host->mmc);
 953
 954         return 0;
 955
 956 clk_disable:
 957         clk_disable_unprepare(sprd_host->clk_enable);
 958
 959 clk_2x_disable:
 960         clk_disable_unprepare(sprd_host->clk_2x_enable);
 961
 962         return ret;
 963 }
 964 #endif
 965
 966 static const struct dev_pm_ops sdhci_sprd_pm_ops = {
 967         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 968                                 pm_runtime_force_resume)
 969         SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend,
 970                            sdhci_sprd_runtime_resume, NULL)
 971 };
 972
 973 static struct platform_driver sdhci_sprd_driver = {
 974         .probe = sdhci_sprd_probe,
 975         .remove_new = sdhci_sprd_remove,
 976         .driver = {
 977                 .name = "sdhci_sprd_r11",
 978                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
 979                 .of_match_table = sdhci_sprd_of_match,
 980                 .pm = &sdhci_sprd_pm_ops,
 981         },
 982 };
 983 module_platform_driver(sdhci_sprd_driver);
 984
 985 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
 986 MODULE_LICENSE("GPL v2");
 987 MODULE_ALIAS("platform:sdhci-sprd-r11");