drivers/mmc/host/sdhci-sprd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Secure Digital Host Controller
   4 //
   5 // Copyright (C) 2018 Spreadtrum, Inc.
   6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
   7
   8 #include <linux/delay.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/highmem.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/of_device.h>
  14 #include <linux/of_gpio.h>
  15 #include <linux/pinctrl/consumer.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/slab.h>
  20
  21 #include "sdhci-pltfm.h"
  22 #include "mmc_hsq.h"
  23
  24 /* SDHCI_ARGUMENT2 register high 16bit */
  25 #define SDHCI_SPRD_ARG2_STUFF           GENMASK(31, 16)
  26
  27 #define SDHCI_SPRD_REG_32_DLL_CFG       0x200
  28 #define  SDHCI_SPRD_DLL_ALL_CPST_EN     (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
  29 #define  SDHCI_SPRD_DLL_EN              BIT(21)
  30 #define  SDHCI_SPRD_DLL_SEARCH_MODE     BIT(16)
  31 #define  SDHCI_SPRD_DLL_INIT_COUNT      0xc00
  32 #define  SDHCI_SPRD_DLL_PHASE_INTERNAL  0x3
  33
  34 #define SDHCI_SPRD_REG_32_DLL_DLY       0x204
  35
  36 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET        0x208
  37 #define  SDHCIBSPRD_IT_WR_DLY_INV               BIT(5)
  38 #define  SDHCI_SPRD_BIT_CMD_DLY_INV             BIT(13)
  39 #define  SDHCI_SPRD_BIT_POSRD_DLY_INV           BIT(21)
  40 #define  SDHCI_SPRD_BIT_NEGRD_DLY_INV           BIT(29)
  41
  42 #define SDHCI_SPRD_REG_32_BUSY_POSI             0x250
  43 #define  SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN        BIT(25)
  44 #define  SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN        BIT(24)
  45
  46 #define SDHCI_SPRD_REG_DEBOUNCE         0x28C
  47 #define  SDHCI_SPRD_BIT_DLL_BAK         BIT(0)
  48 #define  SDHCI_SPRD_BIT_DLL_VAL         BIT(1)
  49
  50 #define  SDHCI_SPRD_INT_SIGNAL_MASK     0x1B7F410B
  51
  52 /* SDHCI_HOST_CONTROL2 */
  53 #define  SDHCI_SPRD_CTRL_HS200          0x0005
  54 #define  SDHCI_SPRD_CTRL_HS400          0x0006
  55 #define  SDHCI_SPRD_CTRL_HS400ES        0x0007
  56
  57 /*
  58  * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
  59  * reserved, and only used on Spreadtrum's design, the hardware cannot work
  60  * if this bit is cleared.
  61  * 1 : normal work
  62  * 0 : hardware reset
  63  */
  64 #define  SDHCI_HW_RESET_CARD            BIT(3)
  65
  66 #define SDHCI_SPRD_MAX_CUR              0xFFFFFF
  67 #define SDHCI_SPRD_CLK_MAX_DIV          1023
  68
  69 #define SDHCI_SPRD_CLK_DEF_RATE         26000000
  70 #define SDHCI_SPRD_PHY_DLL_CLK          52000000
  71
  72 struct sdhci_sprd_host {
  73         u32 version;
  74         struct clk *clk_sdio;
  75         struct clk *clk_enable;
  76         struct clk *clk_2x_enable;
  77         struct pinctrl *pinctrl;
  78         struct pinctrl_state *pins_uhs;
  79         struct pinctrl_state *pins_default;
  80         u32 base_rate;
  81         int flags; /* backup of host attribute */
  82         u32 phy_delay[MMC_TIMING_MMC_HS400 + 2];
  83 };
  84
  85 struct sdhci_sprd_phy_cfg {
  86         const char *property;
  87         u8 timing;
  88 };
  89
  90 static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = {
  91         { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
  92         { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
  93         { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
  94         { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
  95         { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
  96         { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
  97         { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, },
  98         { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, },
  99         { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, },
 100 };
 101
 102 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
 103
 104 static void sdhci_sprd_init_config(struct sdhci_host *host)
 105 {
 106         u16 val;
 107
 108         /* set dll backup mode */
 109         val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
 110         val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
 111         sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
 112 }
 113
 114 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
 115 {
 116         if (unlikely(reg == SDHCI_MAX_CURRENT))
 117                 return SDHCI_SPRD_MAX_CUR;
 118
 119         return readl_relaxed(host->ioaddr + reg);
 120 }
 121
 122 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
 123 {
 124         /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
 125         if (unlikely(reg == SDHCI_MAX_CURRENT))
 126                 return;
 127
 128         if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
 129                 val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
 130
 131         writel_relaxed(val, host->ioaddr + reg);
 132 }
 133
 134 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
 135 {
 136         /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
 137         if (unlikely(reg == SDHCI_BLOCK_COUNT))
 138                 return;
 139
 140         writew_relaxed(val, host->ioaddr + reg);
 141 }
 142
 143 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
 144 {
 145         /*
 146          * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
 147          * standard specification, sdhci_reset() write this register directly
 148          * without checking other reserved bits, that will clear BIT(3) which
 149          * is defined as hardware reset on Spreadtrum's platform and clearing
 150          * it by mistake will lead the card not work. So here we need to work
 151          * around it.
 152          */
 153         if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
 154                 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
 155                         val |= SDHCI_HW_RESET_CARD;
 156         }
 157
 158         writeb_relaxed(val, host->ioaddr + reg);
 159 }
 160
 161 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
 162 {
 163         u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 164
 165         ctrl &= ~SDHCI_CLOCK_CARD_EN;
 166         sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
 167 }
 168
 169 static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host)
 170 {
 171         u16 ctrl;
 172
 173         ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 174         ctrl |= SDHCI_CLOCK_CARD_EN;
 175         sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
 176 }
 177
 178 static inline void
 179 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
 180 {
 181         u32 dll_dly_offset;
 182
 183         dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
 184         if (en)
 185                 dll_dly_offset |= mask;
 186         else
 187                 dll_dly_offset &= ~mask;
 188         sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
 189 }
 190
 191 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
 192 {
 193         u32 div;
 194
 195         /* select 2x clock source */
 196         if (base_clk <= clk * 2)
 197                 return 0;
 198
 199         div = (u32) (base_clk / (clk * 2));
 200
 201         if ((base_clk / div) > (clk * 2))
 202                 div++;
 203
 204         if (div > SDHCI_SPRD_CLK_MAX_DIV)
 205                 div = SDHCI_SPRD_CLK_MAX_DIV;
 206
 207         if (div % 2)
 208                 div = (div + 1) / 2;
 209         else
 210                 div = div / 2;
 211
 212         return div;
 213 }
 214
 215 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
 216                                         unsigned int clk)
 217 {
 218         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 219         u32 div, val, mask;
 220
 221         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 222
 223         div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
 224         div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
 225         sdhci_enable_clk(host, div);
 226
 227         val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
 228         mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
 229         /* Enable CLK_AUTO when the clock is greater than 400K. */
 230         if (clk > 400000) {
 231                 if (mask != (val & mask)) {
 232                         val |= mask;
 233                         sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
 234                 }
 235         } else {
 236                 if (val & mask) {
 237                         val &= ~mask;
 238                         sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
 239                 }
 240         }
 241 }
 242
 243 static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host)
 244 {
 245         u32 tmp;
 246
 247         tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
 248         tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN);
 249         sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
 250         /* wait 1ms */
 251         usleep_range(1000, 1250);
 252
 253         tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
 254         tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE |
 255                 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL;
 256         sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
 257         /* wait 1ms */
 258         usleep_range(1000, 1250);
 259
 260         tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
 261         tmp |= SDHCI_SPRD_DLL_EN;
 262         sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
 263         /* wait 1ms */
 264         usleep_range(1000, 1250);
 265 }
 266
 267 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
 268 {
 269         bool en = false, clk_changed = false;
 270
 271         if (clock == 0) {
 272                 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 273         } else if (clock != host->clock) {
 274                 sdhci_sprd_sd_clk_off(host);
 275                 _sdhci_sprd_set_clock(host, clock);
 276
 277                 if (clock <= 400000)
 278                         en = true;
 279                 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
 280                                           SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
 281                 clk_changed = true;
 282         } else {
 283                 _sdhci_sprd_set_clock(host, clock);
 284         }
 285
 286         /*
 287          * According to the Spreadtrum SD host specification, when we changed
 288          * the clock to be more than 52M, we should enable the PHY DLL which
 289          * is used to track the clock frequency to make the clock work more
 290          * stable. Otherwise deviation may occur of the higher clock.
 291          */
 292         if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK)
 293                 sdhci_sprd_enable_phy_dll(host);
 294 }
 295
 296 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
 297 {
 298         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 299
 300         return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
 301 }
 302
 303 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
 304 {
 305         return 100000;
 306 }
 307
 308 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
 309                                          unsigned int timing)
 310 {
 311         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 312         struct mmc_host *mmc = host->mmc;
 313         u32 *p = sprd_host->phy_delay;
 314         u16 ctrl_2;
 315
 316         if (timing == host->timing)
 317                 return;
 318
 319         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 320         /* Select Bus Speed Mode for host */
 321         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 322         switch (timing) {
 323         case MMC_TIMING_UHS_SDR12:
 324                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 325                 break;
 326         case MMC_TIMING_MMC_HS:
 327         case MMC_TIMING_SD_HS:
 328         case MMC_TIMING_UHS_SDR25:
 329                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 330                 break;
 331         case MMC_TIMING_UHS_SDR50:
 332                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 333                 break;
 334         case MMC_TIMING_UHS_SDR104:
 335                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 336                 break;
 337         case MMC_TIMING_UHS_DDR50:
 338         case MMC_TIMING_MMC_DDR52:
 339                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 340                 break;
 341         case MMC_TIMING_MMC_HS200:
 342                 ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
 343                 break;
 344         case MMC_TIMING_MMC_HS400:
 345                 ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
 346                 break;
 347         default:
 348                 break;
 349         }
 350
 351         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 352
 353         if (!mmc->ios.enhanced_strobe)
 354                 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
 355 }
 356
 357 static void sdhci_sprd_hw_reset(struct sdhci_host *host)
 358 {
 359         int val;
 360
 361         /*
 362          * Note: don't use sdhci_writeb() API here since it is redirected to
 363          * sdhci_sprd_writeb() in which we have a workaround for
 364          * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
 365          * not be cleared.
 366          */
 367         val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
 368         val &= ~SDHCI_HW_RESET_CARD;
 369         writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
 370         /* wait for 10 us */
 371         usleep_range(10, 20);
 372
 373         val |= SDHCI_HW_RESET_CARD;
 374         writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
 375         usleep_range(300, 500);
 376 }
 377
 378 static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
 379 {
 380         /* The Spredtrum controller actual maximum timeout count is 1 << 31 */
 381         return 1 << 31;
 382 }
 383
 384 static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host)
 385 {
 386         return 0;
 387 }
 388
 389 static void sdhci_sprd_request_done(struct sdhci_host *host,
 390                                     struct mmc_request *mrq)
 391 {
 392         /* Validate if the request was from software queue firstly. */
 393         if (mmc_hsq_finalize_request(host->mmc, mrq))
 394                 return;
 395
 396         mmc_request_done(host->mmc, mrq);
 397 }
 398
 399 static void sdhci_sprd_set_power(struct sdhci_host *host, unsigned char mode,
 400                                  unsigned short vdd)
 401 {
 402         struct mmc_host *mmc = host->mmc;
 403
 404         switch (mode) {
 405         case MMC_POWER_OFF:
 406                 mmc_regulator_set_ocr(host->mmc, mmc->supply.vmmc, 0);
 407
 408                 mmc_regulator_disable_vqmmc(mmc);
 409                 break;
 410         case MMC_POWER_ON:
 411                 mmc_regulator_enable_vqmmc(mmc);
 412                 break;
 413         case MMC_POWER_UP:
 414                 mmc_regulator_set_ocr(host->mmc, mmc->supply.vmmc, vdd);
 415                 break;
 416         }
 417 }
 418
 419 static struct sdhci_ops sdhci_sprd_ops = {
 420         .read_l = sdhci_sprd_readl,
 421         .write_l = sdhci_sprd_writel,
 422         .write_w = sdhci_sprd_writew,
 423         .write_b = sdhci_sprd_writeb,
 424         .set_clock = sdhci_sprd_set_clock,
 425         .set_power = sdhci_sprd_set_power,
 426         .get_max_clock = sdhci_sprd_get_max_clock,
 427         .get_min_clock = sdhci_sprd_get_min_clock,
 428         .set_bus_width = sdhci_set_bus_width,
 429         .reset = sdhci_reset,
 430         .set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
 431         .hw_reset = sdhci_sprd_hw_reset,
 432         .get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
 433         .get_ro = sdhci_sprd_get_ro,
 434         .request_done = sdhci_sprd_request_done,
 435 };
 436
 437 static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc,
 438                                         struct mmc_request *mrq)
 439 {
 440         struct sdhci_host *host = mmc_priv(mmc);
 441         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 442
 443         host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
 444
 445         /*
 446          * From version 4.10 onward, ARGUMENT2 register is also as 32-bit
 447          * block count register which doesn't support stuff bits of
 448          * CMD23 argument on Spreadtrum's sd host controller.
 449          */
 450         if (host->version >= SDHCI_SPEC_410 &&
 451             mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
 452             (host->flags & SDHCI_AUTO_CMD23))
 453                 host->flags &= ~SDHCI_AUTO_CMD23;
 454 }
 455
 456 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
 457 {
 458         sdhci_sprd_check_auto_cmd23(mmc, mrq);
 459
 460         sdhci_request(mmc, mrq);
 461 }
 462
 463 static int sdhci_sprd_request_atomic(struct mmc_host *mmc,
 464                                      struct mmc_request *mrq)
 465 {
 466         sdhci_sprd_check_auto_cmd23(mmc, mrq);
 467
 468         return sdhci_request_atomic(mmc, mrq);
 469 }
 470
 471 static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
 472 {
 473         struct sdhci_host *host = mmc_priv(mmc);
 474         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 475         int ret;
 476
 477         if (!IS_ERR(mmc->supply.vqmmc)) {
 478                 ret = mmc_regulator_set_vqmmc(mmc, ios);
 479                 if (ret < 0) {
 480                         pr_err("%s: Switching signalling voltage failed\n",
 481                                mmc_hostname(mmc));
 482                         return ret;
 483                 }
 484         }
 485
 486         if (IS_ERR(sprd_host->pinctrl))
 487                 goto reset;
 488
 489         switch (ios->signal_voltage) {
 490         case MMC_SIGNAL_VOLTAGE_180:
 491                 ret = pinctrl_select_state(sprd_host->pinctrl,
 492                                            sprd_host->pins_uhs);
 493                 if (ret) {
 494                         pr_err("%s: failed to select uhs pin state\n",
 495                                mmc_hostname(mmc));
 496                         return ret;
 497                 }
 498                 break;
 499
 500         default:
 501                 fallthrough;
 502         case MMC_SIGNAL_VOLTAGE_330:
 503                 ret = pinctrl_select_state(sprd_host->pinctrl,
 504                                            sprd_host->pins_default);
 505                 if (ret) {
 506                         pr_err("%s: failed to select default pin state\n",
 507                                mmc_hostname(mmc));
 508                         return ret;
 509                 }
 510                 break;
 511         }
 512
 513         /* Wait for 300 ~ 500 us for pin state stable */
 514         usleep_range(300, 500);
 515
 516 reset:
 517         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 518
 519         return 0;
 520 }
 521
 522 static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc,
 523                                              struct mmc_ios *ios)
 524 {
 525         struct sdhci_host *host = mmc_priv(mmc);
 526         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 527         u32 *p = sprd_host->phy_delay;
 528         u16 ctrl_2;
 529
 530         if (!ios->enhanced_strobe)
 531                 return;
 532
 533         sdhci_sprd_sd_clk_off(host);
 534
 535         /* Set HS400 enhanced strobe mode */
 536         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 537         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 538         ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES;
 539         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 540
 541         sdhci_sprd_sd_clk_on(host);
 542
 543         /* Set the PHY DLL delay value for HS400 enhanced strobe mode */
 544         sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1],
 545                      SDHCI_SPRD_REG_32_DLL_DLY);
 546 }
 547
 548 static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
 549                                        struct device_node *np)
 550 {
 551         u32 *p = sprd_host->phy_delay;
 552         int ret, i, index;
 553         u32 val[4];
 554
 555         for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) {
 556                 ret = of_property_read_u32_array(np,
 557                                 sdhci_sprd_phy_cfgs[i].property, val, 4);
 558                 if (ret)
 559                         continue;
 560
 561                 index = sdhci_sprd_phy_cfgs[i].timing;
 562                 p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24);
 563         }
 564 }
 565
 566 static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
 567         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 568                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 569                   SDHCI_QUIRK_MISSING_CAPS,
 570         .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
 571                    SDHCI_QUIRK2_USE_32BIT_BLK_CNT |
 572                    SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 573         .ops = &sdhci_sprd_ops,
 574 };
 575
 576 static int sdhci_sprd_probe(struct platform_device *pdev)
 577 {
 578         struct sdhci_host *host;
 579         struct sdhci_sprd_host *sprd_host;
 580         struct mmc_hsq *hsq;
 581         struct clk *clk;
 582         int ret = 0;
 583
 584         host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
 585         if (IS_ERR(host))
 586                 return PTR_ERR(host);
 587
 588         host->dma_mask = DMA_BIT_MASK(64);
 589         pdev->dev.dma_mask = &host->dma_mask;
 590         host->mmc_host_ops.request = sdhci_sprd_request;
 591         host->mmc_host_ops.hs400_enhanced_strobe =
 592                 sdhci_sprd_hs400_enhanced_strobe;
 593         /*
 594          * We can not use the standard ops to change and detect the voltage
 595          * signal for Spreadtrum SD host controller, since our voltage regulator
 596          * for I/O is fixed in hardware, that means we do not need control
 597          * the standard SD host controller to change the I/O voltage.
 598          */
 599         host->mmc_host_ops.start_signal_voltage_switch =
 600                 sdhci_sprd_voltage_switch;
 601
 602         host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
 603                 MMC_CAP_WAIT_WHILE_BUSY;
 604
 605         ret = mmc_of_parse(host->mmc);
 606         if (ret)
 607                 goto pltfm_free;
 608
 609         if (!mmc_card_is_removable(host->mmc))
 610                 host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic;
 611         else
 612                 host->always_defer_done = true;
 613
 614         sprd_host = TO_SPRD_HOST(host);
 615         sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node);
 616
 617         sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev);
 618         if (!IS_ERR(sprd_host->pinctrl)) {
 619                 sprd_host->pins_uhs =
 620                         pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs");
 621                 if (IS_ERR(sprd_host->pins_uhs)) {
 622                         ret = PTR_ERR(sprd_host->pins_uhs);
 623                         goto pltfm_free;
 624                 }
 625
 626                 sprd_host->pins_default =
 627                         pinctrl_lookup_state(sprd_host->pinctrl, "default");
 628                 if (IS_ERR(sprd_host->pins_default)) {
 629                         ret = PTR_ERR(sprd_host->pins_default);
 630                         goto pltfm_free;
 631                 }
 632         }
 633
 634         clk = devm_clk_get(&pdev->dev, "sdio");
 635         if (IS_ERR(clk)) {
 636                 ret = PTR_ERR(clk);
 637                 goto pltfm_free;
 638         }
 639         sprd_host->clk_sdio = clk;
 640         sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
 641         if (!sprd_host->base_rate)
 642                 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
 643
 644         clk = devm_clk_get(&pdev->dev, "enable");
 645         if (IS_ERR(clk)) {
 646                 ret = PTR_ERR(clk);
 647                 goto pltfm_free;
 648         }
 649         sprd_host->clk_enable = clk;
 650
 651         clk = devm_clk_get(&pdev->dev, "2x_enable");
 652         if (!IS_ERR(clk))
 653                 sprd_host->clk_2x_enable = clk;
 654
 655         ret = clk_prepare_enable(sprd_host->clk_sdio);
 656         if (ret)
 657                 goto pltfm_free;
 658
 659         ret = clk_prepare_enable(sprd_host->clk_enable);
 660         if (ret)
 661                 goto clk_disable;
 662
 663         ret = clk_prepare_enable(sprd_host->clk_2x_enable);
 664         if (ret)
 665                 goto clk_disable2;
 666
 667         sdhci_sprd_init_config(host);
 668         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 669         sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
 670                                SDHCI_VENDOR_VER_SHIFT);
 671
 672         pm_runtime_get_noresume(&pdev->dev);
 673         pm_runtime_set_active(&pdev->dev);
 674         pm_runtime_enable(&pdev->dev);
 675         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
 676         pm_runtime_use_autosuspend(&pdev->dev);
 677         pm_suspend_ignore_children(&pdev->dev, 1);
 678
 679         sdhci_enable_v4_mode(host);
 680
 681         /*
 682          * Supply the existing CAPS, but clear the UHS-I modes. This
 683          * will allow these modes to be specified only by device
 684          * tree properties through mmc_of_parse().
 685          */
 686         host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 687         host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 688         host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
 689                          SDHCI_SUPPORT_DDR50);
 690
 691         ret = mmc_regulator_get_supply(host->mmc);
 692         if (ret)
 693                 goto pm_runtime_disable;
 694
 695         ret = sdhci_setup_host(host);
 696         if (ret)
 697                 goto pm_runtime_disable;
 698
 699         sprd_host->flags = host->flags;
 700
 701         hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
 702         if (!hsq) {
 703                 ret = -ENOMEM;
 704                 goto err_cleanup_host;
 705         }
 706
 707         ret = mmc_hsq_init(hsq, host->mmc);
 708         if (ret)
 709                 goto err_cleanup_host;
 710
 711         ret = __sdhci_add_host(host);
 712         if (ret)
 713                 goto err_cleanup_host;
 714
 715         pm_runtime_mark_last_busy(&pdev->dev);
 716         pm_runtime_put_autosuspend(&pdev->dev);
 717
 718         return 0;
 719
 720 err_cleanup_host:
 721         sdhci_cleanup_host(host);
 722
 723 pm_runtime_disable:
 724         pm_runtime_put_noidle(&pdev->dev);
 725         pm_runtime_disable(&pdev->dev);
 726         pm_runtime_set_suspended(&pdev->dev);
 727
 728         clk_disable_unprepare(sprd_host->clk_2x_enable);
 729
 730 clk_disable2:
 731         clk_disable_unprepare(sprd_host->clk_enable);
 732
 733 clk_disable:
 734         clk_disable_unprepare(sprd_host->clk_sdio);
 735
 736 pltfm_free:
 737         sdhci_pltfm_free(pdev);
 738         return ret;
 739 }
 740
 741 static int sdhci_sprd_remove(struct platform_device *pdev)
 742 {
 743         struct sdhci_host *host = platform_get_drvdata(pdev);
 744         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 745
 746         sdhci_remove_host(host, 0);
 747
 748         clk_disable_unprepare(sprd_host->clk_sdio);
 749         clk_disable_unprepare(sprd_host->clk_enable);
 750         clk_disable_unprepare(sprd_host->clk_2x_enable);
 751
 752         sdhci_pltfm_free(pdev);
 753
 754         return 0;
 755 }
 756
 757 static const struct of_device_id sdhci_sprd_of_match[] = {
 758         { .compatible = "sprd,sdhci-r11", },
 759         { }
 760 };
 761 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
 762
 763 #ifdef CONFIG_PM
 764 static int sdhci_sprd_runtime_suspend(struct device *dev)
 765 {
 766         struct sdhci_host *host = dev_get_drvdata(dev);
 767         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 768
 769         mmc_hsq_suspend(host->mmc);
 770         sdhci_runtime_suspend_host(host);
 771
 772         clk_disable_unprepare(sprd_host->clk_sdio);
 773         clk_disable_unprepare(sprd_host->clk_enable);
 774         clk_disable_unprepare(sprd_host->clk_2x_enable);
 775
 776         return 0;
 777 }
 778
 779 static int sdhci_sprd_runtime_resume(struct device *dev)
 780 {
 781         struct sdhci_host *host = dev_get_drvdata(dev);
 782         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 783         int ret;
 784
 785         ret = clk_prepare_enable(sprd_host->clk_2x_enable);
 786         if (ret)
 787                 return ret;
 788
 789         ret = clk_prepare_enable(sprd_host->clk_enable);
 790         if (ret)
 791                 goto clk_2x_disable;
 792
 793         ret = clk_prepare_enable(sprd_host->clk_sdio);
 794         if (ret)
 795                 goto clk_disable;
 796
 797         sdhci_runtime_resume_host(host, 1);
 798         mmc_hsq_resume(host->mmc);
 799
 800         return 0;
 801
 802 clk_disable:
 803         clk_disable_unprepare(sprd_host->clk_enable);
 804
 805 clk_2x_disable:
 806         clk_disable_unprepare(sprd_host->clk_2x_enable);
 807
 808         return ret;
 809 }
 810 #endif
 811
 812 static const struct dev_pm_ops sdhci_sprd_pm_ops = {
 813         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 814                                 pm_runtime_force_resume)
 815         SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend,
 816                            sdhci_sprd_runtime_resume, NULL)
 817 };
 818
 819 static struct platform_driver sdhci_sprd_driver = {
 820         .probe = sdhci_sprd_probe,
 821         .remove = sdhci_sprd_remove,
 822         .driver = {
 823                 .name = "sdhci_sprd_r11",
 824                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
 825                 .of_match_table = of_match_ptr(sdhci_sprd_of_match),
 826                 .pm = &sdhci_sprd_pm_ops,
 827         },
 828 };
 829 module_platform_driver(sdhci_sprd_driver);
 830
 831 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
 832 MODULE_LICENSE("GPL v2");
 833 MODULE_ALIAS("platform:sdhci-sprd-r11");