drivers/mmc/host/sdhci-pci-o2micro.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 BayHub Technology Ltd.
   4  *
   5  * Authors: Peter Guo <peter.guo@bayhubtech.com>
   6  *          Adam Lee <adam.lee@canonical.com>
   7  *          Ernest Zhang <ernest.zhang@bayhubtech.com>
   8  */
   9
  10 #include <linux/pci.h>
  11 #include <linux/mmc/host.h>
  12 #include <linux/mmc/mmc.h>
  13 #include <linux/delay.h>
  14 #include <linux/iopoll.h>
  15
  16 #include "sdhci.h"
  17 #include "sdhci-pci.h"
  18
  19 /*
  20  * O2Micro device registers
  21  */
  22
  23 #define O2_SD_MISC_REG5         0x64
  24 #define O2_SD_LD0_CTRL          0x68
  25 #define O2_SD_DEV_CTRL          0x88
  26 #define O2_SD_LOCK_WP           0xD3
  27 #define O2_SD_TEST_REG          0xD4
  28 #define O2_SD_FUNC_REG0         0xDC
  29 #define O2_SD_MULTI_VCC3V       0xEE
  30 #define O2_SD_CLKREQ            0xEC
  31 #define O2_SD_CAPS              0xE0
  32 #define O2_SD_ADMA1             0xE2
  33 #define O2_SD_ADMA2             0xE7
  34 #define O2_SD_MISC_CTRL2        0xF0
  35 #define O2_SD_INF_MOD           0xF1
  36 #define O2_SD_MISC_CTRL4        0xFC
  37 #define O2_SD_MISC_CTRL         0x1C0
  38 #define O2_SD_PWR_FORCE_L0      0x0002
  39 #define O2_SD_TUNING_CTRL       0x300
  40 #define O2_SD_PLL_SETTING       0x304
  41 #define O2_SD_MISC_SETTING      0x308
  42 #define O2_SD_CLK_SETTING       0x328
  43 #define O2_SD_CAP_REG2          0x330
  44 #define O2_SD_CAP_REG0          0x334
  45 #define O2_SD_UHS1_CAP_SETTING  0x33C
  46 #define O2_SD_DELAY_CTRL        0x350
  47 #define O2_SD_UHS2_L1_CTRL      0x35C
  48 #define O2_SD_FUNC_REG3         0x3E0
  49 #define O2_SD_FUNC_REG4         0x3E4
  50 #define O2_SD_LED_ENABLE        BIT(6)
  51 #define O2_SD_FREG0_LEDOFF      BIT(13)
  52 #define O2_SD_FREG4_ENABLE_CLK_SET      BIT(22)
  53
  54 #define O2_SD_VENDOR_SETTING    0x110
  55 #define O2_SD_VENDOR_SETTING2   0x1C8
  56 #define O2_SD_HW_TUNING_DISABLE BIT(4)
  57
  58 #define O2_PLL_DLL_WDT_CONTROL1 0x1CC
  59 #define  O2_PLL_FORCE_ACTIVE    BIT(18)
  60 #define  O2_PLL_LOCK_STATUS     BIT(14)
  61 #define  O2_PLL_SOFT_RESET      BIT(12)
  62 #define  O2_DLL_LOCK_STATUS     BIT(11)
  63
  64 #define O2_SD_DETECT_SETTING 0x324
  65
  66 static const u32 dmdn_table[] = {0x2B1C0000,
  67         0x2C1A0000, 0x371B0000, 0x35100000};
  68 #define DMDN_SZ ARRAY_SIZE(dmdn_table)
  69
  70 struct o2_host {
  71         u8 dll_adjust_count;
  72 };
  73
  74 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
  75 {
  76         ktime_t timeout;
  77         u32 scratch32;
  78
  79         /* Wait max 50 ms */
  80         timeout = ktime_add_ms(ktime_get(), 50);
  81         while (1) {
  82                 bool timedout = ktime_after(ktime_get(), timeout);
  83
  84                 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
  85                 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
  86                     == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
  87                         break;
  88
  89                 if (timedout) {
  90                         pr_err("%s: Card Detect debounce never finished.\n",
  91                                mmc_hostname(host->mmc));
  92                         sdhci_dumpregs(host);
  93                         return;
  94                 }
  95                 udelay(10);
  96         }
  97 }
  98
  99 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
 100 {
 101         ktime_t timeout;
 102         u16 scratch;
 103         u32 scratch32;
 104
 105         /* PLL software reset */
 106         scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
 107         scratch32 |= O2_PLL_SOFT_RESET;
 108         sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
 109         udelay(1);
 110         scratch32 &= ~(O2_PLL_SOFT_RESET);
 111         sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
 112
 113         /* PLL force active */
 114         scratch32 |= O2_PLL_FORCE_ACTIVE;
 115         sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
 116
 117         /* Wait max 20 ms */
 118         timeout = ktime_add_ms(ktime_get(), 20);
 119         while (1) {
 120                 bool timedout = ktime_after(ktime_get(), timeout);
 121
 122                 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
 123                 if (scratch & O2_PLL_LOCK_STATUS)
 124                         break;
 125                 if (timedout) {
 126                         pr_err("%s: Internal clock never stabilised.\n",
 127                                mmc_hostname(host->mmc));
 128                         sdhci_dumpregs(host);
 129                         goto out;
 130                 }
 131                 udelay(10);
 132         }
 133
 134         /* Wait for card detect finish */
 135         udelay(1);
 136         sdhci_o2_wait_card_detect_stable(host);
 137
 138 out:
 139         /* Cancel PLL force active */
 140         scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
 141         scratch32 &= ~O2_PLL_FORCE_ACTIVE;
 142         sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
 143 }
 144
 145 static int sdhci_o2_get_cd(struct mmc_host *mmc)
 146 {
 147         struct sdhci_host *host = mmc_priv(mmc);
 148
 149         if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
 150                 sdhci_o2_enable_internal_clock(host);
 151         else
 152                 sdhci_o2_wait_card_detect_stable(host);
 153
 154         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
 155 }
 156
 157 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
 158 {
 159         u32 scratch_32;
 160
 161         pci_read_config_dword(chip->pdev,
 162                               O2_SD_PLL_SETTING, &scratch_32);
 163
 164         scratch_32 &= 0x0000FFFF;
 165         scratch_32 |= value;
 166
 167         pci_write_config_dword(chip->pdev,
 168                                O2_SD_PLL_SETTING, scratch_32);
 169 }
 170
 171 static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
 172 {
 173         return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
 174 }
 175
 176 /*
 177  * This function is used to detect dll lock status.
 178  * Since the dll lock status bit will toggle randomly
 179  * with very short interval which needs to be polled
 180  * as fast as possible. Set sleep_us as 1 microsecond.
 181  */
 182 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
 183 {
 184         u32     scratch32 = 0;
 185
 186         return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
 187                 scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
 188 }
 189
 190 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
 191 {
 192         u16 reg;
 193
 194         /* enable hardware tuning */
 195         reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
 196         reg &= ~O2_SD_HW_TUNING_DISABLE;
 197         sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
 198 }
 199
 200 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
 201 {
 202         int i;
 203
 204         sdhci_send_tuning(host, opcode);
 205
 206         for (i = 0; i < 150; i++) {
 207                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 208
 209                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
 210                         if (ctrl & SDHCI_CTRL_TUNED_CLK) {
 211                                 host->tuning_done = true;
 212                                 return;
 213                         }
 214                         pr_warn("%s: HW tuning failed !\n",
 215                                 mmc_hostname(host->mmc));
 216                         break;
 217                 }
 218
 219                 mdelay(1);
 220         }
 221
 222         pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
 223                 mmc_hostname(host->mmc));
 224         sdhci_reset_tuning(host);
 225 }
 226
 227 /*
 228  * This function is used to fix o2 dll shift issue.
 229  * It isn't necessary to detect card present before recovery.
 230  * Firstly, it is used by bht emmc card, which is embedded.
 231  * Second, before call recovery card present will be detected
 232  * outside of the execute tuning function.
 233  */
 234 static int sdhci_o2_dll_recovery(struct sdhci_host *host)
 235 {
 236         int ret = 0;
 237         u8 scratch_8 = 0;
 238         u32 scratch_32 = 0;
 239         struct sdhci_pci_slot *slot = sdhci_priv(host);
 240         struct sdhci_pci_chip *chip = slot->chip;
 241         struct o2_host *o2_host = sdhci_pci_priv(slot);
 242
 243         /* UnLock WP */
 244         pci_read_config_byte(chip->pdev,
 245                         O2_SD_LOCK_WP, &scratch_8);
 246         scratch_8 &= 0x7f;
 247         pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
 248         while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
 249                 /* Disable clock */
 250                 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
 251
 252                 /* PLL software reset */
 253                 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
 254                 scratch_32 |= O2_PLL_SOFT_RESET;
 255                 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
 256
 257                 pci_read_config_dword(chip->pdev,
 258                                             O2_SD_FUNC_REG4,
 259                                             &scratch_32);
 260                 /* Enable Base Clk setting change */
 261                 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
 262                 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
 263                 o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
 264
 265                 /* Enable internal clock */
 266                 scratch_8 = SDHCI_CLOCK_INT_EN;
 267                 sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
 268
 269                 if (sdhci_o2_get_cd(host->mmc)) {
 270                         /*
 271                          * need wait at least 5ms for dll status stable,
 272                          * after enable internal clock
 273                          */
 274                         usleep_range(5000, 6000);
 275                         if (sdhci_o2_wait_dll_detect_lock(host)) {
 276                                 scratch_8 |= SDHCI_CLOCK_CARD_EN;
 277                                 sdhci_writeb(host, scratch_8,
 278                                         SDHCI_CLOCK_CONTROL);
 279                                 ret = 1;
 280                         } else {
 281                                 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
 282                                         mmc_hostname(host->mmc),
 283                                         o2_host->dll_adjust_count);
 284                         }
 285                 } else {
 286                         pr_err("%s: card present detect failed.\n",
 287                                 mmc_hostname(host->mmc));
 288                         break;
 289                 }
 290
 291                 o2_host->dll_adjust_count++;
 292         }
 293         if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
 294                 pr_err("%s: DLL adjust over max times\n",
 295                 mmc_hostname(host->mmc));
 296         /* Lock WP */
 297         pci_read_config_byte(chip->pdev,
 298                                    O2_SD_LOCK_WP, &scratch_8);
 299         scratch_8 |= 0x80;
 300         pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
 301         return ret;
 302 }
 303
 304 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
 305 {
 306         struct sdhci_host *host = mmc_priv(mmc);
 307         int current_bus_width = 0;
 308         u32 scratch32 = 0;
 309         u16 scratch = 0;
 310
 311         /*
 312          * This handler only implements the eMMC tuning that is specific to
 313          * this controller.  Fall back to the standard method for other TIMING.
 314          */
 315         if ((host->timing != MMC_TIMING_MMC_HS200) &&
 316                 (host->timing != MMC_TIMING_UHS_SDR104))
 317                 return sdhci_execute_tuning(mmc, opcode);
 318
 319         if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) &&
 320                         (opcode != MMC_SEND_TUNING_BLOCK)))
 321                 return -EINVAL;
 322
 323         /* Force power mode enter L0 */
 324         scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
 325         scratch |= O2_SD_PWR_FORCE_L0;
 326         sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
 327
 328         /* wait DLL lock, timeout value 5ms */
 329         if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
 330                 scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000))
 331                 pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n",
 332                                 mmc_hostname(host->mmc));
 333         /*
 334          * Judge the tuning reason, whether caused by dll shift
 335          * If cause by dll shift, should call sdhci_o2_dll_recovery
 336          */
 337         if (!sdhci_o2_wait_dll_detect_lock(host))
 338                 if (!sdhci_o2_dll_recovery(host)) {
 339                         pr_err("%s: o2 dll recovery failed\n",
 340                                 mmc_hostname(host->mmc));
 341                         return -EINVAL;
 342                 }
 343         /*
 344          * o2 sdhci host didn't support 8bit emmc tuning
 345          */
 346         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
 347                 current_bus_width = mmc->ios.bus_width;
 348                 mmc->ios.bus_width = MMC_BUS_WIDTH_4;
 349                 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
 350         }
 351
 352         sdhci_o2_set_tuning_mode(host);
 353
 354         sdhci_start_tuning(host);
 355
 356         __sdhci_o2_execute_tuning(host, opcode);
 357
 358         sdhci_end_tuning(host);
 359
 360         if (current_bus_width == MMC_BUS_WIDTH_8) {
 361                 mmc->ios.bus_width = MMC_BUS_WIDTH_8;
 362                 sdhci_set_bus_width(host, current_bus_width);
 363         }
 364
 365         /* Cancel force power mode enter L0 */
 366         scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
 367         scratch &= ~(O2_SD_PWR_FORCE_L0);
 368         sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
 369
 370         sdhci_reset(host, SDHCI_RESET_CMD);
 371         sdhci_reset(host, SDHCI_RESET_DATA);
 372
 373         host->flags &= ~SDHCI_HS400_TUNING;
 374         return 0;
 375 }
 376
 377 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
 378 {
 379         int ret;
 380         u32 scratch_32;
 381
 382         /* Set led of SD host function enable */
 383         ret = pci_read_config_dword(chip->pdev,
 384                                     O2_SD_FUNC_REG0, &scratch_32);
 385         if (ret)
 386                 return;
 387
 388         scratch_32 &= ~O2_SD_FREG0_LEDOFF;
 389         pci_write_config_dword(chip->pdev,
 390                                O2_SD_FUNC_REG0, scratch_32);
 391
 392         ret = pci_read_config_dword(chip->pdev,
 393                                     O2_SD_TEST_REG, &scratch_32);
 394         if (ret)
 395                 return;
 396
 397         scratch_32 |= O2_SD_LED_ENABLE;
 398         pci_write_config_dword(chip->pdev,
 399                                O2_SD_TEST_REG, scratch_32);
 400 }
 401
 402 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
 403 {
 404         u32 scratch_32;
 405         int ret;
 406         /* Improve write performance for SD3.0 */
 407         ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
 408         if (ret)
 409                 return;
 410         scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
 411         pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
 412
 413         /* Enable Link abnormal reset generating Reset */
 414         ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
 415         if (ret)
 416                 return;
 417         scratch_32 &= ~((1 << 19) | (1 << 11));
 418         scratch_32 |= (1 << 10);
 419         pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
 420
 421         /* set card power over current protection */
 422         ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
 423         if (ret)
 424                 return;
 425         scratch_32 |= (1 << 4);
 426         pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
 427
 428         /* adjust the output delay for SD mode */
 429         pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
 430
 431         /* Set the output voltage setting of Aux 1.2v LDO */
 432         ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
 433         if (ret)
 434                 return;
 435         scratch_32 &= ~(3 << 12);
 436         pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
 437
 438         /* Set Max power supply capability of SD host */
 439         ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
 440         if (ret)
 441                 return;
 442         scratch_32 &= ~(0x01FE);
 443         scratch_32 |= 0x00CC;
 444         pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
 445         /* Set DLL Tuning Window */
 446         ret = pci_read_config_dword(chip->pdev,
 447                                     O2_SD_TUNING_CTRL, &scratch_32);
 448         if (ret)
 449                 return;
 450         scratch_32 &= ~(0x000000FF);
 451         scratch_32 |= 0x00000066;
 452         pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
 453
 454         /* Set UHS2 T_EIDLE */
 455         ret = pci_read_config_dword(chip->pdev,
 456                                     O2_SD_UHS2_L1_CTRL, &scratch_32);
 457         if (ret)
 458                 return;
 459         scratch_32 &= ~(0x000000FC);
 460         scratch_32 |= 0x00000084;
 461         pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
 462
 463         /* Set UHS2 Termination */
 464         ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
 465         if (ret)
 466                 return;
 467         scratch_32 &= ~((1 << 21) | (1 << 30));
 468
 469         pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
 470
 471         /* Set L1 Entrance Timer */
 472         ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
 473         if (ret)
 474                 return;
 475         scratch_32 &= ~(0xf0000000);
 476         scratch_32 |= 0x30000000;
 477         pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
 478
 479         ret = pci_read_config_dword(chip->pdev,
 480                                     O2_SD_MISC_CTRL4, &scratch_32);
 481         if (ret)
 482                 return;
 483         scratch_32 &= ~(0x000f0000);
 484         scratch_32 |= 0x00080000;
 485         pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
 486 }
 487
 488 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
 489                                     struct sdhci_host *host)
 490 {
 491         int ret;
 492
 493         ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
 494         if (!ret) {
 495                 pr_info("%s: unsupport msi, use INTx irq\n",
 496                         mmc_hostname(host->mmc));
 497                 return;
 498         }
 499
 500         ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
 501                                     PCI_IRQ_MSI | PCI_IRQ_MSIX);
 502         if (ret < 0) {
 503                 pr_err("%s: enable PCI MSI failed, err=%d\n",
 504                        mmc_hostname(host->mmc), ret);
 505                 return;
 506         }
 507
 508         host->irq = pci_irq_vector(chip->pdev, 0);
 509 }
 510
 511 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
 512 {
 513         /* Enable internal clock */
 514         clk |= SDHCI_CLOCK_INT_EN;
 515         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 516
 517         sdhci_o2_enable_internal_clock(host);
 518         if (sdhci_o2_get_cd(host->mmc)) {
 519                 clk |= SDHCI_CLOCK_CARD_EN;
 520                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 521         }
 522 }
 523
 524 static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
 525 {
 526         u16 clk;
 527         u8 scratch;
 528         u32 scratch_32;
 529         struct sdhci_pci_slot *slot = sdhci_priv(host);
 530         struct sdhci_pci_chip *chip = slot->chip;
 531
 532         host->mmc->actual_clock = 0;
 533
 534         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 535
 536         if (clock == 0)
 537                 return;
 538
 539         if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
 540                 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
 541
 542                 scratch &= 0x7f;
 543                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 544
 545                 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
 546
 547                 if ((scratch_32 & 0xFFFF0000) != 0x2c280000)
 548                         o2_pci_set_baseclk(chip, 0x2c280000);
 549
 550                 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
 551
 552                 scratch |= 0x80;
 553                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 554         }
 555
 556         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
 557         sdhci_o2_enable_clk(host, clk);
 558 }
 559
 560 static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
 561 {
 562         struct sdhci_pci_chip *chip;
 563         struct sdhci_host *host;
 564         struct o2_host *o2_host = sdhci_pci_priv(slot);
 565         u32 reg, caps;
 566         int ret;
 567
 568         chip = slot->chip;
 569         host = slot->host;
 570
 571         o2_host->dll_adjust_count = 0;
 572         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 573
 574         /*
 575          * mmc_select_bus_width() will test the bus to determine the actual bus
 576          * width.
 577          */
 578         if (caps & SDHCI_CAN_DO_8BIT)
 579                 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 580
 581         switch (chip->pdev->device) {
 582         case PCI_DEVICE_ID_O2_SDS0:
 583         case PCI_DEVICE_ID_O2_SEABIRD0:
 584         case PCI_DEVICE_ID_O2_SEABIRD1:
 585         case PCI_DEVICE_ID_O2_SDS1:
 586         case PCI_DEVICE_ID_O2_FUJIN2:
 587                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
 588                 if (reg & 0x1)
 589                         host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
 590
 591                 sdhci_pci_o2_enable_msi(chip, host);
 592
 593                 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
 594                         ret = pci_read_config_dword(chip->pdev,
 595                                                     O2_SD_MISC_SETTING, &reg);
 596                         if (ret)
 597                                 return -EIO;
 598                         if (reg & (1 << 4)) {
 599                                 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
 600                                         mmc_hostname(host->mmc));
 601                                 host->flags &= ~SDHCI_SIGNALING_330;
 602                                 host->flags |= SDHCI_SIGNALING_180;
 603                                 host->mmc->caps2 |= MMC_CAP2_NO_SD;
 604                                 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
 605                                 pci_write_config_dword(chip->pdev,
 606                                                        O2_SD_DETECT_SETTING, 3);
 607                         }
 608
 609                         slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
 610                 }
 611
 612                 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) {
 613                         slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
 614                         host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
 615                         host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
 616                 }
 617
 618                 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
 619
 620                 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
 621                         break;
 622                 /* set dll watch dog timer */
 623                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
 624                 reg |= (1 << 12);
 625                 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
 626
 627                 break;
 628         default:
 629                 break;
 630         }
 631
 632         return 0;
 633 }
 634
 635 static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
 636 {
 637         int ret;
 638         u8 scratch;
 639         u32 scratch_32;
 640
 641         switch (chip->pdev->device) {
 642         case PCI_DEVICE_ID_O2_8220:
 643         case PCI_DEVICE_ID_O2_8221:
 644         case PCI_DEVICE_ID_O2_8320:
 645         case PCI_DEVICE_ID_O2_8321:
 646                 /* This extra setup is required due to broken ADMA. */
 647                 ret = pci_read_config_byte(chip->pdev,
 648                                 O2_SD_LOCK_WP, &scratch);
 649                 if (ret)
 650                         return ret;
 651                 scratch &= 0x7f;
 652                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 653
 654                 /* Set Multi 3 to VCC3V# */
 655                 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
 656
 657                 /* Disable CLK_REQ# support after media DET */
 658                 ret = pci_read_config_byte(chip->pdev,
 659                                 O2_SD_CLKREQ, &scratch);
 660                 if (ret)
 661                         return ret;
 662                 scratch |= 0x20;
 663                 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
 664
 665                 /* Choose capabilities, enable SDMA.  We have to write 0x01
 666                  * to the capabilities register first to unlock it.
 667                  */
 668                 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
 669                 if (ret)
 670                         return ret;
 671                 scratch |= 0x01;
 672                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
 673                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
 674
 675                 /* Disable ADMA1/2 */
 676                 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
 677                 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
 678
 679                 /* Disable the infinite transfer mode */
 680                 ret = pci_read_config_byte(chip->pdev,
 681                                 O2_SD_INF_MOD, &scratch);
 682                 if (ret)
 683                         return ret;
 684                 scratch |= 0x08;
 685                 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
 686
 687                 /* Lock WP */
 688                 ret = pci_read_config_byte(chip->pdev,
 689                                 O2_SD_LOCK_WP, &scratch);
 690                 if (ret)
 691                         return ret;
 692                 scratch |= 0x80;
 693                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 694                 break;
 695         case PCI_DEVICE_ID_O2_SDS0:
 696         case PCI_DEVICE_ID_O2_SDS1:
 697         case PCI_DEVICE_ID_O2_FUJIN2:
 698                 /* UnLock WP */
 699                 ret = pci_read_config_byte(chip->pdev,
 700                                 O2_SD_LOCK_WP, &scratch);
 701                 if (ret)
 702                         return ret;
 703
 704                 scratch &= 0x7f;
 705                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 706
 707                 /* DevId=8520 subId= 0x11 or 0x12  Type Chip support */
 708                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
 709                         ret = pci_read_config_dword(chip->pdev,
 710                                                     O2_SD_FUNC_REG0,
 711                                                     &scratch_32);
 712                         scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
 713
 714                         /* Check Whether subId is 0x11 or 0x12 */
 715                         if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
 716                                 scratch_32 = 0x25100000;
 717
 718                                 o2_pci_set_baseclk(chip, scratch_32);
 719                                 ret = pci_read_config_dword(chip->pdev,
 720                                                             O2_SD_FUNC_REG4,
 721                                                             &scratch_32);
 722
 723                                 /* Enable Base Clk setting change */
 724                                 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
 725                                 pci_write_config_dword(chip->pdev,
 726                                                        O2_SD_FUNC_REG4,
 727                                                        scratch_32);
 728
 729                                 /* Set Tuning Window to 4 */
 730                                 pci_write_config_byte(chip->pdev,
 731                                                       O2_SD_TUNING_CTRL, 0x44);
 732
 733                                 break;
 734                         }
 735                 }
 736
 737                 /* Enable 8520 led function */
 738                 o2_pci_led_enable(chip);
 739
 740                 /* Set timeout CLK */
 741                 ret = pci_read_config_dword(chip->pdev,
 742                                             O2_SD_CLK_SETTING, &scratch_32);
 743                 if (ret)
 744                         return ret;
 745
 746                 scratch_32 &= ~(0xFF00);
 747                 scratch_32 |= 0x07E0C800;
 748                 pci_write_config_dword(chip->pdev,
 749                                        O2_SD_CLK_SETTING, scratch_32);
 750
 751                 ret = pci_read_config_dword(chip->pdev,
 752                                             O2_SD_CLKREQ, &scratch_32);
 753                 if (ret)
 754                         return ret;
 755                 scratch_32 |= 0x3;
 756                 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
 757
 758                 ret = pci_read_config_dword(chip->pdev,
 759                                             O2_SD_PLL_SETTING, &scratch_32);
 760                 if (ret)
 761                         return ret;
 762
 763                 scratch_32 &= ~(0x1F3F070E);
 764                 scratch_32 |= 0x18270106;
 765                 pci_write_config_dword(chip->pdev,
 766                                        O2_SD_PLL_SETTING, scratch_32);
 767
 768                 /* Disable UHS1 funciton */
 769                 ret = pci_read_config_dword(chip->pdev,
 770                                             O2_SD_CAP_REG2, &scratch_32);
 771                 if (ret)
 772                         return ret;
 773                 scratch_32 &= ~(0xE0);
 774                 pci_write_config_dword(chip->pdev,
 775                                        O2_SD_CAP_REG2, scratch_32);
 776
 777                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
 778                         sdhci_pci_o2_fujin2_pci_init(chip);
 779
 780                 /* Lock WP */
 781                 ret = pci_read_config_byte(chip->pdev,
 782                                            O2_SD_LOCK_WP, &scratch);
 783                 if (ret)
 784                         return ret;
 785                 scratch |= 0x80;
 786                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 787                 break;
 788         case PCI_DEVICE_ID_O2_SEABIRD0:
 789         case PCI_DEVICE_ID_O2_SEABIRD1:
 790                 /* UnLock WP */
 791                 ret = pci_read_config_byte(chip->pdev,
 792                                 O2_SD_LOCK_WP, &scratch);
 793                 if (ret)
 794                         return ret;
 795
 796                 scratch &= 0x7f;
 797                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 798
 799                 ret = pci_read_config_dword(chip->pdev,
 800                                             O2_SD_PLL_SETTING, &scratch_32);
 801
 802                 if ((scratch_32 & 0xff000000) == 0x01000000) {
 803                         scratch_32 &= 0x0000FFFF;
 804                         scratch_32 |= 0x1F340000;
 805
 806                         pci_write_config_dword(chip->pdev,
 807                                                O2_SD_PLL_SETTING, scratch_32);
 808                 } else {
 809                         scratch_32 &= 0x0000FFFF;
 810                         scratch_32 |= 0x25100000;
 811
 812                         pci_write_config_dword(chip->pdev,
 813                                                O2_SD_PLL_SETTING, scratch_32);
 814
 815                         ret = pci_read_config_dword(chip->pdev,
 816                                                     O2_SD_FUNC_REG4,
 817                                                     &scratch_32);
 818                         scratch_32 |= (1 << 22);
 819                         pci_write_config_dword(chip->pdev,
 820                                                O2_SD_FUNC_REG4, scratch_32);
 821                 }
 822
 823                 /* Set Tuning Windows to 5 */
 824                 pci_write_config_byte(chip->pdev,
 825                                 O2_SD_TUNING_CTRL, 0x55);
 826                 //Adjust 1st and 2nd CD debounce time
 827                 pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32);
 828                 scratch_32 &= 0xFFE7FFFF;
 829                 scratch_32 |= 0x00180000;
 830                 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32);
 831                 pci_write_config_dword(chip->pdev, O2_SD_DETECT_SETTING, 1);
 832                 /* Lock WP */
 833                 ret = pci_read_config_byte(chip->pdev,
 834                                            O2_SD_LOCK_WP, &scratch);
 835                 if (ret)
 836                         return ret;
 837                 scratch |= 0x80;
 838                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 839                 break;
 840         }
 841
 842         return 0;
 843 }
 844
 845 #ifdef CONFIG_PM_SLEEP
 846 static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
 847 {
 848         sdhci_pci_o2_probe(chip);
 849         return sdhci_pci_resume_host(chip);
 850 }
 851 #endif
 852
 853 static const struct sdhci_ops sdhci_pci_o2_ops = {
 854         .set_clock = sdhci_pci_o2_set_clock,
 855         .enable_dma = sdhci_pci_enable_dma,
 856         .set_bus_width = sdhci_set_bus_width,
 857         .reset = sdhci_reset,
 858         .set_uhs_signaling = sdhci_set_uhs_signaling,
 859 };
 860
 861 const struct sdhci_pci_fixes sdhci_o2 = {
 862         .probe = sdhci_pci_o2_probe,
 863         .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 864         .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
 865         .probe_slot = sdhci_pci_o2_probe_slot,
 866 #ifdef CONFIG_PM_SLEEP
 867         .resume = sdhci_pci_o2_resume,
 868 #endif
 869         .ops = &sdhci_pci_o2_ops,
 870         .priv_size = sizeof(struct o2_host),
 871 };