drivers/mmc/host/sdhci-pci-o2micro.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 BayHub Technology Ltd.
   4  *
   5  * Authors: Peter Guo <peter.guo@bayhubtech.com>
   6  *          Adam Lee <adam.lee@canonical.com>
   7  *          Ernest Zhang <ernest.zhang@bayhubtech.com>
   8  */
   9
  10 #include <linux/pci.h>
  11 #include <linux/mmc/host.h>
  12 #include <linux/mmc/mmc.h>
  13 #include <linux/delay.h>
  14 #include <linux/iopoll.h>
  15
  16 #include "sdhci.h"
  17 #include "sdhci-pci.h"
  18
  19 /*
  20  * O2Micro device registers
  21  */
  22
  23 #define O2_SD_MISC_REG5         0x64
  24 #define O2_SD_LD0_CTRL          0x68
  25 #define O2_SD_DEV_CTRL          0x88
  26 #define O2_SD_LOCK_WP           0xD3
  27 #define O2_SD_TEST_REG          0xD4
  28 #define O2_SD_FUNC_REG0         0xDC
  29 #define O2_SD_MULTI_VCC3V       0xEE
  30 #define O2_SD_CLKREQ            0xEC
  31 #define O2_SD_CAPS              0xE0
  32 #define O2_SD_ADMA1             0xE2
  33 #define O2_SD_ADMA2             0xE7
  34 #define O2_SD_INF_MOD           0xF1
  35 #define O2_SD_MISC_CTRL4        0xFC
  36 #define O2_SD_MISC_CTRL         0x1C0
  37 #define O2_SD_PWR_FORCE_L0      0x0002
  38 #define O2_SD_TUNING_CTRL       0x300
  39 #define O2_SD_PLL_SETTING       0x304
  40 #define O2_SD_MISC_SETTING      0x308
  41 #define O2_SD_CLK_SETTING       0x328
  42 #define O2_SD_CAP_REG2          0x330
  43 #define O2_SD_CAP_REG0          0x334
  44 #define O2_SD_UHS1_CAP_SETTING  0x33C
  45 #define O2_SD_DELAY_CTRL        0x350
  46 #define O2_SD_UHS2_L1_CTRL      0x35C
  47 #define O2_SD_FUNC_REG3         0x3E0
  48 #define O2_SD_FUNC_REG4         0x3E4
  49 #define O2_SD_LED_ENABLE        BIT(6)
  50 #define O2_SD_FREG0_LEDOFF      BIT(13)
  51 #define O2_SD_FREG4_ENABLE_CLK_SET      BIT(22)
  52
  53 #define O2_SD_VENDOR_SETTING    0x110
  54 #define O2_SD_VENDOR_SETTING2   0x1C8
  55 #define O2_SD_HW_TUNING_DISABLE BIT(4)
  56
  57 #define O2_PLL_DLL_WDT_CONTROL1 0x1CC
  58 #define  O2_PLL_FORCE_ACTIVE    BIT(18)
  59 #define  O2_PLL_LOCK_STATUS     BIT(14)
  60 #define  O2_PLL_SOFT_RESET      BIT(12)
  61 #define  O2_DLL_LOCK_STATUS     BIT(11)
  62
  63 #define O2_SD_DETECT_SETTING 0x324
  64
  65 static const u32 dmdn_table[] = {0x2B1C0000,
  66         0x2C1A0000, 0x371B0000, 0x35100000};
  67 #define DMDN_SZ ARRAY_SIZE(dmdn_table)
  68
  69 struct o2_host {
  70         u8 dll_adjust_count;
  71 };
  72
  73 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
  74 {
  75         ktime_t timeout;
  76         u32 scratch32;
  77
  78         /* Wait max 50 ms */
  79         timeout = ktime_add_ms(ktime_get(), 50);
  80         while (1) {
  81                 bool timedout = ktime_after(ktime_get(), timeout);
  82
  83                 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
  84                 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
  85                     == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
  86                         break;
  87
  88                 if (timedout) {
  89                         pr_err("%s: Card Detect debounce never finished.\n",
  90                                mmc_hostname(host->mmc));
  91                         sdhci_dumpregs(host);
  92                         return;
  93                 }
  94                 udelay(10);
  95         }
  96 }
  97
  98 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
  99 {
 100         ktime_t timeout;
 101         u16 scratch;
 102         u32 scratch32;
 103
 104         /* PLL software reset */
 105         scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
 106         scratch32 |= O2_PLL_SOFT_RESET;
 107         sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
 108         udelay(1);
 109         scratch32 &= ~(O2_PLL_SOFT_RESET);
 110         sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
 111
 112         /* PLL force active */
 113         scratch32 |= O2_PLL_FORCE_ACTIVE;
 114         sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
 115
 116         /* Wait max 20 ms */
 117         timeout = ktime_add_ms(ktime_get(), 20);
 118         while (1) {
 119                 bool timedout = ktime_after(ktime_get(), timeout);
 120
 121                 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
 122                 if (scratch & O2_PLL_LOCK_STATUS)
 123                         break;
 124                 if (timedout) {
 125                         pr_err("%s: Internal clock never stabilised.\n",
 126                                mmc_hostname(host->mmc));
 127                         sdhci_dumpregs(host);
 128                         goto out;
 129                 }
 130                 udelay(10);
 131         }
 132
 133         /* Wait for card detect finish */
 134         udelay(1);
 135         sdhci_o2_wait_card_detect_stable(host);
 136
 137 out:
 138         /* Cancel PLL force active */
 139         scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
 140         scratch32 &= ~O2_PLL_FORCE_ACTIVE;
 141         sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
 142 }
 143
 144 static int sdhci_o2_get_cd(struct mmc_host *mmc)
 145 {
 146         struct sdhci_host *host = mmc_priv(mmc);
 147
 148         if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
 149                 sdhci_o2_enable_internal_clock(host);
 150         else
 151                 sdhci_o2_wait_card_detect_stable(host);
 152
 153         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
 154 }
 155
 156 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
 157 {
 158         u32 scratch_32;
 159
 160         pci_read_config_dword(chip->pdev,
 161                               O2_SD_PLL_SETTING, &scratch_32);
 162
 163         scratch_32 &= 0x0000FFFF;
 164         scratch_32 |= value;
 165
 166         pci_write_config_dword(chip->pdev,
 167                                O2_SD_PLL_SETTING, scratch_32);
 168 }
 169
 170 static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
 171 {
 172         return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
 173 }
 174
 175 /*
 176  * This function is used to detect dll lock status.
 177  * Since the dll lock status bit will toggle randomly
 178  * with very short interval which needs to be polled
 179  * as fast as possible. Set sleep_us as 1 microsecond.
 180  */
 181 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
 182 {
 183         u32     scratch32 = 0;
 184
 185         return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
 186                 scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
 187 }
 188
 189 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
 190 {
 191         u16 reg;
 192
 193         /* enable hardware tuning */
 194         reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
 195         reg &= ~O2_SD_HW_TUNING_DISABLE;
 196         sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
 197 }
 198
 199 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
 200 {
 201         int i;
 202
 203         sdhci_send_tuning(host, opcode);
 204
 205         for (i = 0; i < 150; i++) {
 206                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 207
 208                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
 209                         if (ctrl & SDHCI_CTRL_TUNED_CLK) {
 210                                 host->tuning_done = true;
 211                                 return;
 212                         }
 213                         pr_warn("%s: HW tuning failed !\n",
 214                                 mmc_hostname(host->mmc));
 215                         break;
 216                 }
 217
 218                 mdelay(1);
 219         }
 220
 221         pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
 222                 mmc_hostname(host->mmc));
 223         sdhci_reset_tuning(host);
 224 }
 225
 226 /*
 227  * This function is used to fix o2 dll shift issue.
 228  * It isn't necessary to detect card present before recovery.
 229  * Firstly, it is used by bht emmc card, which is embedded.
 230  * Second, before call recovery card present will be detected
 231  * outside of the execute tuning function.
 232  */
 233 static int sdhci_o2_dll_recovery(struct sdhci_host *host)
 234 {
 235         int ret = 0;
 236         u8 scratch_8 = 0;
 237         u32 scratch_32 = 0;
 238         struct sdhci_pci_slot *slot = sdhci_priv(host);
 239         struct sdhci_pci_chip *chip = slot->chip;
 240         struct o2_host *o2_host = sdhci_pci_priv(slot);
 241
 242         /* UnLock WP */
 243         pci_read_config_byte(chip->pdev,
 244                         O2_SD_LOCK_WP, &scratch_8);
 245         scratch_8 &= 0x7f;
 246         pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
 247         while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
 248                 /* Disable clock */
 249                 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
 250
 251                 /* PLL software reset */
 252                 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
 253                 scratch_32 |= O2_PLL_SOFT_RESET;
 254                 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
 255
 256                 pci_read_config_dword(chip->pdev,
 257                                             O2_SD_FUNC_REG4,
 258                                             &scratch_32);
 259                 /* Enable Base Clk setting change */
 260                 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
 261                 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
 262                 o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
 263
 264                 /* Enable internal clock */
 265                 scratch_8 = SDHCI_CLOCK_INT_EN;
 266                 sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
 267
 268                 if (sdhci_o2_get_cd(host->mmc)) {
 269                         /*
 270                          * need wait at least 5ms for dll status stable,
 271                          * after enable internal clock
 272                          */
 273                         usleep_range(5000, 6000);
 274                         if (sdhci_o2_wait_dll_detect_lock(host)) {
 275                                 scratch_8 |= SDHCI_CLOCK_CARD_EN;
 276                                 sdhci_writeb(host, scratch_8,
 277                                         SDHCI_CLOCK_CONTROL);
 278                                 ret = 1;
 279                         } else {
 280                                 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
 281                                         mmc_hostname(host->mmc),
 282                                         o2_host->dll_adjust_count);
 283                         }
 284                 } else {
 285                         pr_err("%s: card present detect failed.\n",
 286                                 mmc_hostname(host->mmc));
 287                         break;
 288                 }
 289
 290                 o2_host->dll_adjust_count++;
 291         }
 292         if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
 293                 pr_err("%s: DLL adjust over max times\n",
 294                 mmc_hostname(host->mmc));
 295         /* Lock WP */
 296         pci_read_config_byte(chip->pdev,
 297                                    O2_SD_LOCK_WP, &scratch_8);
 298         scratch_8 |= 0x80;
 299         pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
 300         return ret;
 301 }
 302
 303 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
 304 {
 305         struct sdhci_host *host = mmc_priv(mmc);
 306         int current_bus_width = 0;
 307         u32 scratch32 = 0;
 308         u16 scratch = 0;
 309
 310         /*
 311          * This handler only implements the eMMC tuning that is specific to
 312          * this controller.  Fall back to the standard method for other TIMING.
 313          */
 314         if ((host->timing != MMC_TIMING_MMC_HS200) &&
 315                 (host->timing != MMC_TIMING_UHS_SDR104))
 316                 return sdhci_execute_tuning(mmc, opcode);
 317
 318         if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) &&
 319                         (opcode != MMC_SEND_TUNING_BLOCK)))
 320                 return -EINVAL;
 321
 322         /* Force power mode enter L0 */
 323         scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
 324         scratch |= O2_SD_PWR_FORCE_L0;
 325         sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
 326
 327         /* wait DLL lock, timeout value 5ms */
 328         if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
 329                 scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000))
 330                 pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n",
 331                                 mmc_hostname(host->mmc));
 332         /*
 333          * Judge the tuning reason, whether caused by dll shift
 334          * If cause by dll shift, should call sdhci_o2_dll_recovery
 335          */
 336         if (!sdhci_o2_wait_dll_detect_lock(host))
 337                 if (!sdhci_o2_dll_recovery(host)) {
 338                         pr_err("%s: o2 dll recovery failed\n",
 339                                 mmc_hostname(host->mmc));
 340                         return -EINVAL;
 341                 }
 342         /*
 343          * o2 sdhci host didn't support 8bit emmc tuning
 344          */
 345         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
 346                 current_bus_width = mmc->ios.bus_width;
 347                 mmc->ios.bus_width = MMC_BUS_WIDTH_4;
 348                 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
 349         }
 350
 351         sdhci_o2_set_tuning_mode(host);
 352
 353         sdhci_start_tuning(host);
 354
 355         __sdhci_o2_execute_tuning(host, opcode);
 356
 357         sdhci_end_tuning(host);
 358
 359         if (current_bus_width == MMC_BUS_WIDTH_8) {
 360                 mmc->ios.bus_width = MMC_BUS_WIDTH_8;
 361                 sdhci_set_bus_width(host, current_bus_width);
 362         }
 363
 364         /* Cancel force power mode enter L0 */
 365         scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
 366         scratch &= ~(O2_SD_PWR_FORCE_L0);
 367         sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
 368
 369         sdhci_reset(host, SDHCI_RESET_CMD);
 370         sdhci_reset(host, SDHCI_RESET_DATA);
 371
 372         host->flags &= ~SDHCI_HS400_TUNING;
 373         return 0;
 374 }
 375
 376 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
 377 {
 378         int ret;
 379         u32 scratch_32;
 380
 381         /* Set led of SD host function enable */
 382         ret = pci_read_config_dword(chip->pdev,
 383                                     O2_SD_FUNC_REG0, &scratch_32);
 384         if (ret)
 385                 return;
 386
 387         scratch_32 &= ~O2_SD_FREG0_LEDOFF;
 388         pci_write_config_dword(chip->pdev,
 389                                O2_SD_FUNC_REG0, scratch_32);
 390
 391         ret = pci_read_config_dword(chip->pdev,
 392                                     O2_SD_TEST_REG, &scratch_32);
 393         if (ret)
 394                 return;
 395
 396         scratch_32 |= O2_SD_LED_ENABLE;
 397         pci_write_config_dword(chip->pdev,
 398                                O2_SD_TEST_REG, scratch_32);
 399 }
 400
 401 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
 402 {
 403         u32 scratch_32;
 404         int ret;
 405         /* Improve write performance for SD3.0 */
 406         ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
 407         if (ret)
 408                 return;
 409         scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
 410         pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
 411
 412         /* Enable Link abnormal reset generating Reset */
 413         ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
 414         if (ret)
 415                 return;
 416         scratch_32 &= ~((1 << 19) | (1 << 11));
 417         scratch_32 |= (1 << 10);
 418         pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
 419
 420         /* set card power over current protection */
 421         ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
 422         if (ret)
 423                 return;
 424         scratch_32 |= (1 << 4);
 425         pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
 426
 427         /* adjust the output delay for SD mode */
 428         pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
 429
 430         /* Set the output voltage setting of Aux 1.2v LDO */
 431         ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
 432         if (ret)
 433                 return;
 434         scratch_32 &= ~(3 << 12);
 435         pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
 436
 437         /* Set Max power supply capability of SD host */
 438         ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
 439         if (ret)
 440                 return;
 441         scratch_32 &= ~(0x01FE);
 442         scratch_32 |= 0x00CC;
 443         pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
 444         /* Set DLL Tuning Window */
 445         ret = pci_read_config_dword(chip->pdev,
 446                                     O2_SD_TUNING_CTRL, &scratch_32);
 447         if (ret)
 448                 return;
 449         scratch_32 &= ~(0x000000FF);
 450         scratch_32 |= 0x00000066;
 451         pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
 452
 453         /* Set UHS2 T_EIDLE */
 454         ret = pci_read_config_dword(chip->pdev,
 455                                     O2_SD_UHS2_L1_CTRL, &scratch_32);
 456         if (ret)
 457                 return;
 458         scratch_32 &= ~(0x000000FC);
 459         scratch_32 |= 0x00000084;
 460         pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
 461
 462         /* Set UHS2 Termination */
 463         ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
 464         if (ret)
 465                 return;
 466         scratch_32 &= ~((1 << 21) | (1 << 30));
 467
 468         pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
 469
 470         /* Set L1 Entrance Timer */
 471         ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
 472         if (ret)
 473                 return;
 474         scratch_32 &= ~(0xf0000000);
 475         scratch_32 |= 0x30000000;
 476         pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
 477
 478         ret = pci_read_config_dword(chip->pdev,
 479                                     O2_SD_MISC_CTRL4, &scratch_32);
 480         if (ret)
 481                 return;
 482         scratch_32 &= ~(0x000f0000);
 483         scratch_32 |= 0x00080000;
 484         pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
 485 }
 486
 487 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
 488                                     struct sdhci_host *host)
 489 {
 490         int ret;
 491
 492         ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
 493         if (!ret) {
 494                 pr_info("%s: unsupport msi, use INTx irq\n",
 495                         mmc_hostname(host->mmc));
 496                 return;
 497         }
 498
 499         ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
 500                                     PCI_IRQ_MSI | PCI_IRQ_MSIX);
 501         if (ret < 0) {
 502                 pr_err("%s: enable PCI MSI failed, err=%d\n",
 503                        mmc_hostname(host->mmc), ret);
 504                 return;
 505         }
 506
 507         host->irq = pci_irq_vector(chip->pdev, 0);
 508 }
 509
 510 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
 511 {
 512         /* Enable internal clock */
 513         clk |= SDHCI_CLOCK_INT_EN;
 514         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 515
 516         sdhci_o2_enable_internal_clock(host);
 517         if (sdhci_o2_get_cd(host->mmc)) {
 518                 clk |= SDHCI_CLOCK_CARD_EN;
 519                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 520         }
 521 }
 522
 523 static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
 524 {
 525         u16 clk;
 526         u8 scratch;
 527         u32 scratch_32;
 528         struct sdhci_pci_slot *slot = sdhci_priv(host);
 529         struct sdhci_pci_chip *chip = slot->chip;
 530
 531         host->mmc->actual_clock = 0;
 532
 533         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 534
 535         if (clock == 0)
 536                 return;
 537
 538         if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
 539                 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
 540
 541                 scratch &= 0x7f;
 542                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 543
 544                 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
 545
 546                 if ((scratch_32 & 0xFFFF0000) != 0x2c280000)
 547                         o2_pci_set_baseclk(chip, 0x2c280000);
 548
 549                 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
 550
 551                 scratch |= 0x80;
 552                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 553         }
 554
 555         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
 556         sdhci_o2_enable_clk(host, clk);
 557 }
 558
 559 static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
 560 {
 561         struct sdhci_pci_chip *chip;
 562         struct sdhci_host *host;
 563         struct o2_host *o2_host = sdhci_pci_priv(slot);
 564         u32 reg, caps;
 565         int ret;
 566
 567         chip = slot->chip;
 568         host = slot->host;
 569
 570         o2_host->dll_adjust_count = 0;
 571         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 572
 573         /*
 574          * mmc_select_bus_width() will test the bus to determine the actual bus
 575          * width.
 576          */
 577         if (caps & SDHCI_CAN_DO_8BIT)
 578                 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 579
 580         switch (chip->pdev->device) {
 581         case PCI_DEVICE_ID_O2_SDS0:
 582         case PCI_DEVICE_ID_O2_SEABIRD0:
 583         case PCI_DEVICE_ID_O2_SEABIRD1:
 584         case PCI_DEVICE_ID_O2_SDS1:
 585         case PCI_DEVICE_ID_O2_FUJIN2:
 586                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
 587                 if (reg & 0x1)
 588                         host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
 589
 590                 sdhci_pci_o2_enable_msi(chip, host);
 591
 592                 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
 593                         ret = pci_read_config_dword(chip->pdev,
 594                                                     O2_SD_MISC_SETTING, &reg);
 595                         if (ret)
 596                                 return -EIO;
 597                         if (reg & (1 << 4)) {
 598                                 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
 599                                         mmc_hostname(host->mmc));
 600                                 host->flags &= ~SDHCI_SIGNALING_330;
 601                                 host->flags |= SDHCI_SIGNALING_180;
 602                                 host->mmc->caps2 |= MMC_CAP2_NO_SD;
 603                                 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
 604                                 pci_write_config_dword(chip->pdev,
 605                                                        O2_SD_DETECT_SETTING, 3);
 606                         }
 607
 608                         slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
 609                 }
 610
 611                 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) {
 612                         slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
 613                         host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
 614                         host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
 615                 }
 616
 617                 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
 618
 619                 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
 620                         break;
 621                 /* set dll watch dog timer */
 622                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
 623                 reg |= (1 << 12);
 624                 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
 625
 626                 break;
 627         default:
 628                 break;
 629         }
 630
 631         return 0;
 632 }
 633
 634 static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
 635 {
 636         int ret;
 637         u8 scratch;
 638         u32 scratch_32;
 639
 640         switch (chip->pdev->device) {
 641         case PCI_DEVICE_ID_O2_8220:
 642         case PCI_DEVICE_ID_O2_8221:
 643         case PCI_DEVICE_ID_O2_8320:
 644         case PCI_DEVICE_ID_O2_8321:
 645                 /* This extra setup is required due to broken ADMA. */
 646                 ret = pci_read_config_byte(chip->pdev,
 647                                 O2_SD_LOCK_WP, &scratch);
 648                 if (ret)
 649                         return ret;
 650                 scratch &= 0x7f;
 651                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 652
 653                 /* Set Multi 3 to VCC3V# */
 654                 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
 655
 656                 /* Disable CLK_REQ# support after media DET */
 657                 ret = pci_read_config_byte(chip->pdev,
 658                                 O2_SD_CLKREQ, &scratch);
 659                 if (ret)
 660                         return ret;
 661                 scratch |= 0x20;
 662                 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
 663
 664                 /* Choose capabilities, enable SDMA.  We have to write 0x01
 665                  * to the capabilities register first to unlock it.
 666                  */
 667                 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
 668                 if (ret)
 669                         return ret;
 670                 scratch |= 0x01;
 671                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
 672                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
 673
 674                 /* Disable ADMA1/2 */
 675                 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
 676                 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
 677
 678                 /* Disable the infinite transfer mode */
 679                 ret = pci_read_config_byte(chip->pdev,
 680                                 O2_SD_INF_MOD, &scratch);
 681                 if (ret)
 682                         return ret;
 683                 scratch |= 0x08;
 684                 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
 685
 686                 /* Lock WP */
 687                 ret = pci_read_config_byte(chip->pdev,
 688                                 O2_SD_LOCK_WP, &scratch);
 689                 if (ret)
 690                         return ret;
 691                 scratch |= 0x80;
 692                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 693                 break;
 694         case PCI_DEVICE_ID_O2_SDS0:
 695         case PCI_DEVICE_ID_O2_SDS1:
 696         case PCI_DEVICE_ID_O2_FUJIN2:
 697                 /* UnLock WP */
 698                 ret = pci_read_config_byte(chip->pdev,
 699                                 O2_SD_LOCK_WP, &scratch);
 700                 if (ret)
 701                         return ret;
 702
 703                 scratch &= 0x7f;
 704                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 705
 706                 /* DevId=8520 subId= 0x11 or 0x12  Type Chip support */
 707                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
 708                         ret = pci_read_config_dword(chip->pdev,
 709                                                     O2_SD_FUNC_REG0,
 710                                                     &scratch_32);
 711                         scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
 712
 713                         /* Check Whether subId is 0x11 or 0x12 */
 714                         if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
 715                                 scratch_32 = 0x25100000;
 716
 717                                 o2_pci_set_baseclk(chip, scratch_32);
 718                                 ret = pci_read_config_dword(chip->pdev,
 719                                                             O2_SD_FUNC_REG4,
 720                                                             &scratch_32);
 721
 722                                 /* Enable Base Clk setting change */
 723                                 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
 724                                 pci_write_config_dword(chip->pdev,
 725                                                        O2_SD_FUNC_REG4,
 726                                                        scratch_32);
 727
 728                                 /* Set Tuning Window to 4 */
 729                                 pci_write_config_byte(chip->pdev,
 730                                                       O2_SD_TUNING_CTRL, 0x44);
 731
 732                                 break;
 733                         }
 734                 }
 735
 736                 /* Enable 8520 led function */
 737                 o2_pci_led_enable(chip);
 738
 739                 /* Set timeout CLK */
 740                 ret = pci_read_config_dword(chip->pdev,
 741                                             O2_SD_CLK_SETTING, &scratch_32);
 742                 if (ret)
 743                         return ret;
 744
 745                 scratch_32 &= ~(0xFF00);
 746                 scratch_32 |= 0x07E0C800;
 747                 pci_write_config_dword(chip->pdev,
 748                                        O2_SD_CLK_SETTING, scratch_32);
 749
 750                 ret = pci_read_config_dword(chip->pdev,
 751                                             O2_SD_CLKREQ, &scratch_32);
 752                 if (ret)
 753                         return ret;
 754                 scratch_32 |= 0x3;
 755                 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
 756
 757                 ret = pci_read_config_dword(chip->pdev,
 758                                             O2_SD_PLL_SETTING, &scratch_32);
 759                 if (ret)
 760                         return ret;
 761
 762                 scratch_32 &= ~(0x1F3F070E);
 763                 scratch_32 |= 0x18270106;
 764                 pci_write_config_dword(chip->pdev,
 765                                        O2_SD_PLL_SETTING, scratch_32);
 766
 767                 /* Disable UHS1 funciton */
 768                 ret = pci_read_config_dword(chip->pdev,
 769                                             O2_SD_CAP_REG2, &scratch_32);
 770                 if (ret)
 771                         return ret;
 772                 scratch_32 &= ~(0xE0);
 773                 pci_write_config_dword(chip->pdev,
 774                                        O2_SD_CAP_REG2, scratch_32);
 775
 776                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
 777                         sdhci_pci_o2_fujin2_pci_init(chip);
 778
 779                 /* Lock WP */
 780                 ret = pci_read_config_byte(chip->pdev,
 781                                            O2_SD_LOCK_WP, &scratch);
 782                 if (ret)
 783                         return ret;
 784                 scratch |= 0x80;
 785                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 786                 break;
 787         case PCI_DEVICE_ID_O2_SEABIRD0:
 788         case PCI_DEVICE_ID_O2_SEABIRD1:
 789                 /* UnLock WP */
 790                 ret = pci_read_config_byte(chip->pdev,
 791                                 O2_SD_LOCK_WP, &scratch);
 792                 if (ret)
 793                         return ret;
 794
 795                 scratch &= 0x7f;
 796                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 797
 798                 ret = pci_read_config_dword(chip->pdev,
 799                                             O2_SD_PLL_SETTING, &scratch_32);
 800
 801                 if ((scratch_32 & 0xff000000) == 0x01000000) {
 802                         scratch_32 &= 0x0000FFFF;
 803                         scratch_32 |= 0x1F340000;
 804
 805                         pci_write_config_dword(chip->pdev,
 806                                                O2_SD_PLL_SETTING, scratch_32);
 807                 } else {
 808                         scratch_32 &= 0x0000FFFF;
 809                         scratch_32 |= 0x25100000;
 810
 811                         pci_write_config_dword(chip->pdev,
 812                                                O2_SD_PLL_SETTING, scratch_32);
 813
 814                         ret = pci_read_config_dword(chip->pdev,
 815                                                     O2_SD_FUNC_REG4,
 816                                                     &scratch_32);
 817                         scratch_32 |= (1 << 22);
 818                         pci_write_config_dword(chip->pdev,
 819                                                O2_SD_FUNC_REG4, scratch_32);
 820                 }
 821
 822                 /* Set Tuning Windows to 5 */
 823                 pci_write_config_byte(chip->pdev,
 824                                 O2_SD_TUNING_CTRL, 0x55);
 825                 /* Lock WP */
 826                 ret = pci_read_config_byte(chip->pdev,
 827                                            O2_SD_LOCK_WP, &scratch);
 828                 if (ret)
 829                         return ret;
 830                 scratch |= 0x80;
 831                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 832                 break;
 833         }
 834
 835         return 0;
 836 }
 837
 838 #ifdef CONFIG_PM_SLEEP
 839 static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
 840 {
 841         sdhci_pci_o2_probe(chip);
 842         return sdhci_pci_resume_host(chip);
 843 }
 844 #endif
 845
 846 static const struct sdhci_ops sdhci_pci_o2_ops = {
 847         .set_clock = sdhci_pci_o2_set_clock,
 848         .enable_dma = sdhci_pci_enable_dma,
 849         .set_bus_width = sdhci_set_bus_width,
 850         .reset = sdhci_reset,
 851         .set_uhs_signaling = sdhci_set_uhs_signaling,
 852 };
 853
 854 const struct sdhci_pci_fixes sdhci_o2 = {
 855         .probe = sdhci_pci_o2_probe,
 856         .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 857         .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
 858         .probe_slot = sdhci_pci_o2_probe_slot,
 859 #ifdef CONFIG_PM_SLEEP
 860         .resume = sdhci_pci_o2_resume,
 861 #endif
 862         .ops = &sdhci_pci_o2_ops,
 863         .priv_size = sizeof(struct o2_host),
 864 };