drivers/mmc/host/sdhci-pci-gli.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 Genesys Logic, Inc.
   4  *
   5  * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw>
   6  *
   7  * Version: v0.9.0 (2019-08-08)
   8  */
   9
  10 #include <linux/bitfield.h>
  11 #include <linux/bits.h>
  12 #include <linux/pci.h>
  13 #include <linux/mmc/mmc.h>
  14 #include <linux/delay.h>
  15 #include "sdhci.h"
  16 #include "sdhci-pci.h"
  17 #include "cqhci.h"
  18
  19 /*  Genesys Logic extra registers */
  20 #define SDHCI_GLI_9750_WT         0x800
  21 #define   SDHCI_GLI_9750_WT_EN      BIT(0)
  22 #define   GLI_9750_WT_EN_ON         0x1
  23 #define   GLI_9750_WT_EN_OFF        0x0
  24
  25 #define SDHCI_GLI_9750_DRIVING      0x860
  26 #define   SDHCI_GLI_9750_DRIVING_1    GENMASK(11, 0)
  27 #define   SDHCI_GLI_9750_DRIVING_2    GENMASK(27, 26)
  28 #define   GLI_9750_DRIVING_1_VALUE    0xFFF
  29 #define   GLI_9750_DRIVING_2_VALUE    0x3
  30 #define   SDHCI_GLI_9750_SEL_1        BIT(29)
  31 #define   SDHCI_GLI_9750_SEL_2        BIT(31)
  32 #define   SDHCI_GLI_9750_ALL_RST      (BIT(24)|BIT(25)|BIT(28)|BIT(30))
  33
  34 #define SDHCI_GLI_9750_PLL            0x864
  35 #define   SDHCI_GLI_9750_PLL_LDIV       GENMASK(9, 0)
  36 #define   SDHCI_GLI_9750_PLL_PDIV       GENMASK(14, 12)
  37 #define   SDHCI_GLI_9750_PLL_DIR        BIT(15)
  38 #define   SDHCI_GLI_9750_PLL_TX2_INV    BIT(23)
  39 #define   SDHCI_GLI_9750_PLL_TX2_DLY    GENMASK(22, 20)
  40 #define   GLI_9750_PLL_TX2_INV_VALUE    0x1
  41 #define   GLI_9750_PLL_TX2_DLY_VALUE    0x0
  42 #define   SDHCI_GLI_9750_PLLSSC_STEP    GENMASK(28, 24)
  43 #define   SDHCI_GLI_9750_PLLSSC_EN      BIT(31)
  44
  45 #define SDHCI_GLI_9750_PLLSSC        0x86C
  46 #define   SDHCI_GLI_9750_PLLSSC_PPM    GENMASK(31, 16)
  47
  48 #define SDHCI_GLI_9750_SW_CTRL      0x874
  49 #define   SDHCI_GLI_9750_SW_CTRL_4    GENMASK(7, 6)
  50 #define   GLI_9750_SW_CTRL_4_VALUE    0x3
  51
  52 #define SDHCI_GLI_9750_MISC            0x878
  53 #define   SDHCI_GLI_9750_MISC_TX1_INV    BIT(2)
  54 #define   SDHCI_GLI_9750_MISC_RX_INV     BIT(3)
  55 #define   SDHCI_GLI_9750_MISC_TX1_DLY    GENMASK(6, 4)
  56 #define   GLI_9750_MISC_TX1_INV_VALUE    0x0
  57 #define   GLI_9750_MISC_RX_INV_ON        0x1
  58 #define   GLI_9750_MISC_RX_INV_OFF       0x0
  59 #define   GLI_9750_MISC_RX_INV_VALUE     GLI_9750_MISC_RX_INV_OFF
  60 #define   GLI_9750_MISC_TX1_DLY_VALUE    0x5
  61
  62 #define SDHCI_GLI_9750_TUNING_CONTROL             0x540
  63 #define   SDHCI_GLI_9750_TUNING_CONTROL_EN          BIT(4)
  64 #define   GLI_9750_TUNING_CONTROL_EN_ON             0x1
  65 #define   GLI_9750_TUNING_CONTROL_EN_OFF            0x0
  66 #define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1    BIT(16)
  67 #define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2    GENMASK(20, 19)
  68 #define   GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE    0x1
  69 #define   GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE    0x2
  70
  71 #define SDHCI_GLI_9750_TUNING_PARAMETERS           0x544
  72 #define   SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY    GENMASK(2, 0)
  73 #define   GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE    0x1
  74
  75 #define SDHCI_GLI_9763E_CTRL_HS400  0x7
  76
  77 #define SDHCI_GLI_9763E_HS400_ES_REG      0x52C
  78 #define   SDHCI_GLI_9763E_HS400_ES_BIT      BIT(8)
  79
  80 #define PCIE_GLI_9763E_VHS       0x884
  81 #define   GLI_9763E_VHS_REV        GENMASK(19, 16)
  82 #define   GLI_9763E_VHS_REV_R      0x0
  83 #define   GLI_9763E_VHS_REV_M      0x1
  84 #define   GLI_9763E_VHS_REV_W      0x2
  85 #define PCIE_GLI_9763E_MB        0x888
  86 #define   GLI_9763E_MB_CMDQ_OFF    BIT(19)
  87 #define PCIE_GLI_9763E_SCR       0x8E0
  88 #define   GLI_9763E_SCR_AXI_REQ    BIT(9)
  89
  90 #define SDHCI_GLI_9763E_CQE_BASE_ADDR    0x200
  91 #define GLI_9763E_CQE_TRNS_MODE    (SDHCI_TRNS_MULTI | \
  92                                     SDHCI_TRNS_BLK_CNT_EN | \
  93                                     SDHCI_TRNS_DMA)
  94
  95 #define PCI_GLI_9755_WT       0x800
  96 #define   PCI_GLI_9755_WT_EN    BIT(0)
  97 #define   GLI_9755_WT_EN_ON     0x1
  98 #define   GLI_9755_WT_EN_OFF    0x0
  99
 100 #define PCI_GLI_9755_PLL            0x64
 101 #define   PCI_GLI_9755_PLL_LDIV       GENMASK(9, 0)
 102 #define   PCI_GLI_9755_PLL_PDIV       GENMASK(14, 12)
 103 #define   PCI_GLI_9755_PLL_DIR        BIT(15)
 104 #define   PCI_GLI_9755_PLLSSC_STEP    GENMASK(28, 24)
 105 #define   PCI_GLI_9755_PLLSSC_EN      BIT(31)
 106
 107 #define PCI_GLI_9755_PLLSSC        0x68
 108 #define   PCI_GLI_9755_PLLSSC_PPM    GENMASK(15, 0)
 109
 110 #define GLI_MAX_TUNING_LOOP 40
 111
 112 /* Genesys Logic chipset */
 113 static inline void gl9750_wt_on(struct sdhci_host *host)
 114 {
 115         u32 wt_value;
 116         u32 wt_enable;
 117
 118         wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
 119         wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
 120
 121         if (wt_enable == GLI_9750_WT_EN_ON)
 122                 return;
 123
 124         wt_value &= ~SDHCI_GLI_9750_WT_EN;
 125         wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);
 126
 127         sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
 128 }
 129
 130 static inline void gl9750_wt_off(struct sdhci_host *host)
 131 {
 132         u32 wt_value;
 133         u32 wt_enable;
 134
 135         wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
 136         wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
 137
 138         if (wt_enable == GLI_9750_WT_EN_OFF)
 139                 return;
 140
 141         wt_value &= ~SDHCI_GLI_9750_WT_EN;
 142         wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);
 143
 144         sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
 145 }
 146
 147 static void gli_set_9750(struct sdhci_host *host)
 148 {
 149         u32 driving_value;
 150         u32 pll_value;
 151         u32 sw_ctrl_value;
 152         u32 misc_value;
 153         u32 parameter_value;
 154         u32 control_value;
 155         u16 ctrl2;
 156
 157         gl9750_wt_on(host);
 158
 159         driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
 160         pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
 161         sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
 162         misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
 163         parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
 164         control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
 165
 166         driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);
 167         driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);
 168         driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,
 169                                     GLI_9750_DRIVING_1_VALUE);
 170         driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,
 171                                     GLI_9750_DRIVING_2_VALUE);
 172         driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST);
 173         driving_value |= SDHCI_GLI_9750_SEL_2;
 174         sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
 175
 176         sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;
 177         sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,
 178                                     GLI_9750_SW_CTRL_4_VALUE);
 179         sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
 180
 181         /* reset the tuning flow after reinit and before starting tuning */
 182         pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;
 183         pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;
 184         pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,
 185                                 GLI_9750_PLL_TX2_INV_VALUE);
 186         pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,
 187                                 GLI_9750_PLL_TX2_DLY_VALUE);
 188
 189         misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;
 190         misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
 191         misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;
 192         misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,
 193                                  GLI_9750_MISC_TX1_INV_VALUE);
 194         misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
 195                                  GLI_9750_MISC_RX_INV_VALUE);
 196         misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,
 197                                  GLI_9750_MISC_TX1_DLY_VALUE);
 198
 199         parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;
 200         parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,
 201                                       GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);
 202
 203         control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
 204         control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
 205         control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
 206                                     GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);
 207         control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
 208                                     GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);
 209
 210         sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
 211         sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
 212
 213         /* disable tuned clk */
 214         ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 215         ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
 216         sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
 217
 218         /* enable tuning parameters control */
 219         control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
 220         control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
 221                                     GLI_9750_TUNING_CONTROL_EN_ON);
 222         sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
 223
 224         /* write tuning parameters */
 225         sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
 226
 227         /* disable tuning parameters control */
 228         control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
 229         control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
 230                                     GLI_9750_TUNING_CONTROL_EN_OFF);
 231         sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
 232
 233         /* clear tuned clk */
 234         ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 235         ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
 236         sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
 237
 238         gl9750_wt_off(host);
 239 }
 240
 241 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
 242 {
 243         u32 misc_value;
 244
 245         gl9750_wt_on(host);
 246
 247         misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
 248         misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
 249         if (b) {
 250                 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
 251                                          GLI_9750_MISC_RX_INV_ON);
 252         } else {
 253                 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
 254                                          GLI_9750_MISC_RX_INV_OFF);
 255         }
 256         sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
 257
 258         gl9750_wt_off(host);
 259 }
 260
 261 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
 262 {
 263         int i;
 264         int rx_inv;
 265
 266         for (rx_inv = 0; rx_inv < 2; rx_inv++) {
 267                 gli_set_9750_rx_inv(host, !!rx_inv);
 268                 sdhci_start_tuning(host);
 269
 270                 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {
 271                         u16 ctrl;
 272
 273                         sdhci_send_tuning(host, opcode);
 274
 275                         if (!host->tuning_done) {
 276                                 sdhci_abort_tuning(host, opcode);
 277                                 break;
 278                         }
 279
 280                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 281                         if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
 282                                 if (ctrl & SDHCI_CTRL_TUNED_CLK)
 283                                         return 0; /* Success! */
 284                                 break;
 285                         }
 286                 }
 287         }
 288         if (!host->tuning_done) {
 289                 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
 290                         mmc_hostname(host->mmc));
 291                 return -ETIMEDOUT;
 292         }
 293
 294         pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
 295                 mmc_hostname(host->mmc));
 296         sdhci_reset_tuning(host);
 297
 298         return -EAGAIN;
 299 }
 300
 301 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
 302 {
 303         host->mmc->retune_period = 0;
 304         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
 305                 host->mmc->retune_period = host->tuning_count;
 306
 307         gli_set_9750(host);
 308         host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
 309         sdhci_end_tuning(host);
 310
 311         return 0;
 312 }
 313
 314 static void gl9750_disable_ssc_pll(struct sdhci_host *host)
 315 {
 316         u32 pll;
 317
 318         gl9750_wt_on(host);
 319         pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
 320         pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
 321         sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
 322         gl9750_wt_off(host);
 323 }
 324
 325 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
 326 {
 327         u32 pll;
 328
 329         gl9750_wt_on(host);
 330         pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
 331         pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
 332                  SDHCI_GLI_9750_PLL_PDIV |
 333                  SDHCI_GLI_9750_PLL_DIR);
 334         pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
 335                FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
 336                FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
 337         sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
 338         gl9750_wt_off(host);
 339
 340         /* wait for pll stable */
 341         mdelay(1);
 342 }
 343
 344 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
 345 {
 346         u32 pll;
 347         u32 ssc;
 348
 349         gl9750_wt_on(host);
 350         pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
 351         ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
 352         pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
 353                  SDHCI_GLI_9750_PLLSSC_EN);
 354         ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
 355         pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
 356                FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
 357         ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
 358         sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
 359         sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
 360         gl9750_wt_off(host);
 361 }
 362
 363 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
 364 {
 365         /* set pll to 205MHz and enable ssc */
 366         gl9750_set_ssc(host, 0x1, 0x1F, 0xFFE7);
 367         gl9750_set_pll(host, 0x1, 0x246, 0x0);
 368 }
 369
 370 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
 371 {
 372         struct mmc_ios *ios = &host->mmc->ios;
 373         u16 clk;
 374
 375         host->mmc->actual_clock = 0;
 376
 377         gl9750_disable_ssc_pll(host);
 378         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 379
 380         if (clock == 0)
 381                 return;
 382
 383         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
 384         if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
 385                 host->mmc->actual_clock = 205000000;
 386                 gl9750_set_ssc_pll_205mhz(host);
 387         }
 388
 389         sdhci_enable_clk(host, clk);
 390 }
 391
 392 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
 393 {
 394         int ret;
 395
 396         ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
 397                                     PCI_IRQ_MSI | PCI_IRQ_MSIX);
 398         if (ret < 0) {
 399                 pr_warn("%s: enable PCI MSI failed, error=%d\n",
 400                        mmc_hostname(slot->host->mmc), ret);
 401                 return;
 402         }
 403
 404         slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
 405 }
 406
 407 static inline void gl9755_wt_on(struct pci_dev *pdev)
 408 {
 409         u32 wt_value;
 410         u32 wt_enable;
 411
 412         pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
 413         wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
 414
 415         if (wt_enable == GLI_9755_WT_EN_ON)
 416                 return;
 417
 418         wt_value &= ~PCI_GLI_9755_WT_EN;
 419         wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
 420
 421         pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
 422 }
 423
 424 static inline void gl9755_wt_off(struct pci_dev *pdev)
 425 {
 426         u32 wt_value;
 427         u32 wt_enable;
 428
 429         pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
 430         wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
 431
 432         if (wt_enable == GLI_9755_WT_EN_OFF)
 433                 return;
 434
 435         wt_value &= ~PCI_GLI_9755_WT_EN;
 436         wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
 437
 438         pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
 439 }
 440
 441 static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
 442 {
 443         u32 pll;
 444
 445         gl9755_wt_on(pdev);
 446         pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
 447         pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
 448         pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
 449         gl9755_wt_off(pdev);
 450 }
 451
 452 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
 453 {
 454         u32 pll;
 455
 456         gl9755_wt_on(pdev);
 457         pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
 458         pll &= ~(PCI_GLI_9755_PLL_LDIV |
 459                  PCI_GLI_9755_PLL_PDIV |
 460                  PCI_GLI_9755_PLL_DIR);
 461         pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
 462                FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
 463                FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
 464         pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
 465         gl9755_wt_off(pdev);
 466
 467         /* wait for pll stable */
 468         mdelay(1);
 469 }
 470
 471 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
 472 {
 473         u32 pll;
 474         u32 ssc;
 475
 476         gl9755_wt_on(pdev);
 477         pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
 478         pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
 479         pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
 480                  PCI_GLI_9755_PLLSSC_EN);
 481         ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
 482         pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
 483                FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
 484         ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
 485         pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
 486         pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
 487         gl9755_wt_off(pdev);
 488 }
 489
 490 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
 491 {
 492         /* set pll to 205MHz and enable ssc */
 493         gl9755_set_ssc(pdev, 0x1, 0x1F, 0xFFE7);
 494         gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
 495 }
 496
 497 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
 498 {
 499         struct sdhci_pci_slot *slot = sdhci_priv(host);
 500         struct mmc_ios *ios = &host->mmc->ios;
 501         struct pci_dev *pdev;
 502         u16 clk;
 503
 504         pdev = slot->chip->pdev;
 505         host->mmc->actual_clock = 0;
 506
 507         gl9755_disable_ssc_pll(pdev);
 508         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 509
 510         if (clock == 0)
 511                 return;
 512
 513         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
 514         if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
 515                 host->mmc->actual_clock = 205000000;
 516                 gl9755_set_ssc_pll_205mhz(pdev);
 517         }
 518
 519         sdhci_enable_clk(host, clk);
 520 }
 521
 522 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
 523 {
 524         struct sdhci_host *host = slot->host;
 525
 526         gli_pcie_enable_msi(slot);
 527         slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
 528         sdhci_enable_v4_mode(host);
 529
 530         return 0;
 531 }
 532
 533 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
 534 {
 535         struct sdhci_host *host = slot->host;
 536
 537         gli_pcie_enable_msi(slot);
 538         slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
 539         sdhci_enable_v4_mode(host);
 540
 541         return 0;
 542 }
 543
 544 static void sdhci_gli_voltage_switch(struct sdhci_host *host)
 545 {
 546         /*
 547          * According to Section 3.6.1 signal voltage switch procedure in
 548          * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
 549          * follows:
 550          * (6) Set 1.8V Signal Enable in the Host Control 2 register.
 551          * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
 552          *     period.
 553          * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
 554          *     step (12).
 555          *
 556          * Wait 5ms after set 1.8V signal enable in Host Control 2 register
 557          * to ensure 1.8V signal enable bit is set by GL9750/GL9755.
 558          *
 559          * ...however, the controller in the NUC10i3FNK4 (a 9755) requires
 560          * slightly longer than 5ms before the control register reports that
 561          * 1.8V is ready, and far longer still before the card will actually
 562          * work reliably.
 563          */
 564         usleep_range(100000, 110000);
 565 }
 566
 567 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
 568 {
 569         sdhci_reset(host, mask);
 570         gli_set_9750(host);
 571 }
 572
 573 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
 574 {
 575         u32 value;
 576
 577         value = readl(host->ioaddr + reg);
 578         if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))
 579                 value |= 0xc8;
 580
 581         return value;
 582 }
 583
 584 #ifdef CONFIG_PM_SLEEP
 585 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)
 586 {
 587         struct sdhci_pci_slot *slot = chip->slots[0];
 588
 589         pci_free_irq_vectors(slot->chip->pdev);
 590         gli_pcie_enable_msi(slot);
 591
 592         return sdhci_pci_resume_host(chip);
 593 }
 594
 595 static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip)
 596 {
 597         struct sdhci_pci_slot *slot = chip->slots[0];
 598         int ret;
 599
 600         ret = sdhci_pci_gli_resume(chip);
 601         if (ret)
 602                 return ret;
 603
 604         return cqhci_resume(slot->host->mmc);
 605 }
 606
 607 static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip)
 608 {
 609         struct sdhci_pci_slot *slot = chip->slots[0];
 610         int ret;
 611
 612         ret = cqhci_suspend(slot->host->mmc);
 613         if (ret)
 614                 return ret;
 615
 616         return sdhci_suspend_host(slot->host);
 617 }
 618 #endif
 619
 620 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,
 621                                           struct mmc_ios *ios)
 622 {
 623         struct sdhci_host *host = mmc_priv(mmc);
 624         u32 val;
 625
 626         val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
 627         if (ios->enhanced_strobe)
 628                 val |= SDHCI_GLI_9763E_HS400_ES_BIT;
 629         else
 630                 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT;
 631
 632         sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
 633 }
 634
 635 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
 636                                         unsigned int timing)
 637 {
 638         u16 ctrl_2;
 639
 640         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 641         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 642         if (timing == MMC_TIMING_MMC_HS200)
 643                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 644         else if (timing == MMC_TIMING_MMC_HS)
 645                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 646         else if (timing == MMC_TIMING_MMC_DDR52)
 647                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 648         else if (timing == MMC_TIMING_MMC_HS400)
 649                 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400;
 650
 651         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 652 }
 653
 654 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc)
 655 {
 656         sdhci_dumpregs(mmc_priv(mmc));
 657 }
 658
 659 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc)
 660 {
 661         struct cqhci_host *cq_host = mmc->cqe_private;
 662         u32 value;
 663
 664         value = cqhci_readl(cq_host, CQHCI_CFG);
 665         value |= CQHCI_ENABLE;
 666         cqhci_writel(cq_host, value, CQHCI_CFG);
 667 }
 668
 669 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc)
 670 {
 671         struct sdhci_host *host = mmc_priv(mmc);
 672
 673         sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
 674         sdhci_cqe_enable(mmc);
 675 }
 676
 677 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
 678 {
 679         int cmd_error = 0;
 680         int data_error = 0;
 681
 682         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
 683                 return intmask;
 684
 685         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
 686
 687         return 0;
 688 }
 689
 690 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc)
 691 {
 692         struct sdhci_host *host = mmc_priv(mmc);
 693         struct cqhci_host *cq_host = mmc->cqe_private;
 694         u32 value;
 695
 696         value = cqhci_readl(cq_host, CQHCI_CFG);
 697         value &= ~CQHCI_ENABLE;
 698         cqhci_writel(cq_host, value, CQHCI_CFG);
 699         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
 700 }
 701
 702 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = {
 703         .enable         = sdhci_gl9763e_cqe_enable,
 704         .disable        = sdhci_cqe_disable,
 705         .dumpregs       = sdhci_gl9763e_dumpregs,
 706         .pre_enable     = sdhci_gl9763e_cqe_pre_enable,
 707         .post_disable   = sdhci_gl9763e_cqe_post_disable,
 708 };
 709
 710 static int gl9763e_add_host(struct sdhci_pci_slot *slot)
 711 {
 712         struct device *dev = &slot->chip->pdev->dev;
 713         struct sdhci_host *host = slot->host;
 714         struct cqhci_host *cq_host;
 715         bool dma64;
 716         int ret;
 717
 718         ret = sdhci_setup_host(host);
 719         if (ret)
 720                 return ret;
 721
 722         cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
 723         if (!cq_host) {
 724                 ret = -ENOMEM;
 725                 goto cleanup;
 726         }
 727
 728         cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
 729         cq_host->ops = &sdhci_gl9763e_cqhci_ops;
 730
 731         dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
 732         if (dma64)
 733                 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
 734
 735         ret = cqhci_init(cq_host, host->mmc, dma64);
 736         if (ret)
 737                 goto cleanup;
 738
 739         ret = __sdhci_add_host(host);
 740         if (ret)
 741                 goto cleanup;
 742
 743         return 0;
 744
 745 cleanup:
 746         sdhci_cleanup_host(host);
 747         return ret;
 748 }
 749
 750 static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask)
 751 {
 752         if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) &&
 753             host->mmc->cqe_private)
 754                 cqhci_deactivate(host->mmc);
 755         sdhci_reset(host, mask);
 756 }
 757
 758 static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
 759 {
 760         struct pci_dev *pdev = slot->chip->pdev;
 761         u32 value;
 762
 763         pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
 764         value &= ~GLI_9763E_VHS_REV;
 765         value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
 766         pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
 767
 768         pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);
 769         value |= GLI_9763E_SCR_AXI_REQ;
 770         pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
 771
 772         pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
 773         value &= ~GLI_9763E_VHS_REV;
 774         value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
 775         pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
 776 }
 777
 778 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
 779 {
 780         struct pci_dev *pdev = slot->chip->pdev;
 781         struct sdhci_host *host = slot->host;
 782         u32 value;
 783
 784         host->mmc->caps |= MMC_CAP_8_BIT_DATA |
 785                            MMC_CAP_1_8V_DDR |
 786                            MMC_CAP_NONREMOVABLE;
 787         host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
 788                             MMC_CAP2_HS400_1_8V |
 789                             MMC_CAP2_HS400_ES |
 790                             MMC_CAP2_NO_SDIO |
 791                             MMC_CAP2_NO_SD;
 792
 793         pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);
 794         if (!(value & GLI_9763E_MB_CMDQ_OFF))
 795                 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
 796
 797         gli_pcie_enable_msi(slot);
 798         host->mmc_host_ops.hs400_enhanced_strobe =
 799                                         gl9763e_hs400_enhanced_strobe;
 800         gli_set_gl9763e(slot);
 801         sdhci_enable_v4_mode(host);
 802
 803         return 0;
 804 }
 805
 806 static const struct sdhci_ops sdhci_gl9755_ops = {
 807         .set_clock              = sdhci_gl9755_set_clock,
 808         .enable_dma             = sdhci_pci_enable_dma,
 809         .set_bus_width          = sdhci_set_bus_width,
 810         .reset                  = sdhci_reset,
 811         .set_uhs_signaling      = sdhci_set_uhs_signaling,
 812         .voltage_switch         = sdhci_gli_voltage_switch,
 813 };
 814
 815 const struct sdhci_pci_fixes sdhci_gl9755 = {
 816         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 817         .quirks2        = SDHCI_QUIRK2_BROKEN_DDR50,
 818         .probe_slot     = gli_probe_slot_gl9755,
 819         .ops            = &sdhci_gl9755_ops,
 820 #ifdef CONFIG_PM_SLEEP
 821         .resume         = sdhci_pci_gli_resume,
 822 #endif
 823 };
 824
 825 static const struct sdhci_ops sdhci_gl9750_ops = {
 826         .read_l                 = sdhci_gl9750_readl,
 827         .set_clock              = sdhci_gl9750_set_clock,
 828         .enable_dma             = sdhci_pci_enable_dma,
 829         .set_bus_width          = sdhci_set_bus_width,
 830         .reset                  = sdhci_gl9750_reset,
 831         .set_uhs_signaling      = sdhci_set_uhs_signaling,
 832         .voltage_switch         = sdhci_gli_voltage_switch,
 833         .platform_execute_tuning = gl9750_execute_tuning,
 834 };
 835
 836 const struct sdhci_pci_fixes sdhci_gl9750 = {
 837         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 838         .quirks2        = SDHCI_QUIRK2_BROKEN_DDR50,
 839         .probe_slot     = gli_probe_slot_gl9750,
 840         .ops            = &sdhci_gl9750_ops,
 841 #ifdef CONFIG_PM_SLEEP
 842         .resume         = sdhci_pci_gli_resume,
 843 #endif
 844 };
 845
 846 static const struct sdhci_ops sdhci_gl9763e_ops = {
 847         .set_clock              = sdhci_set_clock,
 848         .enable_dma             = sdhci_pci_enable_dma,
 849         .set_bus_width          = sdhci_set_bus_width,
 850         .reset                  = sdhci_gl9763e_reset,
 851         .set_uhs_signaling      = sdhci_set_gl9763e_signaling,
 852         .voltage_switch         = sdhci_gli_voltage_switch,
 853         .irq                    = sdhci_gl9763e_cqhci_irq,
 854 };
 855
 856 const struct sdhci_pci_fixes sdhci_gl9763e = {
 857         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 858         .probe_slot     = gli_probe_slot_gl9763e,
 859         .ops            = &sdhci_gl9763e_ops,
 860 #ifdef CONFIG_PM_SLEEP
 861         .resume         = sdhci_cqhci_gli_resume,
 862         .suspend        = sdhci_cqhci_gli_suspend,
 863 #endif
 864         .add_host       = gl9763e_add_host,
 865 };