1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
10 * Thanks to the following companies for their support:
12 * - JMicron (hardware and technical support)
15 #include <linux/bitfield.h>
16 #include <linux/string.h>
17 #include <linux/delay.h>
18 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/slab.h>
23 #include <linux/device.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/mmc.h>
26 #include <linux/scatterlist.h>
28 #include <linux/gpio.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/mmc/slot-gpio.h>
31 #include <linux/mmc/sdhci-pci-data.h>
32 #include <linux/acpi.h>
33 #include <linux/dmi.h>
38 #include "sdhci-pci.h"
40 static void sdhci_pci_hw_reset(struct sdhci_host *host);
42 #ifdef CONFIG_PM_SLEEP
43 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
45 mmc_pm_flag_t pm_flags = 0;
46 bool cap_cd_wake = false;
49 for (i = 0; i < chip->num_slots; i++) {
50 struct sdhci_pci_slot *slot = chip->slots[i];
53 pm_flags |= slot->host->mmc->pm_flags;
54 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
59 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
60 return device_wakeup_enable(&chip->pdev->dev);
61 else if (!cap_cd_wake)
62 return device_wakeup_disable(&chip->pdev->dev);
67 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
71 sdhci_pci_init_wakeup(chip);
73 for (i = 0; i < chip->num_slots; i++) {
74 struct sdhci_pci_slot *slot = chip->slots[i];
75 struct sdhci_host *host;
82 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
83 mmc_retune_needed(host->mmc);
85 ret = sdhci_suspend_host(host);
89 if (device_may_wakeup(&chip->pdev->dev))
90 mmc_gpio_set_cd_wake(host->mmc, true);
97 sdhci_resume_host(chip->slots[i]->host);
101 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
103 struct sdhci_pci_slot *slot;
106 for (i = 0; i < chip->num_slots; i++) {
107 slot = chip->slots[i];
111 ret = sdhci_resume_host(slot->host);
115 mmc_gpio_set_cd_wake(slot->host->mmc, false);
121 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
125 ret = cqhci_suspend(chip->slots[0]->host->mmc);
129 return sdhci_pci_suspend_host(chip);
132 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
136 ret = sdhci_pci_resume_host(chip);
140 return cqhci_resume(chip->slots[0]->host->mmc);
145 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
147 struct sdhci_pci_slot *slot;
148 struct sdhci_host *host;
151 for (i = 0; i < chip->num_slots; i++) {
152 slot = chip->slots[i];
158 ret = sdhci_runtime_suspend_host(host);
160 goto err_pci_runtime_suspend;
162 if (chip->rpm_retune &&
163 host->tuning_mode != SDHCI_TUNING_MODE_3)
164 mmc_retune_needed(host->mmc);
169 err_pci_runtime_suspend:
171 sdhci_runtime_resume_host(chip->slots[i]->host);
175 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
177 struct sdhci_pci_slot *slot;
180 for (i = 0; i < chip->num_slots; i++) {
181 slot = chip->slots[i];
185 ret = sdhci_runtime_resume_host(slot->host);
193 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
197 ret = cqhci_suspend(chip->slots[0]->host->mmc);
201 return sdhci_pci_runtime_suspend_host(chip);
204 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
208 ret = sdhci_pci_runtime_resume_host(chip);
212 return cqhci_resume(chip->slots[0]->host->mmc);
216 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
221 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
224 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
229 static void sdhci_pci_dumpregs(struct mmc_host *mmc)
231 sdhci_dumpregs(mmc_priv(mmc));
234 /*****************************************************************************\
236 * Hardware specific quirk handling *
238 \*****************************************************************************/
240 static int ricoh_probe(struct sdhci_pci_chip *chip)
242 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
243 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
244 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
248 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
251 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
252 & SDHCI_TIMEOUT_CLK_MASK) |
254 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
255 & SDHCI_CLOCK_BASE_MASK) |
257 SDHCI_TIMEOUT_CLK_UNIT |
264 #ifdef CONFIG_PM_SLEEP
265 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
267 /* Apply a delay to allow controller to settle */
268 /* Otherwise it becomes confused if card state changed
271 return sdhci_pci_resume_host(chip);
275 static const struct sdhci_pci_fixes sdhci_ricoh = {
276 .probe = ricoh_probe,
277 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
278 SDHCI_QUIRK_FORCE_DMA |
279 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
282 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
283 .probe_slot = ricoh_mmc_probe_slot,
284 #ifdef CONFIG_PM_SLEEP
285 .resume = ricoh_mmc_resume,
287 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
288 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
289 SDHCI_QUIRK_NO_CARD_NO_RESET |
290 SDHCI_QUIRK_MISSING_CAPS
293 static const struct sdhci_pci_fixes sdhci_ene_712 = {
294 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
295 SDHCI_QUIRK_BROKEN_DMA,
298 static const struct sdhci_pci_fixes sdhci_ene_714 = {
299 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
300 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
301 SDHCI_QUIRK_BROKEN_DMA,
304 static const struct sdhci_pci_fixes sdhci_cafe = {
305 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
306 SDHCI_QUIRK_NO_BUSY_IRQ |
307 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
308 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
311 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
312 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
315 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
317 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
322 * ADMA operation is disabled for Moorestown platform due to
325 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
328 * slots number is fixed here for MRST as SDIO3/5 are never used and
329 * have hardware bugs.
335 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
337 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
343 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
345 struct sdhci_pci_slot *slot = dev_id;
346 struct sdhci_host *host = slot->host;
348 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
352 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
354 int err, irq, gpio = slot->cd_gpio;
356 slot->cd_gpio = -EINVAL;
357 slot->cd_irq = -EINVAL;
359 if (!gpio_is_valid(gpio))
362 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
366 err = gpio_direction_input(gpio);
370 irq = gpio_to_irq(gpio);
374 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
375 IRQF_TRIGGER_FALLING, "sd_cd", slot);
379 slot->cd_gpio = gpio;
385 devm_gpio_free(&slot->chip->pdev->dev, gpio);
387 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
390 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
392 if (slot->cd_irq >= 0)
393 free_irq(slot->cd_irq, slot);
398 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
402 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
408 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
410 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
411 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
415 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
417 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
421 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
422 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
423 .probe_slot = mrst_hc_probe_slot,
426 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
427 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
428 .probe = mrst_hc_probe,
431 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
432 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
433 .allow_runtime_pm = true,
434 .own_cd_for_runtime_pm = true,
437 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
438 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
439 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
440 .allow_runtime_pm = true,
441 .probe_slot = mfd_sdio_probe_slot,
444 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
445 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
446 .allow_runtime_pm = true,
447 .probe_slot = mfd_emmc_probe_slot,
450 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
451 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
452 .probe_slot = pch_hc_probe_slot,
457 INTEL_DSM_V18_SWITCH = 3,
458 INTEL_DSM_V33_SWITCH = 4,
459 INTEL_DSM_DRV_STRENGTH = 9,
460 INTEL_DSM_D3_RETUNE = 10,
473 static const guid_t intel_dsm_guid =
474 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
475 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
477 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
478 unsigned int fn, u32 *result)
480 union acpi_object *obj;
484 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
488 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
493 len = min_t(size_t, obj->buffer.length, 4);
496 memcpy(result, obj->buffer.pointer, len);
503 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
504 unsigned int fn, u32 *result)
506 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
509 return __intel_dsm(intel_host, dev, fn, result);
512 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
513 struct mmc_host *mmc)
518 intel_host->d3_retune = true;
520 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
522 pr_debug("%s: DSM not supported, error %d\n",
523 mmc_hostname(mmc), err);
527 pr_debug("%s: DSM function mask %#x\n",
528 mmc_hostname(mmc), intel_host->dsm_fns);
530 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
531 intel_host->drv_strength = err ? 0 : val;
533 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
534 intel_host->d3_retune = err ? true : !!val;
537 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
541 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
543 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
544 /* For eMMC, minimum is 1us but give it 9us for good measure */
547 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
548 /* For eMMC, minimum is 200us but give it 300us for good measure */
549 usleep_range(300, 1000);
552 static int intel_select_drive_strength(struct mmc_card *card,
553 unsigned int max_dtr, int host_drv,
554 int card_drv, int *drv_type)
556 struct sdhci_host *host = mmc_priv(card->host);
557 struct sdhci_pci_slot *slot = sdhci_priv(host);
558 struct intel_host *intel_host = sdhci_pci_priv(slot);
560 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv))
563 return intel_host->drv_strength;
566 static int bxt_get_cd(struct mmc_host *mmc)
568 int gpio_cd = mmc_gpio_get_cd(mmc);
569 struct sdhci_host *host = mmc_priv(mmc);
576 spin_lock_irqsave(&host->lock, flags);
578 if (host->flags & SDHCI_DEVICE_DEAD)
581 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
583 spin_unlock_irqrestore(&host->lock, flags);
588 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
589 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
591 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
594 struct sdhci_pci_slot *slot = sdhci_priv(host);
595 struct intel_host *intel_host = sdhci_pci_priv(slot);
600 * Bus power may control card power, but a full reset still may not
601 * reset the power, whereas a direct write to SDHCI_POWER_CONTROL can.
602 * That might be needed to initialize correctly, if the card was left
603 * powered on previously.
605 if (intel_host->needs_pwr_off) {
606 intel_host->needs_pwr_off = false;
607 if (mode != MMC_POWER_OFF) {
608 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
609 usleep_range(10000, 12500);
613 sdhci_set_power(host, mode, vdd);
615 if (mode == MMC_POWER_OFF)
619 * Bus power might not enable after D3 -> D0 transition due to the
620 * present state not yet having propagated. Retry for up to 2ms.
622 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
623 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
624 if (reg & SDHCI_POWER_ON)
626 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
627 reg |= SDHCI_POWER_ON;
628 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
632 #define INTEL_HS400_ES_REG 0x78
633 #define INTEL_HS400_ES_BIT BIT(0)
635 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
638 struct sdhci_host *host = mmc_priv(mmc);
641 val = sdhci_readl(host, INTEL_HS400_ES_REG);
642 if (ios->enhanced_strobe)
643 val |= INTEL_HS400_ES_BIT;
645 val &= ~INTEL_HS400_ES_BIT;
646 sdhci_writel(host, val, INTEL_HS400_ES_REG);
649 static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
652 struct device *dev = mmc_dev(mmc);
653 struct sdhci_host *host = mmc_priv(mmc);
654 struct sdhci_pci_slot *slot = sdhci_priv(host);
655 struct intel_host *intel_host = sdhci_pci_priv(slot);
660 err = sdhci_start_signal_voltage_switch(mmc, ios);
664 switch (ios->signal_voltage) {
665 case MMC_SIGNAL_VOLTAGE_330:
666 fn = INTEL_DSM_V33_SWITCH;
668 case MMC_SIGNAL_VOLTAGE_180:
669 fn = INTEL_DSM_V18_SWITCH;
675 err = intel_dsm(intel_host, dev, fn, &result);
676 pr_debug("%s: %s DSM fn %u error %d result %u\n",
677 mmc_hostname(mmc), __func__, fn, err, result);
682 static const struct sdhci_ops sdhci_intel_byt_ops = {
683 .set_clock = sdhci_set_clock,
684 .set_power = sdhci_intel_set_power,
685 .enable_dma = sdhci_pci_enable_dma,
686 .set_bus_width = sdhci_set_bus_width,
687 .reset = sdhci_reset,
688 .set_uhs_signaling = sdhci_set_uhs_signaling,
689 .hw_reset = sdhci_pci_hw_reset,
692 static const struct sdhci_ops sdhci_intel_glk_ops = {
693 .set_clock = sdhci_set_clock,
694 .set_power = sdhci_intel_set_power,
695 .enable_dma = sdhci_pci_enable_dma,
696 .set_bus_width = sdhci_set_bus_width,
697 .reset = sdhci_reset,
698 .set_uhs_signaling = sdhci_set_uhs_signaling,
699 .hw_reset = sdhci_pci_hw_reset,
700 .irq = sdhci_cqhci_irq,
703 static void byt_read_dsm(struct sdhci_pci_slot *slot)
705 struct intel_host *intel_host = sdhci_pci_priv(slot);
706 struct device *dev = &slot->chip->pdev->dev;
707 struct mmc_host *mmc = slot->host->mmc;
709 intel_dsm_init(intel_host, dev, mmc);
710 slot->chip->rpm_retune = intel_host->d3_retune;
713 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
715 int err = sdhci_execute_tuning(mmc, opcode);
716 struct sdhci_host *host = mmc_priv(mmc);
722 * Tuning can leave the IP in an active state (Buffer Read Enable bit
723 * set) which prevents the entry to low power states (i.e. S0i3). Data
724 * reset will clear it.
726 sdhci_reset(host, SDHCI_RESET_DATA);
731 static void byt_probe_slot(struct sdhci_pci_slot *slot)
733 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
737 ops->execute_tuning = intel_execute_tuning;
738 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
741 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
743 byt_probe_slot(slot);
744 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
745 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
746 MMC_CAP_CMD_DURING_TFR |
747 MMC_CAP_WAIT_WHILE_BUSY;
748 slot->hw_reset = sdhci_pci_int_hw_reset;
749 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
750 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
751 slot->host->mmc_host_ops.select_drive_strength =
752 intel_select_drive_strength;
756 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot)
758 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
759 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") ||
760 dmi_match(DMI_SYS_VENDOR, "IRBIS"));
763 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
765 int ret = byt_emmc_probe_slot(slot);
767 if (!glk_broken_cqhci(slot))
768 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
770 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
771 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
772 slot->host->mmc_host_ops.hs400_enhanced_strobe =
773 intel_hs400_enhanced_strobe;
774 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
780 static const struct cqhci_host_ops glk_cqhci_ops = {
781 .enable = sdhci_cqe_enable,
782 .disable = sdhci_cqe_disable,
783 .dumpregs = sdhci_pci_dumpregs,
786 static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
788 struct device *dev = &slot->chip->pdev->dev;
789 struct sdhci_host *host = slot->host;
790 struct cqhci_host *cq_host;
794 ret = sdhci_setup_host(host);
798 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
804 cq_host->mmio = host->ioaddr + 0x200;
805 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
806 cq_host->ops = &glk_cqhci_ops;
808 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
810 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
812 ret = cqhci_init(cq_host, host->mmc, dma64);
816 ret = __sdhci_add_host(host);
823 sdhci_cleanup_host(host);
828 #define GLK_RX_CTRL1 0x834
829 #define GLK_TUN_VAL 0x840
830 #define GLK_PATH_PLL GENMASK(13, 8)
831 #define GLK_DLY GENMASK(6, 0)
832 /* Workaround firmware failing to restore the tuning value */
833 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp)
835 struct sdhci_pci_slot *slot = chip->slots[0];
836 struct intel_host *intel_host = sdhci_pci_priv(slot);
837 struct sdhci_host *host = slot->host;
842 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc))
845 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1);
846 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL);
849 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1;
850 intel_host->glk_tun_val = glk_tun_val;
854 if (!intel_host->glk_tun_val)
857 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) {
858 intel_host->rpm_retune_ok = true;
862 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) +
863 (intel_host->glk_tun_val << 1));
864 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1))
867 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly;
868 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1);
870 intel_host->rpm_retune_ok = true;
871 chip->rpm_retune = true;
872 mmc_retune_needed(host->mmc);
873 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc));
876 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp)
878 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
880 glk_rpm_retune_wa(chip, susp);
883 static int glk_runtime_suspend(struct sdhci_pci_chip *chip)
885 glk_rpm_retune_chk(chip, true);
887 return sdhci_cqhci_runtime_suspend(chip);
890 static int glk_runtime_resume(struct sdhci_pci_chip *chip)
892 glk_rpm_retune_chk(chip, false);
894 return sdhci_cqhci_runtime_resume(chip);
899 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
902 unsigned long long max_freq;
904 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
905 "MXFQ", NULL, &max_freq);
906 if (ACPI_FAILURE(status)) {
907 dev_err(&slot->chip->pdev->dev,
908 "MXFQ not found in acpi table\n");
912 slot->host->mmc->f_max = max_freq * 1000000;
917 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
923 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
927 byt_probe_slot(slot);
929 err = ni_set_max_freq(slot);
933 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
934 MMC_CAP_WAIT_WHILE_BUSY;
938 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
940 byt_probe_slot(slot);
941 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
942 MMC_CAP_WAIT_WHILE_BUSY;
946 static void byt_needs_pwr_off(struct sdhci_pci_slot *slot)
948 struct intel_host *intel_host = sdhci_pci_priv(slot);
949 u8 reg = sdhci_readb(slot->host, SDHCI_POWER_CONTROL);
951 intel_host->needs_pwr_off = reg & SDHCI_POWER_ON;
954 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
956 byt_probe_slot(slot);
957 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
958 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
960 slot->cd_override_level = true;
961 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
962 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
963 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
964 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
965 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
967 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
968 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
969 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V;
971 byt_needs_pwr_off(slot);
976 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
977 .allow_runtime_pm = true,
978 .probe_slot = byt_emmc_probe_slot,
979 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
980 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
981 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
982 SDHCI_QUIRK2_STOP_WITH_TC,
983 .ops = &sdhci_intel_byt_ops,
984 .priv_size = sizeof(struct intel_host),
987 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
988 .allow_runtime_pm = true,
989 .probe_slot = glk_emmc_probe_slot,
990 .add_host = glk_emmc_add_host,
991 #ifdef CONFIG_PM_SLEEP
992 .suspend = sdhci_cqhci_suspend,
993 .resume = sdhci_cqhci_resume,
996 .runtime_suspend = glk_runtime_suspend,
997 .runtime_resume = glk_runtime_resume,
999 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1000 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1001 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1002 SDHCI_QUIRK2_STOP_WITH_TC,
1003 .ops = &sdhci_intel_glk_ops,
1004 .priv_size = sizeof(struct intel_host),
1007 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
1008 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1009 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1010 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1011 .allow_runtime_pm = true,
1012 .probe_slot = ni_byt_sdio_probe_slot,
1013 .ops = &sdhci_intel_byt_ops,
1014 .priv_size = sizeof(struct intel_host),
1017 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
1018 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1019 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1020 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1021 .allow_runtime_pm = true,
1022 .probe_slot = byt_sdio_probe_slot,
1023 .ops = &sdhci_intel_byt_ops,
1024 .priv_size = sizeof(struct intel_host),
1027 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
1028 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1029 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1030 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1031 SDHCI_QUIRK2_STOP_WITH_TC,
1032 .allow_runtime_pm = true,
1033 .own_cd_for_runtime_pm = true,
1034 .probe_slot = byt_sd_probe_slot,
1035 .ops = &sdhci_intel_byt_ops,
1036 .priv_size = sizeof(struct intel_host),
1039 /* Define Host controllers for Intel Merrifield platform */
1040 #define INTEL_MRFLD_EMMC_0 0
1041 #define INTEL_MRFLD_EMMC_1 1
1042 #define INTEL_MRFLD_SD 2
1043 #define INTEL_MRFLD_SDIO 3
1046 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
1048 struct acpi_device *device, *child;
1050 device = ACPI_COMPANION(&slot->chip->pdev->dev);
1054 acpi_device_fix_up_power(device);
1055 list_for_each_entry(child, &device->children, node)
1056 if (child->status.present && child->status.enabled)
1057 acpi_device_fix_up_power(child);
1060 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
1063 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
1065 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
1068 case INTEL_MRFLD_EMMC_0:
1069 case INTEL_MRFLD_EMMC_1:
1070 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1071 MMC_CAP_8_BIT_DATA |
1074 case INTEL_MRFLD_SD:
1075 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1077 case INTEL_MRFLD_SDIO:
1078 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
1079 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
1080 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1081 MMC_CAP_POWER_OFF_CARD;
1087 intel_mrfld_mmc_fix_up_power_slot(slot);
1091 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
1092 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1093 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
1094 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1095 .allow_runtime_pm = true,
1096 .probe_slot = intel_mrfld_mmc_probe_slot,
1099 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
1104 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
1109 * Turn PMOS on [bit 0], set over current detection to 2.4 V
1110 * [bit 1:2] and enable over current debouncing [bit 6].
1117 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
1120 static int jmicron_probe(struct sdhci_pci_chip *chip)
1125 if (chip->pdev->revision == 0) {
1126 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
1127 SDHCI_QUIRK_32BIT_DMA_SIZE |
1128 SDHCI_QUIRK_32BIT_ADMA_SIZE |
1129 SDHCI_QUIRK_RESET_AFTER_REQUEST |
1130 SDHCI_QUIRK_BROKEN_SMALL_PIO;
1134 * JMicron chips can have two interfaces to the same hardware
1135 * in order to work around limitations in Microsoft's driver.
1136 * We need to make sure we only bind to one of them.
1138 * This code assumes two things:
1140 * 1. The PCI code adds subfunctions in order.
1142 * 2. The MMC interface has a lower subfunction number
1143 * than the SD interface.
1145 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
1146 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1147 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1148 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1151 struct pci_dev *sd_dev;
1154 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
1155 mmcdev, sd_dev)) != NULL) {
1156 if ((PCI_SLOT(chip->pdev->devfn) ==
1157 PCI_SLOT(sd_dev->devfn)) &&
1158 (chip->pdev->bus == sd_dev->bus))
1163 pci_dev_put(sd_dev);
1164 dev_info(&chip->pdev->dev, "Refusing to bind to "
1165 "secondary interface.\n");
1171 * JMicron chips need a bit of a nudge to enable the power
1174 ret = jmicron_pmos(chip, 1);
1176 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1180 /* quirk for unsable RO-detection on JM388 chips */
1181 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1182 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1183 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1188 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1192 scratch = readb(host->ioaddr + 0xC0);
1199 writeb(scratch, host->ioaddr + 0xC0);
1202 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1204 if (slot->chip->pdev->revision == 0) {
1207 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1208 version = (version & SDHCI_VENDOR_VER_MASK) >>
1209 SDHCI_VENDOR_VER_SHIFT;
1212 * Older versions of the chip have lots of nasty glitches
1213 * in the ADMA engine. It's best just to avoid it
1217 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1220 /* JM388 MMC doesn't support 1.8V while SD supports it */
1221 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1222 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1223 MMC_VDD_29_30 | MMC_VDD_30_31 |
1224 MMC_VDD_165_195; /* allow 1.8V */
1225 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1226 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1230 * The secondary interface requires a bit set to get the
1233 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1234 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1235 jmicron_enable_mmc(slot->host, 1);
1237 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1242 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
1247 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1248 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1249 jmicron_enable_mmc(slot->host, 0);
1252 #ifdef CONFIG_PM_SLEEP
1253 static int jmicron_suspend(struct sdhci_pci_chip *chip)
1257 ret = sdhci_pci_suspend_host(chip);
1261 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1262 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1263 for (i = 0; i < chip->num_slots; i++)
1264 jmicron_enable_mmc(chip->slots[i]->host, 0);
1270 static int jmicron_resume(struct sdhci_pci_chip *chip)
1274 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1275 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1276 for (i = 0; i < chip->num_slots; i++)
1277 jmicron_enable_mmc(chip->slots[i]->host, 1);
1280 ret = jmicron_pmos(chip, 1);
1282 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1286 return sdhci_pci_resume_host(chip);
1290 static const struct sdhci_pci_fixes sdhci_o2 = {
1291 .probe = sdhci_pci_o2_probe,
1292 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1293 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
1294 .probe_slot = sdhci_pci_o2_probe_slot,
1295 #ifdef CONFIG_PM_SLEEP
1296 .resume = sdhci_pci_o2_resume,
1300 static const struct sdhci_pci_fixes sdhci_jmicron = {
1301 .probe = jmicron_probe,
1303 .probe_slot = jmicron_probe_slot,
1304 .remove_slot = jmicron_remove_slot,
1306 #ifdef CONFIG_PM_SLEEP
1307 .suspend = jmicron_suspend,
1308 .resume = jmicron_resume,
1312 /* SysKonnect CardBus2SDIO extra registers */
1313 #define SYSKT_CTRL 0x200
1314 #define SYSKT_RDFIFO_STAT 0x204
1315 #define SYSKT_WRFIFO_STAT 0x208
1316 #define SYSKT_POWER_DATA 0x20c
1317 #define SYSKT_POWER_330 0xef
1318 #define SYSKT_POWER_300 0xf8
1319 #define SYSKT_POWER_184 0xcc
1320 #define SYSKT_POWER_CMD 0x20d
1321 #define SYSKT_POWER_START (1 << 7)
1322 #define SYSKT_POWER_STATUS 0x20e
1323 #define SYSKT_POWER_STATUS_OK (1 << 0)
1324 #define SYSKT_BOARD_REV 0x210
1325 #define SYSKT_CHIP_REV 0x211
1326 #define SYSKT_CONF_DATA 0x212
1327 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1328 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1329 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1331 static int syskt_probe(struct sdhci_pci_chip *chip)
1333 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1334 chip->pdev->class &= ~0x0000FF;
1335 chip->pdev->class |= PCI_SDHCI_IFDMA;
1340 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1344 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1345 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1346 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1347 "board rev %d.%d, chip rev %d.%d\n",
1348 board_rev >> 4, board_rev & 0xf,
1349 chip_rev >> 4, chip_rev & 0xf);
1350 if (chip_rev >= 0x20)
1351 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1353 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1354 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1356 tm = 10; /* Wait max 1 ms */
1358 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1359 if (ps & SYSKT_POWER_STATUS_OK)
1364 dev_err(&slot->chip->pdev->dev,
1365 "power regulator never stabilized");
1366 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1373 static const struct sdhci_pci_fixes sdhci_syskt = {
1374 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1375 .probe = syskt_probe,
1376 .probe_slot = syskt_probe_slot,
1379 static int via_probe(struct sdhci_pci_chip *chip)
1381 if (chip->pdev->revision == 0x10)
1382 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1387 static const struct sdhci_pci_fixes sdhci_via = {
1391 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1393 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1397 static const struct sdhci_pci_fixes sdhci_rtsx = {
1398 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1399 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1400 SDHCI_QUIRK2_BROKEN_DDR50,
1401 .probe_slot = rtsx_probe_slot,
1404 /*AMD chipset generation*/
1405 enum amd_chipset_gen {
1406 AMD_CHIPSET_BEFORE_ML,
1409 AMD_CHIPSET_UNKNOWN,
1413 #define AMD_SD_AUTO_PATTERN 0xB8
1414 #define AMD_MSLEEP_DURATION 4
1415 #define AMD_SD_MISC_CONTROL 0xD0
1416 #define AMD_MAX_TUNE_VALUE 0x0B
1417 #define AMD_AUTO_TUNE_SEL 0x10800
1418 #define AMD_FIFO_PTR 0x30
1419 #define AMD_BIT_MASK 0x1F
1421 static void amd_tuning_reset(struct sdhci_host *host)
1425 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1426 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1427 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1429 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1430 val &= ~SDHCI_CTRL_EXEC_TUNING;
1431 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1434 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1438 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1439 val &= ~AMD_BIT_MASK;
1440 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1441 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1444 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1448 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1449 val |= AMD_FIFO_PTR;
1450 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1453 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode)
1455 struct sdhci_pci_slot *slot = sdhci_priv(host);
1456 struct pci_dev *pdev = slot->chip->pdev;
1458 u8 valid_win_max = 0;
1459 u8 valid_win_end = 0;
1460 u8 ctrl, tune_around;
1462 amd_tuning_reset(host);
1464 for (tune_around = 0; tune_around < 12; tune_around++) {
1465 amd_config_tuning_phase(pdev, tune_around);
1467 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1469 msleep(AMD_MSLEEP_DURATION);
1470 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1471 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1472 } else if (++valid_win > valid_win_max) {
1473 valid_win_max = valid_win;
1474 valid_win_end = tune_around;
1478 if (!valid_win_max) {
1479 dev_err(&pdev->dev, "no tuning point found\n");
1483 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1485 amd_enable_manual_tuning(pdev);
1487 host->mmc->retune_period = 0;
1492 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode)
1494 struct sdhci_host *host = mmc_priv(mmc);
1496 /* AMD requires custom HS200 tuning */
1497 if (host->timing == MMC_TIMING_MMC_HS200)
1498 return amd_execute_tuning_hs200(host, opcode);
1500 /* Otherwise perform standard SDHCI tuning */
1501 return sdhci_execute_tuning(mmc, opcode);
1504 static int amd_probe_slot(struct sdhci_pci_slot *slot)
1506 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
1508 ops->execute_tuning = amd_execute_tuning;
1513 static int amd_probe(struct sdhci_pci_chip *chip)
1515 struct pci_dev *smbus_dev;
1516 enum amd_chipset_gen gen;
1518 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1519 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1521 gen = AMD_CHIPSET_BEFORE_ML;
1523 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1524 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1526 if (smbus_dev->revision < 0x51)
1527 gen = AMD_CHIPSET_CZ;
1529 gen = AMD_CHIPSET_NL;
1531 gen = AMD_CHIPSET_UNKNOWN;
1535 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1536 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1541 static const struct sdhci_ops amd_sdhci_pci_ops = {
1542 .set_clock = sdhci_set_clock,
1543 .enable_dma = sdhci_pci_enable_dma,
1544 .set_bus_width = sdhci_set_bus_width,
1545 .reset = sdhci_reset,
1546 .set_uhs_signaling = sdhci_set_uhs_signaling,
1549 static const struct sdhci_pci_fixes sdhci_amd = {
1551 .ops = &amd_sdhci_pci_ops,
1552 .probe_slot = amd_probe_slot,
1555 static const struct pci_device_id pci_ids[] = {
1556 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1557 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1558 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1559 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1560 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1561 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1562 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1563 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1564 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1565 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1566 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1567 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1568 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1569 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1570 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1571 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1572 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1573 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1574 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1575 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1576 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1577 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1578 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1579 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1580 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1581 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1582 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1583 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1584 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1585 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1586 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1587 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1588 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1589 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1590 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1591 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1592 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1593 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1594 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1595 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1596 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1597 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1598 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1599 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1600 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1601 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
1602 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1603 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1604 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1605 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1606 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1607 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1608 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1609 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1610 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1611 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1612 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1613 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1614 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1615 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1616 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1617 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc),
1618 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd),
1619 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc),
1620 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd),
1621 SDHCI_PCI_DEVICE(O2, 8120, o2),
1622 SDHCI_PCI_DEVICE(O2, 8220, o2),
1623 SDHCI_PCI_DEVICE(O2, 8221, o2),
1624 SDHCI_PCI_DEVICE(O2, 8320, o2),
1625 SDHCI_PCI_DEVICE(O2, 8321, o2),
1626 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1627 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1628 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1629 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1630 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1631 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
1632 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
1633 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1634 /* Generic SD host controller */
1635 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1636 { /* end: all zeroes */ },
1639 MODULE_DEVICE_TABLE(pci, pci_ids);
1641 /*****************************************************************************\
1643 * SDHCI core callbacks *
1645 \*****************************************************************************/
1647 int sdhci_pci_enable_dma(struct sdhci_host *host)
1649 struct sdhci_pci_slot *slot;
1650 struct pci_dev *pdev;
1652 slot = sdhci_priv(host);
1653 pdev = slot->chip->pdev;
1655 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1656 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1657 (host->flags & SDHCI_USE_SDMA)) {
1658 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1659 "doesn't fully claim to support it.\n");
1662 pci_set_master(pdev);
1667 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1669 struct sdhci_pci_slot *slot = sdhci_priv(host);
1670 int rst_n_gpio = slot->rst_n_gpio;
1672 if (!gpio_is_valid(rst_n_gpio))
1674 gpio_set_value_cansleep(rst_n_gpio, 0);
1675 /* For eMMC, minimum is 1us but give it 10us for good measure */
1677 gpio_set_value_cansleep(rst_n_gpio, 1);
1678 /* For eMMC, minimum is 200us but give it 300us for good measure */
1679 usleep_range(300, 1000);
1682 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1684 struct sdhci_pci_slot *slot = sdhci_priv(host);
1687 slot->hw_reset(host);
1690 static const struct sdhci_ops sdhci_pci_ops = {
1691 .set_clock = sdhci_set_clock,
1692 .enable_dma = sdhci_pci_enable_dma,
1693 .set_bus_width = sdhci_set_bus_width,
1694 .reset = sdhci_reset,
1695 .set_uhs_signaling = sdhci_set_uhs_signaling,
1696 .hw_reset = sdhci_pci_hw_reset,
1699 /*****************************************************************************\
1703 \*****************************************************************************/
1705 #ifdef CONFIG_PM_SLEEP
1706 static int sdhci_pci_suspend(struct device *dev)
1708 struct pci_dev *pdev = to_pci_dev(dev);
1709 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1714 if (chip->fixes && chip->fixes->suspend)
1715 return chip->fixes->suspend(chip);
1717 return sdhci_pci_suspend_host(chip);
1720 static int sdhci_pci_resume(struct device *dev)
1722 struct pci_dev *pdev = to_pci_dev(dev);
1723 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1728 if (chip->fixes && chip->fixes->resume)
1729 return chip->fixes->resume(chip);
1731 return sdhci_pci_resume_host(chip);
1736 static int sdhci_pci_runtime_suspend(struct device *dev)
1738 struct pci_dev *pdev = to_pci_dev(dev);
1739 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1744 if (chip->fixes && chip->fixes->runtime_suspend)
1745 return chip->fixes->runtime_suspend(chip);
1747 return sdhci_pci_runtime_suspend_host(chip);
1750 static int sdhci_pci_runtime_resume(struct device *dev)
1752 struct pci_dev *pdev = to_pci_dev(dev);
1753 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1758 if (chip->fixes && chip->fixes->runtime_resume)
1759 return chip->fixes->runtime_resume(chip);
1761 return sdhci_pci_runtime_resume_host(chip);
1765 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1766 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1767 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1768 sdhci_pci_runtime_resume, NULL)
1771 /*****************************************************************************\
1773 * Device probing/removal *
1775 \*****************************************************************************/
1777 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1778 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1781 struct sdhci_pci_slot *slot;
1782 struct sdhci_host *host;
1783 int ret, bar = first_bar + slotno;
1784 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1786 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1787 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1788 return ERR_PTR(-ENODEV);
1791 if (pci_resource_len(pdev, bar) < 0x100) {
1792 dev_err(&pdev->dev, "Invalid iomem size. You may "
1793 "experience problems.\n");
1796 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1797 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1798 return ERR_PTR(-ENODEV);
1801 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1802 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1803 return ERR_PTR(-ENODEV);
1806 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1808 dev_err(&pdev->dev, "cannot allocate host\n");
1809 return ERR_CAST(host);
1812 slot = sdhci_priv(host);
1816 slot->rst_n_gpio = -EINVAL;
1817 slot->cd_gpio = -EINVAL;
1820 /* Retrieve platform data if there is any */
1821 if (*sdhci_pci_get_data)
1822 slot->data = sdhci_pci_get_data(pdev, slotno);
1825 if (slot->data->setup) {
1826 ret = slot->data->setup(slot->data);
1828 dev_err(&pdev->dev, "platform setup failed\n");
1832 slot->rst_n_gpio = slot->data->rst_n_gpio;
1833 slot->cd_gpio = slot->data->cd_gpio;
1836 host->hw_name = "PCI";
1837 host->ops = chip->fixes && chip->fixes->ops ?
1840 host->quirks = chip->quirks;
1841 host->quirks2 = chip->quirks2;
1843 host->irq = pdev->irq;
1845 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1847 dev_err(&pdev->dev, "cannot request region\n");
1851 host->ioaddr = pcim_iomap_table(pdev)[bar];
1853 if (chip->fixes && chip->fixes->probe_slot) {
1854 ret = chip->fixes->probe_slot(slot);
1859 if (gpio_is_valid(slot->rst_n_gpio)) {
1860 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1861 gpio_direction_output(slot->rst_n_gpio, 1);
1862 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1863 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1865 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1866 slot->rst_n_gpio = -EINVAL;
1870 host->mmc->pm_caps = MMC_PM_KEEP_POWER;
1871 host->mmc->slotno = slotno;
1872 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1874 if (device_can_wakeup(&pdev->dev))
1875 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1877 if (host->mmc->caps & MMC_CAP_CD_WAKE)
1878 device_init_wakeup(&pdev->dev, true);
1880 if (slot->cd_idx >= 0) {
1881 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx,
1882 slot->cd_override_level, 0, NULL);
1883 if (ret && ret != -EPROBE_DEFER)
1884 ret = mmc_gpiod_request_cd(host->mmc, NULL,
1886 slot->cd_override_level,
1888 if (ret == -EPROBE_DEFER)
1892 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1897 if (chip->fixes && chip->fixes->add_host)
1898 ret = chip->fixes->add_host(slot);
1900 ret = sdhci_add_host(host);
1904 sdhci_pci_add_own_cd(slot);
1907 * Check if the chip needs a separate GPIO for card detect to wake up
1908 * from runtime suspend. If it is not there, don't allow runtime PM.
1909 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1911 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1912 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1913 chip->allow_runtime_pm = false;
1918 if (chip->fixes && chip->fixes->remove_slot)
1919 chip->fixes->remove_slot(slot, 0);
1922 if (slot->data && slot->data->cleanup)
1923 slot->data->cleanup(slot->data);
1926 sdhci_free_host(host);
1928 return ERR_PTR(ret);
1931 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1936 sdhci_pci_remove_own_cd(slot);
1939 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1940 if (scratch == (u32)-1)
1943 sdhci_remove_host(slot->host, dead);
1945 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1946 slot->chip->fixes->remove_slot(slot, dead);
1948 if (slot->data && slot->data->cleanup)
1949 slot->data->cleanup(slot->data);
1951 sdhci_free_host(slot->host);
1954 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1956 pm_suspend_ignore_children(dev, 1);
1957 pm_runtime_set_autosuspend_delay(dev, 50);
1958 pm_runtime_use_autosuspend(dev);
1959 pm_runtime_allow(dev);
1960 /* Stay active until mmc core scans for a card */
1961 pm_runtime_put_noidle(dev);
1964 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1966 pm_runtime_forbid(dev);
1967 pm_runtime_get_noresume(dev);
1970 static int sdhci_pci_probe(struct pci_dev *pdev,
1971 const struct pci_device_id *ent)
1973 struct sdhci_pci_chip *chip;
1974 struct sdhci_pci_slot *slot;
1976 u8 slots, first_bar;
1979 BUG_ON(pdev == NULL);
1980 BUG_ON(ent == NULL);
1982 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1983 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1985 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1989 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1990 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1994 BUG_ON(slots > MAX_SLOTS);
1996 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
2000 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
2002 if (first_bar > 5) {
2003 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
2007 ret = pcim_enable_device(pdev);
2011 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
2016 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
2018 chip->quirks = chip->fixes->quirks;
2019 chip->quirks2 = chip->fixes->quirks2;
2020 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
2022 chip->num_slots = slots;
2023 chip->pm_retune = true;
2024 chip->rpm_retune = true;
2026 pci_set_drvdata(pdev, chip);
2028 if (chip->fixes && chip->fixes->probe) {
2029 ret = chip->fixes->probe(chip);
2034 slots = chip->num_slots; /* Quirk may have changed this */
2036 for (i = 0; i < slots; i++) {
2037 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
2039 for (i--; i >= 0; i--)
2040 sdhci_pci_remove_slot(chip->slots[i]);
2041 return PTR_ERR(slot);
2044 chip->slots[i] = slot;
2047 if (chip->allow_runtime_pm)
2048 sdhci_pci_runtime_pm_allow(&pdev->dev);
2053 static void sdhci_pci_remove(struct pci_dev *pdev)
2056 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
2058 if (chip->allow_runtime_pm)
2059 sdhci_pci_runtime_pm_forbid(&pdev->dev);
2061 for (i = 0; i < chip->num_slots; i++)
2062 sdhci_pci_remove_slot(chip->slots[i]);
2065 static struct pci_driver sdhci_driver = {
2066 .name = "sdhci-pci",
2067 .id_table = pci_ids,
2068 .probe = sdhci_pci_probe,
2069 .remove = sdhci_pci_remove,
2071 .pm = &sdhci_pci_pm_ops
2075 module_pci_driver(sdhci_driver);
2077 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2078 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2079 MODULE_LICENSE("GPL");