2 * Freescale eSDHC controller driver.
4 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
7 * Authors: Xiaobo Xie <X.Xie@freescale.com>
8 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
16 #include <linux/err.h>
19 #include <linux/of_address.h>
20 #include <linux/delay.h>
21 #include <linux/module.h>
22 #include <linux/sys_soc.h>
23 #include <linux/clk.h>
24 #include <linux/ktime.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/mmc/host.h>
27 #include "sdhci-pltfm.h"
28 #include "sdhci-esdhc.h"
30 #define VENDOR_V_22 0x12
31 #define VENDOR_V_23 0x13
36 bool quirk_incorrect_hostver;
37 unsigned int peripheral_clock;
41 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
42 * to make it compatible with SD spec.
44 * @host: pointer to sdhci_host
45 * @spec_reg: SD spec register address
46 * @value: 32bit eSDHC register value on spec_reg address
48 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
49 * registers are 32 bits. There are differences in register size, register
50 * address, register function, bit position and function between eSDHC spec
53 * Return a fixed up register value
55 static u32 esdhc_readl_fixup(struct sdhci_host *host,
56 int spec_reg, u32 value)
58 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
59 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
63 * The bit of ADMA flag in eSDHC is not compatible with standard
64 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
66 * And for many FSL eSDHC controller, the reset value of field
67 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA,
68 * only these vendor version is greater than 2.2/0x12 support ADMA.
70 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
71 if (esdhc->vendor_ver > VENDOR_V_22) {
72 ret = value | SDHCI_CAN_DO_ADMA2;
77 * The DAT[3:0] line signal levels and the CMD line signal level are
78 * not compatible with standard SDHC register. The line signal levels
79 * DAT[7:0] are at bits 31:24 and the command line signal level is at
80 * bit 23. All other bits are the same as in the standard SDHC
83 if (spec_reg == SDHCI_PRESENT_STATE) {
84 ret = value & 0x000fffff;
85 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
86 ret |= (value << 1) & SDHCI_CMD_LVL;
91 * DTS properties of mmc host are used to enable each speed mode
92 * according to soc and board capability. So clean up
93 * SDR50/SDR104/DDR50 support bits here.
95 if (spec_reg == SDHCI_CAPABILITIES_1) {
96 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
105 static u16 esdhc_readw_fixup(struct sdhci_host *host,
106 int spec_reg, u32 value)
108 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
109 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
111 int shift = (spec_reg & 0x2) * 8;
113 if (spec_reg == SDHCI_HOST_VERSION)
114 ret = value & 0xffff;
116 ret = (value >> shift) & 0xffff;
117 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect
118 * vendor version and spec version information.
120 if ((spec_reg == SDHCI_HOST_VERSION) &&
121 (esdhc->quirk_incorrect_hostver))
122 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
126 static u8 esdhc_readb_fixup(struct sdhci_host *host,
127 int spec_reg, u32 value)
131 int shift = (spec_reg & 0x3) * 8;
133 ret = (value >> shift) & 0xff;
136 * "DMA select" locates at offset 0x28 in SD specification, but on
137 * P5020 or P3041, it locates at 0x29.
139 if (spec_reg == SDHCI_HOST_CONTROL) {
140 /* DMA select is 22,23 bits in Protocol Control Register */
141 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
142 /* fixup the result */
143 ret &= ~SDHCI_CTRL_DMA_MASK;
150 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be
151 * written into eSDHC register.
153 * @host: pointer to sdhci_host
154 * @spec_reg: SD spec register address
155 * @value: 8/16/32bit SD spec register value that would be written
156 * @old_value: 32bit eSDHC register value on spec_reg address
158 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
159 * registers are 32 bits. There are differences in register size, register
160 * address, register function, bit position and function between eSDHC spec
163 * Return a fixed up register value
165 static u32 esdhc_writel_fixup(struct sdhci_host *host,
166 int spec_reg, u32 value, u32 old_value)
171 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
172 * when SYSCTL[RSTD] is set for some special operations.
173 * No any impact on other operation.
175 if (spec_reg == SDHCI_INT_ENABLE)
176 ret = value | SDHCI_INT_BLK_GAP;
183 static u32 esdhc_writew_fixup(struct sdhci_host *host,
184 int spec_reg, u16 value, u32 old_value)
186 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
187 int shift = (spec_reg & 0x2) * 8;
191 case SDHCI_TRANSFER_MODE:
193 * Postpone this write, we must do it together with a
194 * command write that is down below. Return old value.
196 pltfm_host->xfer_mode_shadow = value;
199 ret = (value << 16) | pltfm_host->xfer_mode_shadow;
203 ret = old_value & (~(0xffff << shift));
204 ret |= (value << shift);
206 if (spec_reg == SDHCI_BLOCK_SIZE) {
208 * Two last DMA bits are reserved, and first one is used for
209 * non-standard blksz of 4096 bytes that we don't support
210 * yet. So clear the DMA boundary bits.
212 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
217 static u32 esdhc_writeb_fixup(struct sdhci_host *host,
218 int spec_reg, u8 value, u32 old_value)
223 int shift = (spec_reg & 0x3) * 8;
226 * eSDHC doesn't have a standard power control register, so we do
227 * nothing here to avoid incorrect operation.
229 if (spec_reg == SDHCI_POWER_CONTROL)
232 * "DMA select" location is offset 0x28 in SD specification, but on
233 * P5020 or P3041, it's located at 0x29.
235 if (spec_reg == SDHCI_HOST_CONTROL) {
237 * If host control register is not standard, exit
240 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
243 /* DMA select is 22,23 bits in Protocol Control Register */
244 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
245 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
246 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
247 (old_value & SDHCI_CTRL_DMA_MASK);
248 ret = (ret & (~0xff)) | tmp;
250 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */
251 ret &= ~ESDHC_HOST_CONTROL_RES;
255 ret = (old_value & (~(0xff << shift))) | (value << shift);
259 static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
264 if (reg == SDHCI_CAPABILITIES_1)
265 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
267 value = ioread32be(host->ioaddr + reg);
269 ret = esdhc_readl_fixup(host, reg, value);
274 static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
279 if (reg == SDHCI_CAPABILITIES_1)
280 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
282 value = ioread32(host->ioaddr + reg);
284 ret = esdhc_readl_fixup(host, reg, value);
289 static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
293 int base = reg & ~0x3;
295 value = ioread32be(host->ioaddr + base);
296 ret = esdhc_readw_fixup(host, reg, value);
300 static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
304 int base = reg & ~0x3;
306 value = ioread32(host->ioaddr + base);
307 ret = esdhc_readw_fixup(host, reg, value);
311 static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
315 int base = reg & ~0x3;
317 value = ioread32be(host->ioaddr + base);
318 ret = esdhc_readb_fixup(host, reg, value);
322 static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
326 int base = reg & ~0x3;
328 value = ioread32(host->ioaddr + base);
329 ret = esdhc_readb_fixup(host, reg, value);
333 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
337 value = esdhc_writel_fixup(host, reg, val, 0);
338 iowrite32be(value, host->ioaddr + reg);
341 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
345 value = esdhc_writel_fixup(host, reg, val, 0);
346 iowrite32(value, host->ioaddr + reg);
349 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
351 int base = reg & ~0x3;
355 value = ioread32be(host->ioaddr + base);
356 ret = esdhc_writew_fixup(host, reg, val, value);
357 if (reg != SDHCI_TRANSFER_MODE)
358 iowrite32be(ret, host->ioaddr + base);
361 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
363 int base = reg & ~0x3;
367 value = ioread32(host->ioaddr + base);
368 ret = esdhc_writew_fixup(host, reg, val, value);
369 if (reg != SDHCI_TRANSFER_MODE)
370 iowrite32(ret, host->ioaddr + base);
373 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
375 int base = reg & ~0x3;
379 value = ioread32be(host->ioaddr + base);
380 ret = esdhc_writeb_fixup(host, reg, val, value);
381 iowrite32be(ret, host->ioaddr + base);
384 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
386 int base = reg & ~0x3;
390 value = ioread32(host->ioaddr + base);
391 ret = esdhc_writeb_fixup(host, reg, val, value);
392 iowrite32(ret, host->ioaddr + base);
396 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
397 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
398 * and Block Gap Event(IRQSTAT[BGE]) are also set.
399 * For Continue, apply soft reset for data(SYSCTL[RSTD]);
400 * and re-issue the entire read transaction from beginning.
402 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
404 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
405 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
410 applicable = (intmask & SDHCI_INT_DATA_END) &&
411 (intmask & SDHCI_INT_BLK_GAP) &&
412 (esdhc->vendor_ver == VENDOR_V_23);
416 host->data->error = 0;
417 dmastart = sg_dma_address(host->data->sg);
418 dmanow = dmastart + host->data->bytes_xfered;
420 * Force update to the next DMA block boundary.
422 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
423 SDHCI_DEFAULT_BOUNDARY_SIZE;
424 host->data->bytes_xfered = dmanow - dmastart;
425 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
428 static int esdhc_of_enable_dma(struct sdhci_host *host)
431 struct device *dev = mmc_dev(host->mmc);
433 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") ||
434 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc"))
435 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
437 value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
439 if (of_dma_is_coherent(dev->of_node))
440 value |= ESDHC_DMA_SNOOP;
442 value &= ~ESDHC_DMA_SNOOP;
444 sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
448 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
450 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
451 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
453 if (esdhc->peripheral_clock)
454 return esdhc->peripheral_clock;
456 return pltfm_host->clock;
459 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
461 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
462 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
465 if (esdhc->peripheral_clock)
466 clock = esdhc->peripheral_clock;
468 clock = pltfm_host->clock;
469 return clock / 256 / 16;
472 static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
477 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
480 val |= ESDHC_CLOCK_SDCLKEN;
482 val &= ~ESDHC_CLOCK_SDCLKEN;
484 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
487 timeout = ktime_add_ms(ktime_get(), 20);
488 val = ESDHC_CLOCK_STABLE;
490 bool timedout = ktime_after(ktime_get(), timeout);
492 if (sdhci_readl(host, ESDHC_PRSSTAT) & val)
495 pr_err("%s: Internal clock never stabilised.\n",
496 mmc_hostname(host->mmc));
503 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
505 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
506 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
512 host->mmc->actual_clock = 0;
515 esdhc_clock_enable(host, false);
519 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
520 if (esdhc->vendor_ver < VENDOR_V_23)
524 * Limit SD clock to 167MHz for ls1046a according to its datasheet
526 if (clock > 167000000 &&
527 of_find_compatible_node(NULL, NULL, "fsl,ls1046a-esdhc"))
531 * Limit SD clock to 125MHz for ls1012a according to its datasheet
533 if (clock > 125000000 &&
534 of_find_compatible_node(NULL, NULL, "fsl,ls1012a-esdhc"))
537 /* Workaround to reduce the clock frequency for p1010 esdhc */
538 if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
539 if (clock > 20000000)
541 if (clock > 40000000)
545 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
546 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
547 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
548 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
550 while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
553 while (host->max_clk / pre_div / div > clock && div < 16)
556 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
557 clock, host->max_clk / pre_div / div);
558 host->mmc->actual_clock = host->max_clk / pre_div / div;
562 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
563 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
564 | (div << ESDHC_DIVIDER_SHIFT)
565 | (pre_div << ESDHC_PREDIV_SHIFT));
566 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
569 timeout = ktime_add_ms(ktime_get(), 20);
571 bool timedout = ktime_after(ktime_get(), timeout);
573 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
576 pr_err("%s: Internal clock never stabilised.\n",
577 mmc_hostname(host->mmc));
583 temp |= ESDHC_CLOCK_SDCLKEN;
584 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
587 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
591 ctrl = sdhci_readl(host, ESDHC_PROCTL);
592 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
594 case MMC_BUS_WIDTH_8:
595 ctrl |= ESDHC_CTRL_8BITBUS;
598 case MMC_BUS_WIDTH_4:
599 ctrl |= ESDHC_CTRL_4BITBUS;
606 sdhci_writel(host, ctrl, ESDHC_PROCTL);
609 static void esdhc_reset(struct sdhci_host *host, u8 mask)
613 sdhci_reset(host, mask);
615 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
616 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
618 if (mask & SDHCI_RESET_ALL) {
619 val = sdhci_readl(host, ESDHC_TBCTL);
621 sdhci_writel(host, val, ESDHC_TBCTL);
625 /* The SCFG, Supplemental Configuration Unit, provides SoC specific
626 * configuration and status registers for the device. There is a
627 * SDHC IO VSEL control register on SCFG for some platforms. It's
628 * used to support SDHC IO voltage switching.
630 static const struct of_device_id scfg_device_ids[] = {
631 { .compatible = "fsl,t1040-scfg", },
632 { .compatible = "fsl,ls1012a-scfg", },
633 { .compatible = "fsl,ls1046a-scfg", },
637 /* SDHC IO VSEL control register definition */
638 #define SCFG_SDHCIOVSELCR 0x408
639 #define SDHCIOVSELCR_TGLEN 0x80000000
640 #define SDHCIOVSELCR_VSELVAL 0x60000000
641 #define SDHCIOVSELCR_SDHC_VS 0x00000001
643 static int esdhc_signal_voltage_switch(struct mmc_host *mmc,
646 struct sdhci_host *host = mmc_priv(mmc);
647 struct device_node *scfg_node;
648 void __iomem *scfg_base = NULL;
653 * Signal Voltage Switching is only applicable for Host Controllers
656 if (host->version < SDHCI_SPEC_300)
659 val = sdhci_readl(host, ESDHC_PROCTL);
661 switch (ios->signal_voltage) {
662 case MMC_SIGNAL_VOLTAGE_330:
663 val &= ~ESDHC_VOLT_SEL;
664 sdhci_writel(host, val, ESDHC_PROCTL);
666 case MMC_SIGNAL_VOLTAGE_180:
667 scfg_node = of_find_matching_node(NULL, scfg_device_ids);
669 scfg_base = of_iomap(scfg_node, 0);
671 sdhciovselcr = SDHCIOVSELCR_TGLEN |
672 SDHCIOVSELCR_VSELVAL;
673 iowrite32be(sdhciovselcr,
674 scfg_base + SCFG_SDHCIOVSELCR);
676 val |= ESDHC_VOLT_SEL;
677 sdhci_writel(host, val, ESDHC_PROCTL);
680 sdhciovselcr = SDHCIOVSELCR_TGLEN |
681 SDHCIOVSELCR_SDHC_VS;
682 iowrite32be(sdhciovselcr,
683 scfg_base + SCFG_SDHCIOVSELCR);
686 val |= ESDHC_VOLT_SEL;
687 sdhci_writel(host, val, ESDHC_PROCTL);
695 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
697 struct sdhci_host *host = mmc_priv(mmc);
700 /* Use tuning block for tuning procedure */
701 esdhc_clock_enable(host, false);
702 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
703 val |= ESDHC_FLUSH_ASYNC_FIFO;
704 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
706 val = sdhci_readl(host, ESDHC_TBCTL);
708 sdhci_writel(host, val, ESDHC_TBCTL);
709 esdhc_clock_enable(host, true);
711 return sdhci_execute_tuning(mmc, opcode);
714 #ifdef CONFIG_PM_SLEEP
715 static u32 esdhc_proctl;
716 static int esdhc_of_suspend(struct device *dev)
718 struct sdhci_host *host = dev_get_drvdata(dev);
720 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
722 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
723 mmc_retune_needed(host->mmc);
725 return sdhci_suspend_host(host);
728 static int esdhc_of_resume(struct device *dev)
730 struct sdhci_host *host = dev_get_drvdata(dev);
731 int ret = sdhci_resume_host(host);
734 /* Isn't this already done by sdhci_resume_host() ? --rmk */
735 esdhc_of_enable_dma(host);
736 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
742 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops,
746 static const struct sdhci_ops sdhci_esdhc_be_ops = {
747 .read_l = esdhc_be_readl,
748 .read_w = esdhc_be_readw,
749 .read_b = esdhc_be_readb,
750 .write_l = esdhc_be_writel,
751 .write_w = esdhc_be_writew,
752 .write_b = esdhc_be_writeb,
753 .set_clock = esdhc_of_set_clock,
754 .enable_dma = esdhc_of_enable_dma,
755 .get_max_clock = esdhc_of_get_max_clock,
756 .get_min_clock = esdhc_of_get_min_clock,
757 .adma_workaround = esdhc_of_adma_workaround,
758 .set_bus_width = esdhc_pltfm_set_bus_width,
759 .reset = esdhc_reset,
760 .set_uhs_signaling = sdhci_set_uhs_signaling,
763 static const struct sdhci_ops sdhci_esdhc_le_ops = {
764 .read_l = esdhc_le_readl,
765 .read_w = esdhc_le_readw,
766 .read_b = esdhc_le_readb,
767 .write_l = esdhc_le_writel,
768 .write_w = esdhc_le_writew,
769 .write_b = esdhc_le_writeb,
770 .set_clock = esdhc_of_set_clock,
771 .enable_dma = esdhc_of_enable_dma,
772 .get_max_clock = esdhc_of_get_max_clock,
773 .get_min_clock = esdhc_of_get_min_clock,
774 .adma_workaround = esdhc_of_adma_workaround,
775 .set_bus_width = esdhc_pltfm_set_bus_width,
776 .reset = esdhc_reset,
777 .set_uhs_signaling = sdhci_set_uhs_signaling,
780 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
781 .quirks = ESDHC_DEFAULT_QUIRKS |
783 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
785 SDHCI_QUIRK_NO_CARD_NO_RESET |
786 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
787 .ops = &sdhci_esdhc_be_ops,
790 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
791 .quirks = ESDHC_DEFAULT_QUIRKS |
792 SDHCI_QUIRK_NO_CARD_NO_RESET |
793 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
794 .ops = &sdhci_esdhc_le_ops,
797 static struct soc_device_attribute soc_incorrect_hostver[] = {
798 { .family = "QorIQ T4240", .revision = "1.0", },
799 { .family = "QorIQ T4240", .revision = "2.0", },
803 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
805 struct sdhci_pltfm_host *pltfm_host;
806 struct sdhci_esdhc *esdhc;
807 struct device_node *np;
812 pltfm_host = sdhci_priv(host);
813 esdhc = sdhci_pltfm_priv(pltfm_host);
815 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
816 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
817 SDHCI_VENDOR_VER_SHIFT;
818 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
819 if (soc_device_match(soc_incorrect_hostver))
820 esdhc->quirk_incorrect_hostver = true;
822 esdhc->quirk_incorrect_hostver = false;
824 np = pdev->dev.of_node;
825 clk = of_clk_get(np, 0);
828 * esdhc->peripheral_clock would be assigned with a value
829 * which is eSDHC base clock when use periperal clock.
830 * For ls1046a, the clock value got by common clk API is
831 * peripheral clock while the eSDHC base clock is 1/2
834 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc"))
835 esdhc->peripheral_clock = clk_get_rate(clk) / 2;
837 esdhc->peripheral_clock = clk_get_rate(clk);
842 if (esdhc->peripheral_clock) {
843 esdhc_clock_enable(host, false);
844 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
845 val |= ESDHC_PERIPHERAL_CLK_SEL;
846 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
847 esdhc_clock_enable(host, true);
851 static int sdhci_esdhc_probe(struct platform_device *pdev)
853 struct sdhci_host *host;
854 struct device_node *np;
855 struct sdhci_pltfm_host *pltfm_host;
856 struct sdhci_esdhc *esdhc;
859 np = pdev->dev.of_node;
861 if (of_property_read_bool(np, "little-endian"))
862 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
863 sizeof(struct sdhci_esdhc));
865 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
866 sizeof(struct sdhci_esdhc));
869 return PTR_ERR(host);
871 host->mmc_host_ops.start_signal_voltage_switch =
872 esdhc_signal_voltage_switch;
873 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
874 host->tuning_delay = 1;
876 esdhc_init(pdev, host);
878 sdhci_get_of_property(pdev);
880 pltfm_host = sdhci_priv(host);
881 esdhc = sdhci_pltfm_priv(pltfm_host);
882 if (esdhc->vendor_ver == VENDOR_V_22)
883 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
885 if (esdhc->vendor_ver > VENDOR_V_22)
886 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
888 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) {
889 host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
890 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
893 if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
894 of_device_is_compatible(np, "fsl,p5020-esdhc") ||
895 of_device_is_compatible(np, "fsl,p4080-esdhc") ||
896 of_device_is_compatible(np, "fsl,p1020-esdhc") ||
897 of_device_is_compatible(np, "fsl,t1040-esdhc"))
898 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
900 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
901 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
903 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
905 * Freescale messed up with P2020 as it has a non-standard
906 * host control register
908 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
911 /* call to generic mmc_of_parse to support additional capabilities */
912 ret = mmc_of_parse(host->mmc);
916 mmc_of_parse_voltage(np, &host->ocr_mask);
918 ret = sdhci_add_host(host);
924 sdhci_pltfm_free(pdev);
928 static const struct of_device_id sdhci_esdhc_of_match[] = {
929 { .compatible = "fsl,mpc8379-esdhc" },
930 { .compatible = "fsl,mpc8536-esdhc" },
931 { .compatible = "fsl,esdhc" },
934 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
936 static struct platform_driver sdhci_esdhc_driver = {
938 .name = "sdhci-esdhc",
939 .of_match_table = sdhci_esdhc_of_match,
940 .pm = &esdhc_of_dev_pm_ops,
942 .probe = sdhci_esdhc_probe,
943 .remove = sdhci_pltfm_unregister,
946 module_platform_driver(sdhci_esdhc_driver);
948 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
949 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
950 "Anton Vorontsov <avorontsov@ru.mvista.com>");
951 MODULE_LICENSE("GPL v2");