2 * Freescale eSDHC controller driver.
4 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
7 * Authors: Xiaobo Xie <X.Xie@freescale.com>
8 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
16 #include <linux/err.h>
19 #include <linux/delay.h>
20 #include <linux/module.h>
21 #include <linux/mmc/host.h>
22 #include "sdhci-pltfm.h"
23 #include "sdhci-esdhc.h"
25 #define VENDOR_V_22 0x12
26 #define VENDOR_V_23 0x13
34 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
35 * to make it compatible with SD spec.
37 * @host: pointer to sdhci_host
38 * @spec_reg: SD spec register address
39 * @value: 32bit eSDHC register value on spec_reg address
41 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
42 * registers are 32 bits. There are differences in register size, register
43 * address, register function, bit position and function between eSDHC spec
46 * Return a fixed up register value
48 static u32 esdhc_readl_fixup(struct sdhci_host *host,
49 int spec_reg, u32 value)
51 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
52 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
56 * The bit of ADMA flag in eSDHC is not compatible with standard
57 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
59 * And for many FSL eSDHC controller, the reset value of field
60 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA,
61 * only these vendor version is greater than 2.2/0x12 support ADMA.
63 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
64 if (esdhc->vendor_ver > VENDOR_V_22) {
65 ret = value | SDHCI_CAN_DO_ADMA2;
70 * The DAT[3:0] line signal levels and the CMD line signal level are
71 * not compatible with standard SDHC register. The line signal levels
72 * DAT[7:0] are at bits 31:24 and the command line signal level is at
73 * bit 23. All other bits are the same as in the standard SDHC
76 if (spec_reg == SDHCI_PRESENT_STATE) {
77 ret = value & 0x000fffff;
78 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
79 ret |= (value << 1) & SDHCI_CMD_LVL;
87 static u16 esdhc_readw_fixup(struct sdhci_host *host,
88 int spec_reg, u32 value)
91 int shift = (spec_reg & 0x2) * 8;
93 if (spec_reg == SDHCI_HOST_VERSION)
96 ret = (value >> shift) & 0xffff;
100 static u8 esdhc_readb_fixup(struct sdhci_host *host,
101 int spec_reg, u32 value)
105 int shift = (spec_reg & 0x3) * 8;
107 ret = (value >> shift) & 0xff;
110 * "DMA select" locates at offset 0x28 in SD specification, but on
111 * P5020 or P3041, it locates at 0x29.
113 if (spec_reg == SDHCI_HOST_CONTROL) {
114 /* DMA select is 22,23 bits in Protocol Control Register */
115 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
116 /* fixup the result */
117 ret &= ~SDHCI_CTRL_DMA_MASK;
124 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be
125 * written into eSDHC register.
127 * @host: pointer to sdhci_host
128 * @spec_reg: SD spec register address
129 * @value: 8/16/32bit SD spec register value that would be written
130 * @old_value: 32bit eSDHC register value on spec_reg address
132 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
133 * registers are 32 bits. There are differences in register size, register
134 * address, register function, bit position and function between eSDHC spec
137 * Return a fixed up register value
139 static u32 esdhc_writel_fixup(struct sdhci_host *host,
140 int spec_reg, u32 value, u32 old_value)
145 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
146 * when SYSCTL[RSTD] is set for some special operations.
147 * No any impact on other operation.
149 if (spec_reg == SDHCI_INT_ENABLE)
150 ret = value | SDHCI_INT_BLK_GAP;
157 static u32 esdhc_writew_fixup(struct sdhci_host *host,
158 int spec_reg, u16 value, u32 old_value)
160 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
161 int shift = (spec_reg & 0x2) * 8;
165 case SDHCI_TRANSFER_MODE:
167 * Postpone this write, we must do it together with a
168 * command write that is down below. Return old value.
170 pltfm_host->xfer_mode_shadow = value;
173 ret = (value << 16) | pltfm_host->xfer_mode_shadow;
177 ret = old_value & (~(0xffff << shift));
178 ret |= (value << shift);
180 if (spec_reg == SDHCI_BLOCK_SIZE) {
182 * Two last DMA bits are reserved, and first one is used for
183 * non-standard blksz of 4096 bytes that we don't support
184 * yet. So clear the DMA boundary bits.
186 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
191 static u32 esdhc_writeb_fixup(struct sdhci_host *host,
192 int spec_reg, u8 value, u32 old_value)
197 int shift = (spec_reg & 0x3) * 8;
200 * eSDHC doesn't have a standard power control register, so we do
201 * nothing here to avoid incorrect operation.
203 if (spec_reg == SDHCI_POWER_CONTROL)
206 * "DMA select" location is offset 0x28 in SD specification, but on
207 * P5020 or P3041, it's located at 0x29.
209 if (spec_reg == SDHCI_HOST_CONTROL) {
211 * If host control register is not standard, exit
214 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
217 /* DMA select is 22,23 bits in Protocol Control Register */
218 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
219 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
220 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
221 (old_value & SDHCI_CTRL_DMA_MASK);
222 ret = (ret & (~0xff)) | tmp;
224 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */
225 ret &= ~ESDHC_HOST_CONTROL_RES;
229 ret = (old_value & (~(0xff << shift))) | (value << shift);
233 static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
238 value = ioread32be(host->ioaddr + reg);
239 ret = esdhc_readl_fixup(host, reg, value);
244 static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
249 value = ioread32(host->ioaddr + reg);
250 ret = esdhc_readl_fixup(host, reg, value);
255 static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
259 int base = reg & ~0x3;
261 value = ioread32be(host->ioaddr + base);
262 ret = esdhc_readw_fixup(host, reg, value);
266 static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
270 int base = reg & ~0x3;
272 value = ioread32(host->ioaddr + base);
273 ret = esdhc_readw_fixup(host, reg, value);
277 static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
281 int base = reg & ~0x3;
283 value = ioread32be(host->ioaddr + base);
284 ret = esdhc_readb_fixup(host, reg, value);
288 static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
292 int base = reg & ~0x3;
294 value = ioread32(host->ioaddr + base);
295 ret = esdhc_readb_fixup(host, reg, value);
299 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
303 value = esdhc_writel_fixup(host, reg, val, 0);
304 iowrite32be(value, host->ioaddr + reg);
307 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
311 value = esdhc_writel_fixup(host, reg, val, 0);
312 iowrite32(value, host->ioaddr + reg);
315 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
317 int base = reg & ~0x3;
321 value = ioread32be(host->ioaddr + base);
322 ret = esdhc_writew_fixup(host, reg, val, value);
323 if (reg != SDHCI_TRANSFER_MODE)
324 iowrite32be(ret, host->ioaddr + base);
327 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
329 int base = reg & ~0x3;
333 value = ioread32(host->ioaddr + base);
334 ret = esdhc_writew_fixup(host, reg, val, value);
335 if (reg != SDHCI_TRANSFER_MODE)
336 iowrite32(ret, host->ioaddr + base);
339 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
341 int base = reg & ~0x3;
345 value = ioread32be(host->ioaddr + base);
346 ret = esdhc_writeb_fixup(host, reg, val, value);
347 iowrite32be(ret, host->ioaddr + base);
350 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
352 int base = reg & ~0x3;
356 value = ioread32(host->ioaddr + base);
357 ret = esdhc_writeb_fixup(host, reg, val, value);
358 iowrite32(ret, host->ioaddr + base);
362 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
363 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
364 * and Block Gap Event(IRQSTAT[BGE]) are also set.
365 * For Continue, apply soft reset for data(SYSCTL[RSTD]);
366 * and re-issue the entire read transaction from beginning.
368 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
370 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
371 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
376 applicable = (intmask & SDHCI_INT_DATA_END) &&
377 (intmask & SDHCI_INT_BLK_GAP) &&
378 (esdhc->vendor_ver == VENDOR_V_23);
382 host->data->error = 0;
383 dmastart = sg_dma_address(host->data->sg);
384 dmanow = dmastart + host->data->bytes_xfered;
386 * Force update to the next DMA block boundary.
388 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
389 SDHCI_DEFAULT_BOUNDARY_SIZE;
390 host->data->bytes_xfered = dmanow - dmastart;
391 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
394 static int esdhc_of_enable_dma(struct sdhci_host *host)
398 value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
399 value |= ESDHC_DMA_SNOOP;
400 sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
404 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
406 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
408 return pltfm_host->clock;
411 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
413 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
415 return pltfm_host->clock / 256 / 16;
418 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
420 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
421 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
426 host->mmc->actual_clock = 0;
431 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
432 if (esdhc->vendor_ver < VENDOR_V_23)
436 * Limit SD clock to 167MHz for ls1046a according to its datasheet
438 if (clock > 167000000 &&
439 of_find_compatible_node(NULL, NULL, "fsl,ls1046a-esdhc"))
443 * Limit SD clock to 125MHz for ls1012a according to its datasheet
445 if (clock > 125000000 &&
446 of_find_compatible_node(NULL, NULL, "fsl,ls1012a-esdhc"))
449 /* Workaround to reduce the clock frequency for p1010 esdhc */
450 if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
451 if (clock > 20000000)
453 if (clock > 40000000)
457 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
458 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
460 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
462 while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
465 while (host->max_clk / pre_div / div > clock && div < 16)
468 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
469 clock, host->max_clk / pre_div / div);
470 host->mmc->actual_clock = host->max_clk / pre_div / div;
474 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
475 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
476 | (div << ESDHC_DIVIDER_SHIFT)
477 | (pre_div << ESDHC_PREDIV_SHIFT));
478 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
482 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
486 ctrl = sdhci_readl(host, ESDHC_PROCTL);
487 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
489 case MMC_BUS_WIDTH_8:
490 ctrl |= ESDHC_CTRL_8BITBUS;
493 case MMC_BUS_WIDTH_4:
494 ctrl |= ESDHC_CTRL_4BITBUS;
501 sdhci_writel(host, ctrl, ESDHC_PROCTL);
504 static void esdhc_reset(struct sdhci_host *host, u8 mask)
506 sdhci_reset(host, mask);
508 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
509 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
512 #ifdef CONFIG_PM_SLEEP
513 static u32 esdhc_proctl;
514 static int esdhc_of_suspend(struct device *dev)
516 struct sdhci_host *host = dev_get_drvdata(dev);
518 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
520 return sdhci_suspend_host(host);
523 static int esdhc_of_resume(struct device *dev)
525 struct sdhci_host *host = dev_get_drvdata(dev);
526 int ret = sdhci_resume_host(host);
529 /* Isn't this already done by sdhci_resume_host() ? --rmk */
530 esdhc_of_enable_dma(host);
531 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
537 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops,
541 static const struct sdhci_ops sdhci_esdhc_be_ops = {
542 .read_l = esdhc_be_readl,
543 .read_w = esdhc_be_readw,
544 .read_b = esdhc_be_readb,
545 .write_l = esdhc_be_writel,
546 .write_w = esdhc_be_writew,
547 .write_b = esdhc_be_writeb,
548 .set_clock = esdhc_of_set_clock,
549 .enable_dma = esdhc_of_enable_dma,
550 .get_max_clock = esdhc_of_get_max_clock,
551 .get_min_clock = esdhc_of_get_min_clock,
552 .adma_workaround = esdhc_of_adma_workaround,
553 .set_bus_width = esdhc_pltfm_set_bus_width,
554 .reset = esdhc_reset,
555 .set_uhs_signaling = sdhci_set_uhs_signaling,
558 static const struct sdhci_ops sdhci_esdhc_le_ops = {
559 .read_l = esdhc_le_readl,
560 .read_w = esdhc_le_readw,
561 .read_b = esdhc_le_readb,
562 .write_l = esdhc_le_writel,
563 .write_w = esdhc_le_writew,
564 .write_b = esdhc_le_writeb,
565 .set_clock = esdhc_of_set_clock,
566 .enable_dma = esdhc_of_enable_dma,
567 .get_max_clock = esdhc_of_get_max_clock,
568 .get_min_clock = esdhc_of_get_min_clock,
569 .adma_workaround = esdhc_of_adma_workaround,
570 .set_bus_width = esdhc_pltfm_set_bus_width,
571 .reset = esdhc_reset,
572 .set_uhs_signaling = sdhci_set_uhs_signaling,
575 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
576 .quirks = ESDHC_DEFAULT_QUIRKS |
578 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
580 SDHCI_QUIRK_NO_CARD_NO_RESET |
581 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
582 .ops = &sdhci_esdhc_be_ops,
585 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
586 .quirks = ESDHC_DEFAULT_QUIRKS |
587 SDHCI_QUIRK_NO_CARD_NO_RESET |
588 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
589 .ops = &sdhci_esdhc_le_ops,
592 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
594 struct sdhci_pltfm_host *pltfm_host;
595 struct sdhci_esdhc *esdhc;
598 pltfm_host = sdhci_priv(host);
599 esdhc = sdhci_pltfm_priv(pltfm_host);
601 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
602 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
603 SDHCI_VENDOR_VER_SHIFT;
604 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
607 static int sdhci_esdhc_probe(struct platform_device *pdev)
609 struct sdhci_host *host;
610 struct device_node *np;
611 struct sdhci_pltfm_host *pltfm_host;
612 struct sdhci_esdhc *esdhc;
615 np = pdev->dev.of_node;
617 if (of_property_read_bool(np, "little-endian"))
618 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
619 sizeof(struct sdhci_esdhc));
621 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
622 sizeof(struct sdhci_esdhc));
625 return PTR_ERR(host);
627 esdhc_init(pdev, host);
629 sdhci_get_of_property(pdev);
631 pltfm_host = sdhci_priv(host);
632 esdhc = sdhci_pltfm_priv(pltfm_host);
633 if (esdhc->vendor_ver == VENDOR_V_22)
634 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
636 if (esdhc->vendor_ver > VENDOR_V_22)
637 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
639 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) {
640 host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
641 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
644 if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
645 of_device_is_compatible(np, "fsl,p5020-esdhc") ||
646 of_device_is_compatible(np, "fsl,p4080-esdhc") ||
647 of_device_is_compatible(np, "fsl,p1020-esdhc") ||
648 of_device_is_compatible(np, "fsl,t1040-esdhc"))
649 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
651 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
652 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
654 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
656 * Freescale messed up with P2020 as it has a non-standard
657 * host control register
659 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
662 /* call to generic mmc_of_parse to support additional capabilities */
663 ret = mmc_of_parse(host->mmc);
667 mmc_of_parse_voltage(np, &host->ocr_mask);
669 ret = sdhci_add_host(host);
675 sdhci_pltfm_free(pdev);
679 static const struct of_device_id sdhci_esdhc_of_match[] = {
680 { .compatible = "fsl,mpc8379-esdhc" },
681 { .compatible = "fsl,mpc8536-esdhc" },
682 { .compatible = "fsl,esdhc" },
685 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
687 static struct platform_driver sdhci_esdhc_driver = {
689 .name = "sdhci-esdhc",
690 .of_match_table = sdhci_esdhc_of_match,
691 .pm = &esdhc_of_dev_pm_ops,
693 .probe = sdhci_esdhc_probe,
694 .remove = sdhci_pltfm_unregister,
697 module_platform_driver(sdhci_esdhc_driver);
699 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
700 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
701 "Anton Vorontsov <avorontsov@ru.mvista.com>");
702 MODULE_LICENSE("GPL v2");