1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller
5 * Copyright (C) 2018 Synaptics Incorporated
7 * Author: Jisheng Zhang <jszhang@kernel.org>
10 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
15 #include <linux/sizes.h>
17 #include "sdhci-pltfm.h"
19 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)
21 /* DWCMSHC specific Mode Select value */
22 #define DWCMSHC_CTRL_HS400 0x7
24 #define BOUNDARY_OK(addr, len) \
25 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
32 * If DMA addr spans 128MB boundary, we split the DMA transfer into two
33 * so that each DMA transfer doesn't exceed the boundary.
35 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
36 dma_addr_t addr, int len, unsigned int cmd)
40 if (likely(!len || BOUNDARY_OK(addr, len))) {
41 sdhci_adma_write_desc(host, desc, addr, len, cmd);
45 offset = addr & (SZ_128M - 1);
46 tmplen = SZ_128M - offset;
47 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
51 sdhci_adma_write_desc(host, desc, addr, len, cmd);
54 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
55 struct mmc_request *mrq)
57 struct sdhci_host *host = mmc_priv(mmc);
60 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit
61 * block count register which doesn't support stuff bits of
62 * CMD23 argument on dwcmsch host controller.
64 if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF))
65 host->flags &= ~SDHCI_AUTO_CMD23;
67 host->flags |= SDHCI_AUTO_CMD23;
70 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)
72 dwcmshc_check_auto_cmd23(mmc, mrq);
74 sdhci_request(mmc, mrq);
77 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
82 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
83 /* Select Bus Speed Mode for host */
84 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
85 if ((timing == MMC_TIMING_MMC_HS200) ||
86 (timing == MMC_TIMING_UHS_SDR104))
87 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
88 else if (timing == MMC_TIMING_UHS_SDR12)
89 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
90 else if ((timing == MMC_TIMING_UHS_SDR25) ||
91 (timing == MMC_TIMING_MMC_HS))
92 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
93 else if (timing == MMC_TIMING_UHS_SDR50)
94 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
95 else if ((timing == MMC_TIMING_UHS_DDR50) ||
96 (timing == MMC_TIMING_MMC_DDR52))
97 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
98 else if (timing == MMC_TIMING_MMC_HS400)
99 ctrl_2 |= DWCMSHC_CTRL_HS400;
100 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
103 static const struct sdhci_ops sdhci_dwcmshc_ops = {
104 .set_clock = sdhci_set_clock,
105 .set_bus_width = sdhci_set_bus_width,
106 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
107 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
108 .reset = sdhci_reset,
109 .adma_write_desc = dwcmshc_adma_write_desc,
112 static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
113 .ops = &sdhci_dwcmshc_ops,
114 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
115 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
118 static int dwcmshc_probe(struct platform_device *pdev)
120 struct sdhci_pltfm_host *pltfm_host;
121 struct sdhci_host *host;
122 struct dwcmshc_priv *priv;
126 host = sdhci_pltfm_init(pdev, &sdhci_dwcmshc_pdata,
127 sizeof(struct dwcmshc_priv));
129 return PTR_ERR(host);
132 * extra adma table cnt for cross 128M boundary handling.
134 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
135 if (extra > SDHCI_MAX_SEGS)
136 extra = SDHCI_MAX_SEGS;
137 host->adma_table_cnt += extra;
139 pltfm_host = sdhci_priv(host);
140 priv = sdhci_pltfm_priv(pltfm_host);
142 pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
143 if (IS_ERR(pltfm_host->clk)) {
144 err = PTR_ERR(pltfm_host->clk);
145 dev_err(&pdev->dev, "failed to get core clk: %d\n", err);
148 err = clk_prepare_enable(pltfm_host->clk);
152 priv->bus_clk = devm_clk_get(&pdev->dev, "bus");
153 if (!IS_ERR(priv->bus_clk))
154 clk_prepare_enable(priv->bus_clk);
156 err = mmc_of_parse(host->mmc);
160 sdhci_get_of_property(pdev);
162 host->mmc_host_ops.request = dwcmshc_request;
164 err = sdhci_add_host(host);
171 clk_disable_unprepare(pltfm_host->clk);
172 clk_disable_unprepare(priv->bus_clk);
174 sdhci_pltfm_free(pdev);
178 static int dwcmshc_remove(struct platform_device *pdev)
180 struct sdhci_host *host = platform_get_drvdata(pdev);
181 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
182 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
184 sdhci_remove_host(host, 0);
186 clk_disable_unprepare(pltfm_host->clk);
187 clk_disable_unprepare(priv->bus_clk);
189 sdhci_pltfm_free(pdev);
194 #ifdef CONFIG_PM_SLEEP
195 static int dwcmshc_suspend(struct device *dev)
197 struct sdhci_host *host = dev_get_drvdata(dev);
198 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
199 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
202 ret = sdhci_suspend_host(host);
206 clk_disable_unprepare(pltfm_host->clk);
207 if (!IS_ERR(priv->bus_clk))
208 clk_disable_unprepare(priv->bus_clk);
213 static int dwcmshc_resume(struct device *dev)
215 struct sdhci_host *host = dev_get_drvdata(dev);
216 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
217 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
220 ret = clk_prepare_enable(pltfm_host->clk);
224 if (!IS_ERR(priv->bus_clk)) {
225 ret = clk_prepare_enable(priv->bus_clk);
230 return sdhci_resume_host(host);
234 static SIMPLE_DEV_PM_OPS(dwcmshc_pmops, dwcmshc_suspend, dwcmshc_resume);
236 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
237 { .compatible = "snps,dwcmshc-sdhci" },
240 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
242 static struct platform_driver sdhci_dwcmshc_driver = {
244 .name = "sdhci-dwcmshc",
245 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
246 .of_match_table = sdhci_dwcmshc_dt_ids,
247 .pm = &dwcmshc_pmops,
249 .probe = dwcmshc_probe,
250 .remove = dwcmshc_remove,
252 module_platform_driver(sdhci_dwcmshc_driver);
254 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");
255 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
256 MODULE_LICENSE("GPL v2");