2 * Atmel SDMMC controller driver.
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
21 #include <linux/kernel.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/slot-gpio.h>
24 #include <linux/module.h>
26 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
30 #include "sdhci-pltfm.h"
32 #define SDMMC_MC1R 0x204
33 #define SDMMC_MC1R_DDR BIT(3)
34 #define SDMMC_MC1R_FCD BIT(7)
35 #define SDMMC_CACR 0x230
36 #define SDMMC_CACR_CAPWREN BIT(0)
37 #define SDMMC_CACR_KEY (0x46 << 8)
39 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
41 struct sdhci_at91_priv {
47 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
51 mc1r = readb(host->ioaddr + SDMMC_MC1R);
52 mc1r |= SDMMC_MC1R_FCD;
53 writeb(mc1r, host->ioaddr + SDMMC_MC1R);
56 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
59 unsigned long timeout;
61 host->mmc->actual_clock = 0;
64 * There is no requirement to disable the internal clock before
65 * changing the SD clock configuration. Moreover, disabling the
66 * internal clock, changing the configuration and re-enabling the
67 * internal clock causes some bugs. It can prevent to get the internal
68 * clock stable flag ready and an unexpected switch to the base clock
71 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
72 clk &= SDHCI_CLOCK_INT_EN;
73 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
78 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
80 clk |= SDHCI_CLOCK_INT_EN;
81 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
85 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
86 & SDHCI_CLOCK_INT_STABLE)) {
88 pr_err("%s: Internal clock never stabilised.\n",
89 mmc_hostname(host->mmc));
96 clk |= SDHCI_CLOCK_CARD_EN;
97 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
101 * In this specific implementation of the SDHCI controller, the power register
102 * needs to have a valid voltage set even when the power supply is managed by
103 * an external regulator.
105 static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
108 if (!IS_ERR(host->mmc->supply.vmmc)) {
109 struct mmc_host *mmc = host->mmc;
111 spin_unlock_irq(&host->lock);
112 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
113 spin_lock_irq(&host->lock);
115 sdhci_set_power_noreg(host, mode, vdd);
118 void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, unsigned int timing)
120 if (timing == MMC_TIMING_MMC_DDR52)
121 sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
122 sdhci_set_uhs_signaling(host, timing);
125 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
127 sdhci_reset(host, mask);
129 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
130 || mmc_gpio_get_cd(host->mmc) >= 0)
131 sdhci_at91_set_force_card_detect(host);
134 static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
135 .set_clock = sdhci_at91_set_clock,
136 .set_bus_width = sdhci_set_bus_width,
137 .reset = sdhci_at91_reset,
138 .set_uhs_signaling = sdhci_at91_set_uhs_signaling,
139 .set_power = sdhci_at91_set_power,
142 static const struct sdhci_pltfm_data soc_data_sama5d2 = {
143 .ops = &sdhci_at91_sama5d2_ops,
146 static const struct of_device_id sdhci_at91_dt_match[] = {
147 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
152 static int sdhci_at91_runtime_suspend(struct device *dev)
154 struct sdhci_host *host = dev_get_drvdata(dev);
155 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
156 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
159 ret = sdhci_runtime_suspend_host(host);
161 clk_disable_unprepare(priv->gck);
162 clk_disable_unprepare(priv->hclock);
163 clk_disable_unprepare(priv->mainck);
168 static int sdhci_at91_runtime_resume(struct device *dev)
170 struct sdhci_host *host = dev_get_drvdata(dev);
171 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
172 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
175 ret = clk_prepare_enable(priv->mainck);
177 dev_err(dev, "can't enable mainck\n");
181 ret = clk_prepare_enable(priv->hclock);
183 dev_err(dev, "can't enable hclock\n");
187 ret = clk_prepare_enable(priv->gck);
189 dev_err(dev, "can't enable gck\n");
193 return sdhci_runtime_resume_host(host);
195 #endif /* CONFIG_PM */
197 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
198 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
199 pm_runtime_force_resume)
200 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
201 sdhci_at91_runtime_resume,
205 static int sdhci_at91_probe(struct platform_device *pdev)
207 const struct of_device_id *match;
208 const struct sdhci_pltfm_data *soc_data;
209 struct sdhci_host *host;
210 struct sdhci_pltfm_host *pltfm_host;
211 struct sdhci_at91_priv *priv;
212 unsigned int caps0, caps1;
213 unsigned int clk_base, clk_mul;
214 unsigned int gck_rate, real_gck_rate;
216 unsigned int preset_div;
218 match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
221 soc_data = match->data;
223 host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
225 return PTR_ERR(host);
227 pltfm_host = sdhci_priv(host);
228 priv = sdhci_pltfm_priv(pltfm_host);
230 priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
231 if (IS_ERR(priv->mainck)) {
232 dev_err(&pdev->dev, "failed to get baseclk\n");
233 return PTR_ERR(priv->mainck);
236 priv->hclock = devm_clk_get(&pdev->dev, "hclock");
237 if (IS_ERR(priv->hclock)) {
238 dev_err(&pdev->dev, "failed to get hclock\n");
239 return PTR_ERR(priv->hclock);
242 priv->gck = devm_clk_get(&pdev->dev, "multclk");
243 if (IS_ERR(priv->gck)) {
244 dev_err(&pdev->dev, "failed to get multclk\n");
245 return PTR_ERR(priv->gck);
249 * The mult clock is provided by as a generated clock by the PMC
250 * controller. In order to set the rate of gck, we have to get the
251 * base clock rate and the clock mult from capabilities.
253 clk_prepare_enable(priv->hclock);
254 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
255 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
256 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
257 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
258 gck_rate = clk_base * 1000000 * (clk_mul + 1);
259 ret = clk_set_rate(priv->gck, gck_rate);
261 dev_err(&pdev->dev, "failed to set gck");
262 goto hclock_disable_unprepare;
265 * We need to check if we have the requested rate for gck because in
266 * some cases this rate could be not supported. If it happens, the rate
267 * is the closest one gck can provide. We have to update the value
270 real_gck_rate = clk_get_rate(priv->gck);
271 if (real_gck_rate != gck_rate) {
272 clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
273 caps1 &= (~SDHCI_CLOCK_MUL_MASK);
274 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK);
275 /* Set capabilities in r/w mode. */
276 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
277 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
278 /* Set capabilities in ro mode. */
279 writel(0, host->ioaddr + SDMMC_CACR);
280 dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n",
281 clk_mul, real_gck_rate);
285 * We have to set preset values because it depends on the clk_mul
286 * value. Moreover, SDR104 is supported in a degraded mode since the
287 * maximum sd clock value is 120 MHz instead of 208 MHz. For that
288 * reason, we need to use presets to support SDR104.
290 preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
291 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
292 host->ioaddr + SDHCI_PRESET_FOR_SDR12);
293 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
294 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
295 host->ioaddr + SDHCI_PRESET_FOR_SDR25);
296 preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
297 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
298 host->ioaddr + SDHCI_PRESET_FOR_SDR50);
299 preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
300 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
301 host->ioaddr + SDHCI_PRESET_FOR_SDR104);
302 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
303 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
304 host->ioaddr + SDHCI_PRESET_FOR_DDR50);
306 clk_prepare_enable(priv->mainck);
307 clk_prepare_enable(priv->gck);
309 ret = mmc_of_parse(host->mmc);
311 goto clocks_disable_unprepare;
313 sdhci_get_of_property(pdev);
315 pm_runtime_get_noresume(&pdev->dev);
316 pm_runtime_set_active(&pdev->dev);
317 pm_runtime_enable(&pdev->dev);
318 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
319 pm_runtime_use_autosuspend(&pdev->dev);
321 /* HS200 is broken at this moment */
322 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
324 ret = sdhci_add_host(host);
326 goto pm_runtime_disable;
329 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
330 * the assumption that all the clocks of the controller are disabled.
331 * It means we can't get irq from it when it is runtime suspended.
332 * For that reason, it is not planned to wake-up on a card detect irq
333 * from the controller.
334 * If we want to use runtime PM and to be able to wake-up on card
335 * insertion, we have to use a GPIO for the card detection or we can
336 * use polling. Be aware that using polling will resume/suspend the
337 * controller between each attempt.
338 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
339 * to enable polling via device tree with broken-cd property.
341 if (mmc_card_is_removable(host->mmc) &&
342 mmc_gpio_get_cd(host->mmc) < 0) {
343 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
344 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
348 * If the device attached to the MMC bus is not removable, it is safer
349 * to set the Force Card Detect bit. People often don't connect the
350 * card detect signal and use this pin for another purpose. If the card
351 * detect pin is not muxed to SDHCI controller, a default value is
352 * used. This value can be different from a SoC revision to another
353 * one. Problems come when this default value is not card present. To
354 * avoid this case, if the device is non removable then the card
355 * detection procedure using the SDMCC_CD signal is bypassed.
356 * This bit is reset when a software reset for all command is performed
357 * so we need to implement our own reset function to set back this bit.
359 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
361 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
362 || mmc_gpio_get_cd(host->mmc) >= 0)
363 sdhci_at91_set_force_card_detect(host);
365 pm_runtime_put_autosuspend(&pdev->dev);
370 pm_runtime_disable(&pdev->dev);
371 pm_runtime_set_suspended(&pdev->dev);
372 pm_runtime_put_noidle(&pdev->dev);
373 clocks_disable_unprepare:
374 clk_disable_unprepare(priv->gck);
375 clk_disable_unprepare(priv->mainck);
376 hclock_disable_unprepare:
377 clk_disable_unprepare(priv->hclock);
378 sdhci_pltfm_free(pdev);
382 static int sdhci_at91_remove(struct platform_device *pdev)
384 struct sdhci_host *host = platform_get_drvdata(pdev);
385 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
386 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
387 struct clk *gck = priv->gck;
388 struct clk *hclock = priv->hclock;
389 struct clk *mainck = priv->mainck;
391 pm_runtime_get_sync(&pdev->dev);
392 pm_runtime_disable(&pdev->dev);
393 pm_runtime_put_noidle(&pdev->dev);
395 sdhci_pltfm_unregister(pdev);
397 clk_disable_unprepare(gck);
398 clk_disable_unprepare(hclock);
399 clk_disable_unprepare(mainck);
404 static struct platform_driver sdhci_at91_driver = {
406 .name = "sdhci-at91",
407 .of_match_table = sdhci_at91_dt_match,
408 .pm = &sdhci_at91_dev_pm_ops,
410 .probe = sdhci_at91_probe,
411 .remove = sdhci_at91_remove,
414 module_platform_driver(sdhci_at91_driver);
416 MODULE_DESCRIPTION("SDHCI driver for at91");
417 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
418 MODULE_LICENSE("GPL v2");