2 * Atmel SDMMC controller driver.
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
21 #include <linux/kernel.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/slot-gpio.h>
24 #include <linux/module.h>
26 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
30 #include "sdhci-pltfm.h"
32 #define SDMMC_MC1R 0x204
33 #define SDMMC_MC1R_DDR BIT(3)
34 #define SDMMC_MC1R_FCD BIT(7)
35 #define SDMMC_CACR 0x230
36 #define SDMMC_CACR_CAPWREN BIT(0)
37 #define SDMMC_CACR_KEY (0x46 << 8)
39 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
41 struct sdhci_at91_priv {
48 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
52 mc1r = readb(host->ioaddr + SDMMC_MC1R);
53 mc1r |= SDMMC_MC1R_FCD;
54 writeb(mc1r, host->ioaddr + SDMMC_MC1R);
57 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
60 unsigned long timeout;
62 host->mmc->actual_clock = 0;
65 * There is no requirement to disable the internal clock before
66 * changing the SD clock configuration. Moreover, disabling the
67 * internal clock, changing the configuration and re-enabling the
68 * internal clock causes some bugs. It can prevent to get the internal
69 * clock stable flag ready and an unexpected switch to the base clock
72 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
73 clk &= SDHCI_CLOCK_INT_EN;
74 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
79 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
81 clk |= SDHCI_CLOCK_INT_EN;
82 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
86 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
87 & SDHCI_CLOCK_INT_STABLE)) {
89 pr_err("%s: Internal clock never stabilised.\n",
90 mmc_hostname(host->mmc));
97 clk |= SDHCI_CLOCK_CARD_EN;
98 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
102 * In this specific implementation of the SDHCI controller, the power register
103 * needs to have a valid voltage set even when the power supply is managed by
104 * an external regulator.
106 static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
109 if (!IS_ERR(host->mmc->supply.vmmc)) {
110 struct mmc_host *mmc = host->mmc;
112 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
114 sdhci_set_power_noreg(host, mode, vdd);
117 void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, unsigned int timing)
121 if (timing == MMC_TIMING_MMC_DDR52) {
122 mc1r = sdhci_readb(host, SDMMC_MC1R);
123 mc1r |= SDMMC_MC1R_DDR;
124 sdhci_writeb(host, mc1r, SDMMC_MC1R);
126 sdhci_set_uhs_signaling(host, timing);
129 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
131 sdhci_reset(host, mask);
133 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
134 || mmc_gpio_get_cd(host->mmc) >= 0)
135 sdhci_at91_set_force_card_detect(host);
138 static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
139 .set_clock = sdhci_at91_set_clock,
140 .set_bus_width = sdhci_set_bus_width,
141 .reset = sdhci_at91_reset,
142 .set_uhs_signaling = sdhci_at91_set_uhs_signaling,
143 .set_power = sdhci_at91_set_power,
146 static const struct sdhci_pltfm_data soc_data_sama5d2 = {
147 .ops = &sdhci_at91_sama5d2_ops,
150 static const struct of_device_id sdhci_at91_dt_match[] = {
151 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
154 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
156 static int sdhci_at91_set_clks_presets(struct device *dev)
158 struct sdhci_host *host = dev_get_drvdata(dev);
159 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
160 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
162 unsigned int caps0, caps1;
163 unsigned int clk_base, clk_mul;
164 unsigned int gck_rate, real_gck_rate;
165 unsigned int preset_div;
168 * The mult clock is provided by as a generated clock by the PMC
169 * controller. In order to set the rate of gck, we have to get the
170 * base clock rate and the clock mult from capabilities.
172 clk_prepare_enable(priv->hclock);
173 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
174 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
175 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
176 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
177 gck_rate = clk_base * 1000000 * (clk_mul + 1);
178 ret = clk_set_rate(priv->gck, gck_rate);
180 dev_err(dev, "failed to set gck");
181 clk_disable_unprepare(priv->hclock);
185 * We need to check if we have the requested rate for gck because in
186 * some cases this rate could be not supported. If it happens, the rate
187 * is the closest one gck can provide. We have to update the value
190 real_gck_rate = clk_get_rate(priv->gck);
191 if (real_gck_rate != gck_rate) {
192 clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
193 caps1 &= (~SDHCI_CLOCK_MUL_MASK);
194 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) &
195 SDHCI_CLOCK_MUL_MASK);
196 /* Set capabilities in r/w mode. */
197 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN,
198 host->ioaddr + SDMMC_CACR);
199 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
200 /* Set capabilities in ro mode. */
201 writel(0, host->ioaddr + SDMMC_CACR);
202 dev_info(dev, "update clk mul to %u as gck rate is %u Hz\n",
203 clk_mul, real_gck_rate);
207 * We have to set preset values because it depends on the clk_mul
208 * value. Moreover, SDR104 is supported in a degraded mode since the
209 * maximum sd clock value is 120 MHz instead of 208 MHz. For that
210 * reason, we need to use presets to support SDR104.
212 preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
213 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
214 host->ioaddr + SDHCI_PRESET_FOR_SDR12);
215 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
216 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
217 host->ioaddr + SDHCI_PRESET_FOR_SDR25);
218 preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
219 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
220 host->ioaddr + SDHCI_PRESET_FOR_SDR50);
221 preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
222 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
223 host->ioaddr + SDHCI_PRESET_FOR_SDR104);
224 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
225 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
226 host->ioaddr + SDHCI_PRESET_FOR_DDR50);
228 clk_prepare_enable(priv->mainck);
229 clk_prepare_enable(priv->gck);
234 #ifdef CONFIG_PM_SLEEP
235 static int sdhci_at91_suspend(struct device *dev)
237 struct sdhci_host *host = dev_get_drvdata(dev);
238 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
239 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
242 ret = pm_runtime_force_suspend(dev);
244 priv->restore_needed = true;
248 #endif /* CONFIG_PM_SLEEP */
251 static int sdhci_at91_runtime_suspend(struct device *dev)
253 struct sdhci_host *host = dev_get_drvdata(dev);
254 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
255 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
258 ret = sdhci_runtime_suspend_host(host);
260 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
261 mmc_retune_needed(host->mmc);
263 clk_disable_unprepare(priv->gck);
264 clk_disable_unprepare(priv->hclock);
265 clk_disable_unprepare(priv->mainck);
270 static int sdhci_at91_runtime_resume(struct device *dev)
272 struct sdhci_host *host = dev_get_drvdata(dev);
273 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
274 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
277 if (priv->restore_needed) {
278 ret = sdhci_at91_set_clks_presets(dev);
282 priv->restore_needed = false;
286 ret = clk_prepare_enable(priv->mainck);
288 dev_err(dev, "can't enable mainck\n");
292 ret = clk_prepare_enable(priv->hclock);
294 dev_err(dev, "can't enable hclock\n");
298 ret = clk_prepare_enable(priv->gck);
300 dev_err(dev, "can't enable gck\n");
305 return sdhci_runtime_resume_host(host);
307 #endif /* CONFIG_PM */
309 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
310 SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume)
311 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
312 sdhci_at91_runtime_resume,
316 static int sdhci_at91_probe(struct platform_device *pdev)
318 const struct of_device_id *match;
319 const struct sdhci_pltfm_data *soc_data;
320 struct sdhci_host *host;
321 struct sdhci_pltfm_host *pltfm_host;
322 struct sdhci_at91_priv *priv;
325 match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
328 soc_data = match->data;
330 host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
332 return PTR_ERR(host);
334 pltfm_host = sdhci_priv(host);
335 priv = sdhci_pltfm_priv(pltfm_host);
337 priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
338 if (IS_ERR(priv->mainck)) {
339 dev_err(&pdev->dev, "failed to get baseclk\n");
340 ret = PTR_ERR(priv->mainck);
341 goto sdhci_pltfm_free;
344 priv->hclock = devm_clk_get(&pdev->dev, "hclock");
345 if (IS_ERR(priv->hclock)) {
346 dev_err(&pdev->dev, "failed to get hclock\n");
347 ret = PTR_ERR(priv->hclock);
348 goto sdhci_pltfm_free;
351 priv->gck = devm_clk_get(&pdev->dev, "multclk");
352 if (IS_ERR(priv->gck)) {
353 dev_err(&pdev->dev, "failed to get multclk\n");
354 ret = PTR_ERR(priv->gck);
355 goto sdhci_pltfm_free;
358 ret = sdhci_at91_set_clks_presets(&pdev->dev);
360 goto sdhci_pltfm_free;
362 priv->restore_needed = false;
364 ret = mmc_of_parse(host->mmc);
366 goto clocks_disable_unprepare;
368 sdhci_get_of_property(pdev);
370 pm_runtime_get_noresume(&pdev->dev);
371 pm_runtime_set_active(&pdev->dev);
372 pm_runtime_enable(&pdev->dev);
373 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
374 pm_runtime_use_autosuspend(&pdev->dev);
376 /* HS200 is broken at this moment */
377 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
379 ret = sdhci_add_host(host);
381 goto pm_runtime_disable;
384 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
385 * the assumption that all the clocks of the controller are disabled.
386 * It means we can't get irq from it when it is runtime suspended.
387 * For that reason, it is not planned to wake-up on a card detect irq
388 * from the controller.
389 * If we want to use runtime PM and to be able to wake-up on card
390 * insertion, we have to use a GPIO for the card detection or we can
391 * use polling. Be aware that using polling will resume/suspend the
392 * controller between each attempt.
393 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
394 * to enable polling via device tree with broken-cd property.
396 if (mmc_card_is_removable(host->mmc) &&
397 mmc_gpio_get_cd(host->mmc) < 0) {
398 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
399 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
403 * If the device attached to the MMC bus is not removable, it is safer
404 * to set the Force Card Detect bit. People often don't connect the
405 * card detect signal and use this pin for another purpose. If the card
406 * detect pin is not muxed to SDHCI controller, a default value is
407 * used. This value can be different from a SoC revision to another
408 * one. Problems come when this default value is not card present. To
409 * avoid this case, if the device is non removable then the card
410 * detection procedure using the SDMCC_CD signal is bypassed.
411 * This bit is reset when a software reset for all command is performed
412 * so we need to implement our own reset function to set back this bit.
414 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
416 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
417 || mmc_gpio_get_cd(host->mmc) >= 0)
418 sdhci_at91_set_force_card_detect(host);
420 pm_runtime_put_autosuspend(&pdev->dev);
425 pm_runtime_disable(&pdev->dev);
426 pm_runtime_set_suspended(&pdev->dev);
427 pm_runtime_put_noidle(&pdev->dev);
428 clocks_disable_unprepare:
429 clk_disable_unprepare(priv->gck);
430 clk_disable_unprepare(priv->mainck);
431 clk_disable_unprepare(priv->hclock);
433 sdhci_pltfm_free(pdev);
437 static int sdhci_at91_remove(struct platform_device *pdev)
439 struct sdhci_host *host = platform_get_drvdata(pdev);
440 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
441 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
442 struct clk *gck = priv->gck;
443 struct clk *hclock = priv->hclock;
444 struct clk *mainck = priv->mainck;
446 pm_runtime_get_sync(&pdev->dev);
447 pm_runtime_disable(&pdev->dev);
448 pm_runtime_put_noidle(&pdev->dev);
450 sdhci_pltfm_unregister(pdev);
452 clk_disable_unprepare(gck);
453 clk_disable_unprepare(hclock);
454 clk_disable_unprepare(mainck);
459 static struct platform_driver sdhci_at91_driver = {
461 .name = "sdhci-at91",
462 .of_match_table = sdhci_at91_dt_match,
463 .pm = &sdhci_at91_dev_pm_ops,
465 .probe = sdhci_at91_probe,
466 .remove = sdhci_at91_remove,
469 module_platform_driver(sdhci_at91_driver);
471 MODULE_DESCRIPTION("SDHCI driver for at91");
472 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
473 MODULE_LICENSE("GPL v2");